ICHAUS IC-MR

preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 1/44
FEATURES
APPLICATIONS
♦ Fast 13-bit sine-to-digital conversion within 2 µs
♦ Precision PGA for differential and single-ended signals of
up to 500 kHz
♦ Voltage or current input mode with signal monitoring
♦ Adjustable signal conditioning for offset, amplitude, and phase
♦ Input signal stabilization through LED or MR bridge current
control of up to 50 mA
♦ 8-bit parallel and serial I/O interfaces (BiSS, SSI, and SPI)
♦ Absolute data interface (ADI: BiSS/SSI) for position preset
♦ Period counter of up to 50 bits with selectable
singleturn/multiturn splitting
♦ Position data preset using ST/MT offset registers
♦ 12-bit A/D converter for temperature sensing
♦ Special functions for safety applications (signal monitoring, life
counter, and extended CRC)
♦ Current-limited, differential 1 Vpp sine/cosine outputs to 100 Ω
♦ Device configurable through I/O interfaces or a serial
EEPROM
♦ Single-sided 5 V operation from -40 to +110 °C
♦ Fast position decoding for
safety-oriented encoder systems
♦ Motor feedback systems
PACKAGES
QFN48 7x7
BLOCK DIAGRAM
TMS
PSI
T0
T1
T2
ACO
VDD
SIGNAL CONDITIONING
Conditioning
U/U
VDDA
PSO
I/ U
NSI
I/ U
VREF
PCI
NSO
Conditioning
U/U
Amplitude
Control
2
2
Filter
SIN + COS = 1
Conditioning
U/U
PCO
I/ U
NCI
NCO
Conditioning
U/U
I/ U
ASLI
AMAO
ABSOLUTE DATA
INTERFACE
iC-MR
SCL
SDA
(ADI)
PERIOD COUNTER
INTERPOLATOR
37...34-bit
13-bit
EEPROM
INTERFACE
SAFETY
RESET
NERR
FEATURES
OFFSET
NRES
REGISTER
Configuration / CRC
Error Monitor
Life Counter
SERIAL I/O INTERFACE
PARALLEL I/O INTERFACE
D7 D6 D5 D4 D3 D2 D1 D0
Copyright © 2013 iC-Haus
BiSS
NWR
NRD
NL NCS
MAI
SSI
SLO
12-bit
SPI
SLI
ADC
A/D CONVERTER
GND
GNDA
http://www.ichaus.com
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 2/44
DESCRIPTION
Device iC-MR is a universal sine-to-digital converter
with signal conditioning and various interfaces for
configuration and data communication. Microcontrollers can be connected up through a parallel I/O
interface with an 8-bit bus width (12.5 MHz) or using
a serial I/O interface (4-pin SPI, 20 MHz). The serial
I/O interface can function as a sensor interface either
in BiSS C protocol (up to 10 MHz, bidirectional) or in
SSI protocol (up to 4 MHz).
In the analog signal path iC-MR has precision input
amplifiers with an adjustable gain for differential or
referenced voltage signals of 10 mV peak to 1 V peak
or for current signals of approx. 10 µA to 300 µA (input pins PSI, NSI, PCI, and NCI). A separate measurement input (VREF) enables signals to be referenced to the sensor’s reference voltage.
The downstream signal conditioning unit can compensate for typical sine/cosine sensor signal errors,
such as offset, amplitude, and phase errors. The
conditioned signals are filtered and output through
analog line drivers with an amplitude of typically
250 mV (output pins PSO, NSO, PCO, and NCO). A
differential 1 Vpp signal to 100 Ω is available for line
transmission.
A control signal is gained from the conditioned signals to stabilize the sine/cosine output signals. This
can adjust the transmitting LED of optical encoder
systems using the integrated 50 mA driver stage (output ACO). With magnetic sensors this driver output
supplies the MR measuring bridges or can be used
to feedback the bridge supply voltage. By tracking
the sensor supply, sensor temperature and ageing effects are compensated for, the input signals are stabilized, and precise calibration of the input signals is
maintained. This makes a constant interpolation accuracy possible across the entire operating temperature range.
At the same time the sensor is monitored for proper
functioning. The amplitude and offset of the input signals at pins PSI, NSI, PCI, and NCI are checked, enabling wire-breakage or short circuits to be detected.
The control unit operating limits are also monitored
so that an alarm can be signaled through the I/O interface and/or at error output NERR, depending on
the configuration, with dirt or ageing of optical systems.
Sine-to-digital conversion is performed by a fast interpolator with a sample-&-hold circuit which resolves a
sine period with 13 bits either continuously or on request. In parallel and independent of the interpolator a configurable 37-bit period counter logs the sine
and cosine zero crossings. This period counter is
programmable and can take its start value from the
serial absolute data interface (ADI); the corresponding interface master operates either in BiSS C or SSI
protocol.
For position measurement applications iC-MR differentiates between multiturn and singleturn data using
a selectable intersection on the period counter. The
position can be corrected accordingly using the multiturn and singleturn offset values.
An integrated 12-bit A/D converter digitizes linear
measurement voltages at pin ADC for the evaluation
of KTY temperature sensors, for example. Measurement of the calibratable converter is observed by settable threshold values so that a permissible operating
temperature range with a lower and upper temperature threshold can be monitored.
After power-on iC-MR collects its CRC protected
configuration data from an external I2 C-EEPROM or
waits for the configuration from one of the I/O interfaces. An undervoltage reset zeroes internal registers and is shown as a reset pulse at pin NRES,
which also serves as a reset input (low active).
Errors can always be masked and allocated to an
error byte (and displayed at error message output
NERR) or a warning byte. The internal status registers are available to the I/O interfaces which have a
number of different commands (software reset, memory verification, and error simulation).
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 3/44
CONTENTS
PACKAGING INFORMATION
PIN CONFIGURATION QFN48-7x7
(topview) . . . . . . . . . . . . . . . . .
4
Acquiring position data . . . . . . . . . . . . .
28
4
ABSOLUTE MAXIMUM RATINGS
5
THERMAL DATA
5
EEPROM INTERFACE
Address range . . . . . . . . . . . . . . . . .
Accessing external memory banks . . . . . .
Startup and selection of I/O interface . . . . .
29
29
30
30
ELECTRICAL CHARACTERISTICS
6
PARALLEL I/O INTERFACE
Reading out registers . . . . . . . . . . . . .
Writing to registers . . . . . . . . . . . . . . .
Reading out position data . . . . . . . . . . .
31
31
31
31
SERIAL I/O INTERFACE: BiSS C
Configuration . . . . . . . . . .
Register communication . . . .
Commands . . . . . . . . . . .
Configuration examples . . . .
.
.
.
.
34
34
35
35
35
OPERATING CONDITIONS:
PARALLEL I/O INTERFACE
11
OPERATING CONDITIONS:
SERIAL I/O INTERFACE
12
CONFIGURATION PARAMETERS
14
REGISTER MAP
15
OPERATING MODES
Calibration modes . . . . . . . . . . . . . . .
18
18
SERIAL I/O INTERFACE: SSI
Configuration . . . . . . . . . . . . . . . . . .
Configuration examples . . . . . . . . . . . .
36
36
36
BIAS CURRENT SOURCE AND SIGNAL
FILTER
Bias current source . . . . . . . . . . . . . . .
Signal filter . . . . . . . . . . . . . . . . . . .
18
18
18
SERIAL I/O INTERFACE: SPI
Register access . . . . . . . . . . . . . . . .
Cyclic readout . . . . . . . . . . . . . . . . .
37
37
37
SIGNAL CONDITIONING
Input configuration . . . . . . .
Gain settings SIN and COS . .
Offset calibration SIN and COS
Phase correction SIN vs. COS
Diagnostic data . . . . . . . . .
19
19
20
20
21
22
ABSOLUTE DATA INTERFACE (ADI)
37
40
40
40
41
41
42
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
AMPLITUDE CONTROL
23
SAFETY FEATURES
CRC Verification . . . . . . .
Safety register . . . . . . . .
Status and command register
Error mask . . . . . . . . . .
Life counter . . . . . . . . . .
12-BIT A/D CONVERTER
24
DESIGN REVIEW: Application notes
43
INTERPOLATOR AND CYCLE COUNTER
26
REVISION HISTORY
43
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 4/44
PACKAGING INFORMATION
PIN CONFIGURATION QFN48-7x7
(topview)
PIN FUNCTIONS
No. Name Function
1 ACO Signal Level Controller, high-side current
source output
2 VDDA +5V Supply Voltage, analog
3 GNDA Ground, analog
4 PSO Sine Output
5 NSO Sine Output, inverted
6 PCO Cosine Output
7 NCO Cosine Output, inverted
8 NERR Error Signal, input/indication output*
9 VDD +5V Supply Voltage, digital
10 GND Ground, digital
11 SDA EEPROM Interface, data line I2 C
12 SCL EEPROM Interface, clock line I2 C
PIN FUNCTIONS
No. Name Function
13 D7
Par. Interface, data line
14 D6
Par. Interface, data line
15 D5
Par. Interface, data line
16 D4
Par. Interface, data line
17 D3
Par. Interface, data line
18 D2
Par. Interface, data line
19 D1
Par. Interface, data line
20 D0
Par. Interface, data line
21 NWR Par. Interface, write signal*
22 NRD Par. Interface, read signal*
23 NL
Par. Interface, storage signal*
Ser. Interface, data acquisition*
24 NCS Par. Interface, chip select*
Ser. Interface, chip select*
25 MAI
Ser. Interface, clock input
26 SLO Ser. Interface, data output
27 SLI
Ser. Interface, data input
28 ASLI Absolute Data Interface, data input
29 AMAO Absolute Data Interface, clock output
30 TMS Test Mode Selection Input
31 NRES Reset Signal, input/indication output*
32 n.c.
33 T2
Test Pin
34 n.c.
35 ADC 12-bit ADC Input, temperature sensor
36 n.c.
37 T0
Test Pin
38 T1
Test Pin
39 n.c.
40 NSI
Sine Input, inverted
41 PSI
Sine Input
42 VREF Reference Voltage, input/output
43 PCI
Cosine Input
44 NCI
Cosine Input, inverted
45 n.c.
46 n.c.
47 n.c.
48 n.c.
n.c.:
Pin is not connected.
*) Pin is low active.
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 5/44
ABSOLUTE MAXIMUM RATINGS
Beyond these values damage may occur; device operation is not guaranteed.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 VDDA
Voltage at VDDA
-0.3
6
V
G002 VDD
Voltage at VDD
-0.3
6
V
G003 V()
Voltage at ACO, PSO, NSO, PCO,
NCO, NERR, SDA, SCL, D(7...0),
NWR, NRD, NL, NCS, MAI, SLO, SLI,
ASLI, AMAO, TMS, NRES, ADC, PSI,
NSI, VREF, PCI, NCI
-0.3
VDDA
+0.3
V
G004 I(VDDA)
Current in VDDA
-100
400
mA
G005 I(VDD)
Current in VDD
-100
100
mA
G006 Vd()
ESD Susceptibility at all pins
2
kV
G007 Tj
Chip Temperature
-40
150
°C
G008 Ts
Storage Temperature
-40
150
°C
HBM 100 pF discharged through 1.5 kΩ, all
pins versus GNDA
THERMAL DATA
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
T01
Ta
Operating Ambient Temperature Range package QFN48
T02
Rthja
Thermal Resistance
Chip to Ambient
QFN48 soldered to PCB according to
JEDEC 51
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
Typ.
-40
Max.
110
30
°C
K/W
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 6/44
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
4.5
5
5.5
V
General
001
VDDA,
VDD
Permissible Supply Voltage
002
I(VDDA)
VDDA Supply Current
25
50
mA
003
004
I(VDD)
VDD Supply Current
5
50
mA
Vc()hi
005
Vc()hi
Clamp Voltage hi
at digital inputs ASLI, SLI, MAI,
NCS, NL, NRD, NWR, NRES,
NERR, SDA, SCL, TMS
Clamp Voltage hi
at digital inputs D(7...0)
006
Vcz()hi
Clamp Voltage hi
I() = 4 mA
at ACO, VDDA, PSO, NSO, PCO,
NCO, AMAO, SLO, ADC, PSI,
NSI, VREF, PCI, NCI
007
Vc()lo
Clamp Voltage lo
I() = -4 mA
at ACO, VDDA, PSO, NSO, PCO,
NCO, AMAO, SLO, ADC, PSI,
NSI, VREF, PCI, NCI
Vc()hi = V() - V(VDD),
I() = 4 mA
0.3
1.2
V
Vc()hi = V() - V(VDD),
I() = 1.6 mA
0.3
1.2
V
11
V
-0.3
V
-1.2
Bias Current Source, Reference Voltages, Input/Output VREF
101
IBP
Bias Current Source
IBP calibrated to 200 µA
102
VPAH
Reference Voltage VPAH
referenced to GNDA
92.5
100
107.5
%
45
50
55
%VDDA
103
104
V05
Reference Voltage V05
VREFI
Internal Ref. Voltage VREFI
DCPOS = 1
DCPOS = 0
450
500
550
mV
1.35
2.25
1.5
2.5
1.65
2.75
V
V
105
Vin()
Permissible Input Voltage at
VREF
SELREF = 0x3
0.5
VDDA
−2
V
106
Rin()
Input Resistance at VREF
SELREF = 0x3, REFVOS = 0x3, UIN = 1,
TUIN = 0, Rin() referenced to VREFin()
20
30
kΩ
107
Vref()out
Output Voltage at VREF
SELREF = 0x2, I() = 0
108
I0()
Leakage Current at VREF
SELREF = 0x0 or 0x1
26
100
-1
%VREFI
+1
µA
12-bit A/D Converter, Measuring Input ADC
601
RESOadc
A/D Converter Resolution
12
bit
602
603
t()adc
A/D Conversion Time
1.1
ms
Vin()FS
Maximum Full Scale Input
Voltage
2.5
2.0
V
V
604
INL()
A/D Conversion Nonlinearity
ADCSLOP = 0xFF
ADCSLOP = 0x00
Signal Conditioning, Inputs: PSI, NSI, PCI, NCI
701 Vin()sig
Permissible V Mode Input Voltage UIN = 1, TUIN = 0
0.75
UIN = 1, TUIN = 1, DCPOS = 1
-0.1
702
Iin()
V Mode Input Current
UIN = 1, TUIN = 0
-100
703
704
Rin()
V Mode Input Resistance
UIN = 1, TUIN = 1, vs. VREFin, Tj = 27 °C,
16.4
Iin()sig
Permissible I Mode Input Current UIN = 0, DCPOS = 0
UIN = 0, DCPOS = 1
705
706
CTR()sig
Permissible Signal Contrast Ratio current ratio of Iin()pkpk vs. Iin()dc
Rin()
I Mode Input Resistance
707
TC(Rin)
Temperature Coefficient of Rin
708
Vin()os
Offset Voltage of Input Stage
Tj = 27 °C, vs. VREFin;
UIN = 0, RIN = 00
UIN = 0, RIN = 01
UIN = 0, RIN = 10
UIN = 0, RIN = 11
±0.95
LSB
VDDA
− 1.5
VDDA
+ 0.1
V
100
nA
23.6
kΩ
-300
10
-10
300
µA
µA
0.125
1
1.1
1.6
2.2
3.2
20
1.6
2.3
3.2
4.6
2.1
3.0
4.2
6.0
0.15
referenced to side of input;
GR = 0x4, GFC = 0x1F, GFS = 0x7C0
V
kΩ
kΩ
kΩ
kΩ
%/K
300
µV
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 7/44
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.
Item
No.
709
Symbol
Parameter
Conditions
Unit
Min.
Vin()diff
Recommended Differential Input Vin()diff = V(PSI) − V(NSI), respectively
Vin()diff = V(PCI) − V(NCI);
Voltage
TUIN = 0
TUIN = 1
Typ.
20
80
Max.
1000
4000
710
Vcore()
Recommended Internal Signal
Level
G * Vin()diff, MODE = 0x01
711
GF, GC
Selectable Gain Factors
TUIN = 0
TUIN = 1
712
∆GFdiff
Differential Gain Accuracy
referenced to fine gain range (GFS, GFC)
-1
1
LSB
713
∆GFabs
Absolute Gain Accuracy
referenced to fine gain range (GFS, GFC),
guaranteed range of monotony
-20
20
LSB
714
715
∆GRabs
Gain Accuracy
referenced to coarse gain range (GR)
-8
8
%
VOScal1
Offset Calibration Range
measured at output, source V(ACO) = 3 V,
REFVOS = 00, MODE =0x01;
ORS, ORC = 00
ORS, ORC = 01
ORS, ORC = 10
ORS, ORC = 11
±450
±900
±2700
±5400
mV
mV
mV
mV
measured at output, source V05,
REFVOS = 01, MODE = 0x01;
ORS, ORC = 00
ORS, ORC = 01
ORS, ORC = 10
ORS, ORC = 11
±1500
±3000
±9000
±18000
mV
mV
mV
mV
measured at output, source V025,
REFVOS = 10, MODE = 0x01;
ORS, ORC = 00
ORS, ORC = 01
ORS, ORC = 10
ORS, ORC = 11
±750
±1500
±4500
±9000
mV
mV
mV
mV
measured at output, source VDC = 125 mV,
REFVOS = 11, MODE = 0x01;
ORS, ORC = 00
ORS, ORC = 01
ORS, ORC = 10
ORS, ORC = 11
±375
±750
±2250
±4500
mV
mV
mV
mV
716
717
718
VOScal2
VOScal3
VOScal4
Offset Calibration Range
Offset Calibration Range
Offset Calibration Range
6
mVpp
mVpp
2
0.5
Vpp
100
25
719
∆VOSdiff
Differential Linearity Error of
Offset Correction
-0.5
0.5
LSB
720
∆VOSint
Integral Linearity Error of Offset
Correction
-100
100
LSB
721
PHIcal
Phase Correction Range
722
∆PHIdiff
Differential Linearity Error of
Phase Correction
-0.25
0.25
LSB
723
∆PHIint
Integral Linearity Error of Phase
Correction
-20
20
LSB
724
fin()max
Permissible Input Frequency
725
fhc()
Input Amplifier Cut-off Frequency
(-3 dB)
sine vs. cosine signal
angle accuracy better 8 bit
±10.4
°
500
kHz
250
kHz
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 8/44
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Unit
Min.
Amplitude Control, Output ACO
801 Vs()hi
Saturation Voltage hi
802
Conditions
Isc()hi
Short-Circuit Current hi in ACO
Typ.
Vs()hi = VDD − V();
ACOR = 00, I() = -5 mA
ACOR = 01, I() = -10 mA
ACOR = 10, I() = -25 mA
ACOR = 11, I() = -50 mA
V() = 0 V ... VDD − 1 V;
ACOR = 00
ACOR = 01
ACOR = 10
ACOR = 11
803
804
tr()
Rise Time Current Source ACO
I(ACO): 0 % → 90 % of setpoint
tset()
Settling Time Current Source
ACO
square control active,
I(ACO): 50 % → 100 % of setpoint
805
Vscq()
Regulated Mean Target
Amplitude with Square Control
806
Vdc()
807
-10
-20
-50
-100
Max.
1
1
1
1
V
V
V
V
-5
-10
-25
-50
mA
mA
mA
mA
1
ms
400
µs
Vscq() = Vpp(V(PSO) - V(NSO)), respectively
Vscq() = Vpp(V(PCO) - V(NCO));
ACOC = 0x19
500
mV
Regulated Mean Setpoint with
Sum Control
ACOD = 0x00
ACOD = 0x7F
166
551
mV
mV
It()min
Monitoring of ACO Output Current, lower threshold
referenced to current range ACOR
3
%Isc
808
It()max
Monitoring of ACO Output Current, upper threshold
referenced to current range ACOR
90
%Isc
809
Vt()min
Monitoring of Signal Level 1,
lower threshold
referenced to Vscq()
40
%
810
Vt()max
Monitoring of Signal Level 2,
upper threshold
referenced to Vscq()
135
%
Cut-off Frequency
ENF = 1, SELBP = 0; fin < 10 Hz
fin > 100 kHz
15
2400
kHz
kHz
Phase Shift
ENF = 1, SELBP = 0,
fin = 100 kHz for sine and cosine
1.5
°
Signal Filter
901 fc()
902
PHI()
Analog Outputs PSO, NSO, PCO and NCO
A01 Vpk()max Permissible Maximum Output
Amplitude
VDDA = 4.5 V, DC level VDDA/2,
RL = 50 Ω vs. VDDA/2
250
300
mV
275
mV
A02
Vpk()
Output Amplitude with Sensor
Tracking by Output ACO
ACOC = 0x19
225
A03
fc
Cut-off Frequency
CL = 250 pF
500
A04
Vos
Output Offset Voltage
A05
Isc()hi
Short-Circuit Current hi
V() = 0 V
-40
-20
-15
A06
Isc()lo
Short-Circuit Current lo
V() = VDD
15
20
40
A07
SR()
Slew Rate
RLdiff = 100 Ω, CL = 25 pF
5
A08
Rout()
Test Signal Source Resistance
MODE = 0x01 (Analog 1)
5
A09
fout()cal
Permissible Test Signal Output
Frequency
MODE = 0x01 (Analog 1), CL = 200 pF
kHz
±200
µV
mA
mA
V/µs
kΩ
2
kHz
Signal Level Monitoring
B01
Vpp()max
Signal Level Monitoring,
upper threshold
referenced to target amplitude of converter and
analog output, see Figure 1
110
150
%Vpp
B02
Vpp()min
Signal Level Monitoring,
lower threshold
referenced to target amplitude of converter and
analog output, see Figure 1
10
50
%Vpp
B03
Vpp()hys
Signal Level Monitoring,
Hysteresis
referenced to Vpp()min, Vpp()max
B04
Vdc()max
Mean Value Monitoring,
upper threshold
referenced to VPAH, see Figure 2
B05
Vdc()min
Mean Value Monitoring,
lower threshold
referenced to VPAH, see Figure 2
30
mV
120
140
%VPAH
50
70
%VPAH
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 9/44
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
13-bit Interpolator
C01 tipo
Conversion Time
ACQMODE = 00, see Figure 5
2
µs
C02 AAabs
Absolute Conversion Accuracy
Vpk() = 250 mV
2
LSB
Reset Input / Reset Indication Output NRES
K01
VDDon
VDD Turn-on Threshold
increasing voltage at VDD vs. GND
2.6
4.3
K02
VDDoff
VDD Turn-off Threshold
decreasing voltage at VDD vs. GND
2.3
4.0
K03
VDDhys
VDD Hysteresis
VDDhys = VDDon - VDDoff
400
K04
Vt()hi
Input Threshold Voltage hi
K05
Vt()lo
Input Threshold Voltage lo
K06
Vt()hys
Input Hysteresis
K07
Ipu()
Pull-up Current
K08
Vs()lo
Output Saturation Voltage lo
I() = 4 mA
K09
Isc()lo
Output Short-Circuit Current lo
V() = 0.4 V...VDD
V
mV
2
0.8
Vt()hys = Vt()hi - Vt()lo
V
V
V
300
500
-750
-300
4
mV
-60
µA
400
mV
80
mA
Oscillator
M01 fosc
Internal Oscillator Frequency
15
MHz
EEPROM Interface SCL, SDA
N01 Vs()lo
Saturation voltage lo
N02 Isc()
Short-Circuit Current lo
N03 Vt()hi
Input Threshold Voltage hi
N04 Vt()lo
Input Threshold Voltage lo
N05 Vt()hys
Input Hysteresis
Vt()hys = Vt()hi - Vt()lo
100
250
N06 Ipu()
Input Pull-up Current
V() = 0 V...VDD - 1 V
-750
-300
-60
N07 Vpu()
Input Pull-up Voltage
Vpu() = VDD - V(), I() = -5 µA
0.4
V
N08 fclk()
N09 tbusy()cfg
Clock Frequency at SCL
100
120
130
kHz
Duration of Configuration Phase
I() = 4 mA
4
400
mV
80
mA
2
V
0.8
IBP not adjusted;
read in of EEPROM
no EEPROM connected
V
mV
5
1
µA
ms
ms
Serial Interface MAI, SLO, SLI
O01 Vt()hi
Threshold Voltage hi at SLI, MAI
O02 Vt()lo
Threshold Voltage lo at SLI, MAI
O03 Vt()Hys
Hysteresis at SLI, MAI
O04 Ipu()
Pull-up Current at MAI
O05 Ipd()
O06 fclk()
Pull-down Current at SLI
O07 tp()
Propagation Delay at SLO versus
Clock Edge MAI
O08 tbusy()
O09 ttimeout
Processing Time
O10 Vs()hi
Saturation Voltage hi at SLO
Vs()hi = VDD - V(), I() = -4 mA
400
mV
O11 Vs()lo
Saturation Voltage lo at SLO
I() = 4 mA
400
mV
O12 Isc()hi
Short-circuit Current hi at SLO
V() = 0 V...VDD - 0.4 V
-80
-4
mA
O13 Isc()lo
Short-circuit Current lo at SLO
V() = 0.4 V...VDD
4
80
mA
2
V
Permissible Clock Frequency at
MAI
2
0.8
Vt()hys = Vt()hi - Vt()lo
V
300
500
-150
-60
-8
8
60
150
µA
4
10
10
MHz
MHz
MHz
50
ns
SSI protocol
BiSS C protocol
SPI
10
ACQMODE = 00, see Figure 5
Adaptive Timeout
V
mV
µA
t()ipo
1/fosc
1.5*tMAS
+
3/fosc
Parallel Interface D(7...0), NWR, NRD, NL, NCS
P01
Vt()hi
Threshold Voltage hi
D(7...0) as input
P02
Vt()lo
Threshold Voltage lo
D(7...0) as input
0.8
P03
Vt()hys
Input Hysteresis
D(7...0) as input, Vt()hys = Vt()hi - Vt()lo
300
500
P04
Ipu()
Pull-up Current at D(7...0)
-70
-30
V
mV
-5
µA
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 10/44
ELECTRICAL CHARACTERISTICS
Operating conditions:
VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C, unless otherwise noted.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
-150
-60
-8
µA
P05
Ipu()
Pull-up Current at NWR, NRD,
NL, NCS
P06
Vs()hi
Saturation Voltage hi
at D(7...0) Outputs
Vs()hi = VDD - V(), I() = -1.6 mA
400
mV
P07
Vs()lo
Saturation Voltage lo
at D(7...0) Outputs
I() = 1.6 mA
400
mV
P08
Isc()hi
Short-circuit Current hi
at D(7...0) Outputs
V() = 0 V...VDD - 0.4 V
-50
-1.6
mA
P09
Isc()lo
Short-circuit Current lo
at D(7...0) Outputs
V() = 0.4 V...VDD
1.6
50
mA
2
V
Absolute Data Interface ASLI, AMAO
Q01 Vt()hi
Threshold Voltage hi at ASLI
Q02 Vt()lo
Threshold Voltage lo at ASLI
Q03 Vt()hys
Hysteresis at ASLI
Q04 Ipu()
Pull-up Current at ASLI
Q05 Vs()hi
Saturation Voltage hi at AMAO
Vs()hi = VDD - V(), I() = -1.6 mA
Q06 Vs()lo
Saturation Voltage lo at AMAO
I() = 1.6 mA
Q07 Isc()hi
Short-circuit Current hi at AMAO V() = 0 V...VDD - 0.4 V
-50
Q08 Isc()lo
Q09 fclk()
Short-circuit Current lo at AMAO V() = 0.4 V...VDD
1.6
50
mA
0.8
Vt()hys = Vt()hi - Vt()lo
Clock Frequency at AMAO
V
300
500
-150
-60
GET_ADI = 0, SSI_ADI = 1 (SSI protocol)
GET_ADI = 0, SSI_ADI = 0 (BiSS C protocol)
mV
-8
µA
400
mV
400
mV
-1.6
mA
1/16
1/2
fosc
fosc
Error Signal Input/Output NERR
R01 Vt()hi
Threshold Voltage hi
R02 Vt()lo
Threshold Voltage lo
2
R03 Vt()hys
Input Hysteresis
R04 Ipu()
Pull-up Current
R05 Vs()lo
Saturation Voltage lo
I() = 4 mA
R06 Isc()lo
Short-circuit Current lo
V() = 0.4 V...VDD
0.8
Vt()hys = Vt()hi - Vt()lo
V
V
100
150
-750
-300
4
mV
-60
µA
400
mV
60
mA
1 Vpp
V(PSIN) - V(NSIN)
90°
V(PCOS) - V(NCOS)
VDDA
Vdc()max
180°
φ
0°
270°
0°
90°
180°
270°
360°
V(PSIN)
V(PCOS)
V(NSIN)
V(NCOS)
Vdc()min
Vpp()min
Vpp()max
Figure 1: Differential voltage thresholds for maximum
and minimum alarm
0V
Figure 2: Maximum and minimum voltage thresholds
for DC check
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 11/44
OPERATING CONDITIONS: PARALLEL I/O INTERFACE
Operating conditions: VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA, Tj = -40...125 °C
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
I001 ts AW
Setup Time:
addresses stable before NWR hi → lo
50
ns
I002 th WA
Hold Time:
addresses stable after NWR lo → hi
50
ns
I003 ts DW
Setup Time:
data stable before NWR hi → lo
50
ns
I004 th WD
Hold Time:
data stable after NWR lo → hi
50
ns
I005 tWL
Signal Duration:
NWR at low level
80
ns
I006 tRL
Signal Duration:
NRD at low level
80
ns
I007 tp RD1
Propagation Delay:
data stable after NRD hi → lo
50
ns
I008 tp RD2
Propagation Delay:
data bus high ohmic after NRD lo → hi
80
ns
I009 tWW
Signal Duration:
between NWR lo → hi and hi → lo
80
ns
I010 tWR
Signal Duration:
between NWR lo → hi and NRD hi → lo
or NRD lo → hi and NWR hi → lo
80
ns
I011 tRR
Signal Duration:
between NRD lo → hi and hi → lo
80
ns
I012 tCL
Signal Duration:
between NCS hi → lo and NRD hi → lo
or NCS hi → lo und NWR hi → lo
80
ns
I013 tCH
Signal Duration:
between NRD lo → hi and NCS lo → hi
80
ns
CL = 10 pF
NCS
tCH
tCL
D(7:0)
ADDRESS
DATA_IN
thAW
tsAW
tsDW
DATA_OUT
thDW
tpRD1
tpRD2
NWR
tWL
tWW
tWR
NRD
tRL
Figure 3: Parallel interface timing.
tRR
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 12/44
OPERATING CONDITIONS: SERIAL I/O INTERFACE
Operating conditions: VDDA = VDD = 4.5...5.5 V, GNDA = GND = 0 V, IBP calibrated to 200 µA Tj = -40...125 °C
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
SSI protocol (INTCFG = 00, NESSI = 0)
I111 tMAS
Permissible Clock Period
250
ns
I112 tMASh
Clock Signal Hi Level Duration
125
ns
I113 tMASl
Clock Signal Lo Level Duration
125
ns
I114 treq
REQ Signal Lo Level Duration
125
ns
BiSS C protocol (INTCFG = 00, NESSI = 1)
I115 tMAS
Permissible Clock Period
100
ns
I116 tMASh
Clock Signal Hi Level Duration
50
ns
I117 tMASl
Clock Signal Lo Level Duration
50
ns
SPI protocol (INTCFG = 10)
I118 tMAS
Permissible Clock Period
100
ns
I119 tMASh
Clock Signal Hi Level Duration
50
ns
I120 tMASl
Clock Signal Lo Level Duration
50
ns
I121 tCL
Signal Duration:
between NCS hi → lo and MAI hi → lo
50
ns
I122 tCH
Signal Duration:
between MAI lo → hi and NCS lo → hi
50
ns
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 13/44
treq
MAI
tMAS
REQ
SLO
DATA
DATA
tMASh tMASl
DATA
DATA
ttimeout
tpMASLO
Figure 4: SSI protocol timing.
MAI
SLO
START
DATA
DATA
tbusy
Figure 5: BiSS C protocol timing with conversion time t()IPO (ACQMODE = 00)
tMAS
MAI
SLO
START
tMASh tMASl
DATA
tpMASLO
DATA
ttimeout
ttimeout
Figure 6: BiSS C protocol timing without conversion time t()IPO (ACQMODE 6= 00)
NCS
MAI
SLI
SLO
tMAS
tCL
tMASh tMASl
Figure 7: SPI protocol timing.
tCH
iC-MR 13-BIT S&H SIN/COS
preliminary
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 14/44
CONFIGURATION PARAMETERS
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
MODE
Operating mode
Bias Current Source and Filter . . . . . . . . . . . . page 18
CFGBIAS
Bias calibration
ENF
Signal filter activation
SELBP
Signal filter cut-off frequency
NEFDR
Signal filter dead band
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . page 19
INMODE
Input mode
differential/single-ended
UIN
Current/voltage operation
RIN
Input resistance
TUIN
Input voltage divider
DCPOS
Reference voltage input
SELREF
Input reference voltage selection
GR
Coarse gain
GFS
Fine gain sine
GFC
Fine gain cosine
REFVOS
Offset reference source
MPS
Center potential sine
MPC
Center potential cosine
ORS
Offset adjustment range sine
ORC
Offset adjustment range cosine
OFS
Offset adjustment sine
OFC
Offset adjustment cosine
PH
Phase correction sin/cos
DIAG
Diagnosis register
Amplitude Control . . . . . . . . . . . . . . . . . . . . . . . . Page 23
ACOT
ACO Output control mode
ACOR
ACO Output current range
ACOC
Setpoint square control (amplitude)
ACOD
Setpoint sum control (DC value)
LCMODE
Control mode
12 bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . Page 24
ADCSLOP
Maximum ADC input voltage
ADCOFF
Digital temperature offset
TEMPHI
Upper temperature threshold
TEMPLO
Lower temperature threshold
Interpolator and Cycle Counter . . . . . . . . . . . Page 26
CODERES
Cycle counter resolution
DIR
Code inversion
MTOFF
Multiturn offset
STOFF
Singleturn offset
STRESO
Singleturn resolution
MTRESO
Multiturn resolution
ACQMODE
Position data acquisition
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . Page 29
CFG_E2P
EDS range selection
BSEL
Bank selection
INTCFG
Interface selection
Parallel I/O Interface . . . . . . . . . . . . . . . . . . . . . . Page 31
FULL_CYC
Cyclic telegram length
Serial I/O Interface: BiSS C . . . . . . . . . . . . . . . Page 34
NESSI
SSI protocol selection
ENLC
Life counter enable
ENXCRC
CRCS
TMPSCD
Extended CRC protection
CRC start value
Temperature data enable (BiSS)
Serial I/O Interface: SSI . . . . . . . . . . . . . . . . . . . Page 36
NESSI
SSI protocol selection
SSIRING
SSI ring mode selection
SSIERR
SSI with error bit
SSIMODE
SSI protocol options
Serial I/O Interface: SPI . . . . . . . . . . . . . . . . . . . Page 37
Absolute Data Interface (ADI) . . . . . . . . . . . . . Page 38
STP_ADI
Startup with absolute data
CYC_ADI
Cyclic reading of absolute data
DL_ADI
Data length absolute data interface
SYNC_ADI
Synchronisation bits absolute data interface
SSI_ADI
Protocol of absolute data interface
GET_ADI
BiSS chain with absolute data interface
CHK_ADI
Cyclic check of absolute data
Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 40
CRCCFG
CRC test value of configuration
NRDOK
Selection of read/write protection
SEC_HI
Safety register for configuration section
SEC_LO
Safety register for EDS memory section
STATUS
Status byte
CMD
Command register
ERROR
Error byte
EMSK
Error mask
WMSK
Warning mask
RES_ERR
Error reset
THR_FAMP
Amplitude error filter threshold
TO_FAMP
Amplitude error filter timeout
EN_FAMP
Amplitude error filtering
preliminary
iC-MR 13-BIT S&H SIN/COS
INTERPOLATOR WITH CONTROLLER INTERFACES
Rev A1, Page 15/44
REGISTER MAP
Configuration and output data register
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Amplitude control (configuration)
0x00
ACOT(0)
ACOR(1:0)
ACOC(4:0)
0x01
ACOD(6:0)
ACOT(1)
Signal conditioning (configuration)
0x02
0x03
GFS(3:0)
LCMODE
-
GFS(10:4)
0x04
GFC(7:0)
0x05
0x06
MPS(3:0)
-
-
MPC(7:0)
-
-
ORS(1:0)
-
0x09
0x0A
0
-
ORC(1:0)
0x0B
MPC(9:8)
-
OFS(10:8)
NEFDR
OFC(10:8)
OFC(7:0)
PH(3:0)
0x0D
SELREF(1:0)
INMODE
PH(9:4)
DCPOS
0x0F
0x10
-
OFS(7:0)
0x0C
0x0E
GFC(10:8)
MPS(9:4)
0x07
0x08
GR(2:0)
REFVOS(1:0)
TUIN
CFGBIAS(3:0)
0
0
1
RIN(1:0)
UIN
SELBP
ENF
0
0
0
0
SSIRING
SSIERR
1
MODE(1:0)
12-bit A/D converter and temperature monitoring (configuration)
0x11
ADCSLOP(7:0)
0x12
ADCOFF(7:0)
0x13
ADCOFF(15:8)
0x14
TEMPLO(7:0)
0x15
TEMPLO(15:8)
0x16
TEMPHI(7:0)
0x17
TEMPHI(15:8)
Interfaces (configuration)
0x18
INTCFG(1:0)
FULL_CYC
GET_ADI
STP_ADI
CYC_ADI
0x19
ACQMODE(1:0)
ENLC
NESSI
ENXCRC
TMPSCD
0x1A
DL_ADI(4:0)
SSIMODE(1:0)
SYNC_ADI(1:0)
SSI_ADI
Offset & interpolator (configuration)
0x1B
STOFF(1:0)
0
0
0
0x1C
STOFF(9:2)
0x1D
STOFF(17:10)
0x1E
STOFF(25:18)
0x1F
MTOFF(7:0)
0x20
MTOFF(15:8)
0x21
MTOFF(23:16)
DIR
CODERES(1:0)
Mask register for error and warning (configuration)
0x22
EMSK_EXT
EMSK_ABS
EMSK_IPO
EMSK_KNF
EMSK_SYN
EMSK_TMP
EMSK_AMP
EMSK_RGL
0x23
WMSK_EXT
WMSK_ABS
WMSK_IPO
WMSK_KNF
WMSK_SYN
WMSK_TMP
WMSK_AMP
WMSK_RGL
Data resolution (configuration)
0x24
MTRESO(2:0)
STRESO(4:0)