STMICROELECTRONICS L6598_04

L6598
HIGH VOLTAGE RESONANT CONTROLLER
1
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Figure 1. Packages
FEATURES
HIGH VOLTAGE RAIL UP TO 600V
dV/dt IMMUNITY ±50V/ns IN FULL
TEMPERATURE RANGE
DRIVER CURRENT CAPABILITY:
250mA SOURCE
450mA SINK
SWITCHING TIMES 80/40ns RISE/FALL WITH
1nF LOAD
CMOS SHUT DOWN INPUT
UNDER VOLTAGE LOCK OUT
SOFT START FREQUENCY SHIFTING
TIMING
SENSE OP AMP FOR CLOSED LOOP
CONTROL OR PROTECTION FEATURES
HIGH ACCURACY CURRENT CONTROLLED
OSCILLATOR
INTEGRATED BOOTSTRAP DIODE
CLAMPING ON Vs
SO16, DIP16 PACKAGES
SO-16N
DIP-16
Table 1. Order Codes
Part Number
Package
L6598
DIP-16
L6598D
SO-16N
L6598D013TR
Tape & Reel
technology, able to ensure voltage ratings up to
600V, making it perfectly suited for AC/DC Adapters
and wherever a Resonant Topology can be beneficial. The device is intended to drive two Power MOS,
in the classical Half Bridge Topology. A dedicated
Timing Section allows the designer to set Soft Start
Time, Soft Start and Minimum Frequency. An Error
Amplifier, together with the two Enable inputs, are
made available. In addition, the integrated Bootstrap
Diode and the Zener Clamping on low voltage supply, reduces to a minimum the external parts needed
in the applications.
DESCRIPTION
The device is manufactured with the BCD OFF LINE
Figure 2. Block Diagram
VS
OPOUT
OPINOPIN+
5
OP AMP
H.V.
12
+
-
6
BOOTSTRAP
DRIVER
UV
DETECTION
7
HVG
DRIVER
16
VBOOT
15
HVG
14
OUT
Ifmin
VREF
DEAD
TIME
DRIVING
LOGIC
LEVEL
SHIFTER
11
LVG DRIVER
Ifstart
VREF
+
2
+
CONTROL
LOGIC
LVG
10
GND
Vthe1
8
-
Rfstart
LOAD
Vs
4
Rfmin
CBOOT
EN1
Vthe2
9
-
EN2
Iss
3
Cf
VCO
1
Css
June 2004
D98IN887A
1/17
L6598
Figure 3. Pin Connection
Css
1
16
VBOOT
Rfstart
2
15
HVG
Cf
3
14
OUT
Rfmin
4
13
N.C.
OPOUT
5
12
VS
OPIN-
6
11
LVG
OPIN+
7
10
GND
EN1
8
9
EN2
D98IN888
Table 2. Thermal Data
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to Ambient
SO16N
DIP16
Unit
120
80
°C/W
Table 3. Pin Function
N.
Name
Function
1
CSS
2
Rfstart
3
Cf
4
Rfmin
Minimum Oscillation Frequency Setting - Low Impedance Voltage Source - See also Cf
5
OPout
Sense OP AMP Output - Low Impedance
6
OPon-
Sense Op Amp Inverting Input - High Impedance
7
OPon+
Sense Op Amp Non Inverting Input - High Impedance
8
EN1
Half Bridge Latched Enable
9
EN2
Half Bridge Unlatched Enable
10
GND
Ground
11
LVG
Low Side Driver Output
12
Vs
13
N.C.
Soft Start Timing Capacitor
Soft Start Frequency Setting - Low Impedance Voltage Source - See also Cf
Oscillator Frequency Setting - see also Rfmin, Rfstart
Supply Volatge with Internal Zener Clamp
Not Connected
14
OUT
High Side Driver Reference
15
HVG
High Side Driver Output
16
Vboot
Bootstrapped Supply Voltage
2/17
L6598
Table 4. Absolute Maximum Ratings
Symbol
IS
Parameter
Supply Current at Vcl (*)
Value
Unit
25
mA
14.6
V
-1 to VBOOT -18
V
-1 to VBOOT
V
VLVG
Low Side Output
VOUT
High Side Reference
VHVG
High Side Output
VBOOT
Floating Supply Voltage
618
V
dVBOOT/dt
VBOOT pin Slew Rate (repetitive)
±50
V/ns
dVOUT/dt
OUT pin Slew Rate (repetitive)
±50
V/ns
Vir
Forced Input Voltage (pins Rfmin, Rfstart)
-0.3 to 5
V
Vic
Forced Input Volatge (pins Css, Cf)
-0.3 to 5
V
-0.3 to 5
V
±3
mA
-0.3 to 5
V
VEN1, VEN2 Enable Input Voltage
IEN1, IEN2
Enable Input Current
Vopc
Sense Op Amp Common Mode Range
Vopd
Sense Op Amp Differential Mode Range
-5 to 5
V
Vopo
Sense Op Amp Output Voltage (forced)
4.6
V
Tstg
Storage Temperature
-40 to +150
°C
Tj
Junction Temperature
-40 to +150
°C
Tamb
Ambient Temperature
-40 to +125
°C
(*) The device is provided of an internal Clamping Zener between GND and the Vs pin, It must not be supplied by a low impedance voltage
source.
Note : ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (Human Body Model).
Table 5. Recommended Operating Conditions
Symbol
VS
Parameter
Supply Voltage
Value
Unit
10 to Vcl
V
Vout (*)
High Side Reference
-1 to Vboot-Vcl
V
Vboot (*)
Floating Supply Rail
500
V
Maximum Switching Frequency
400
kHz
fmax
(*) If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580V.
3/17
L6598
Table 6. Electrical Characteristcs
(VS = 12V; VBOOT - VOUT = 12V; Tamb = 25°C)
Symbol
Pin
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY VOLTAGE
Vsuvp
VS Turn On Threshold
10
10.7
11.4
V
Vsuvn
12
VS Turn Off Threshold
7.3
8
8.7
V
Vsuvh
Supply Voltage Under Voltage
hysteresis
2.7
Vcl
Supply Voltage Clamping
Isu
Start Up Current
Vs < Vsuvn
14.6
Iq
Quiescent Current, fout =
60kHz, no load
Vs > Vsuvp
15.6
2
V
16.6
V
250
µA
3
mA
HIGH VOLTAGE SECTION
Ibootleak
16
BOOT pin Leakage Current
VBOOT = 580V
5
µA
Ioutleak
14
OUT pin Leakage Current
VOUT = 562V
5
µA
Rdon
16
Bootstrap Driver On Resistance
300
Ω
100
150
HIGH/LOW SIDE DRIVERS
Ihvgso
15
Ihvgsi
Ilvgso
11
Ilvgsi
trise
15,11
High Side Driver Source Current VHVG-VOUT = 0
170
250
mA
High Side Driver Sink Current
VHVG-VBOOT = 0
300
450
mA
Low Side Driver Source Current
VLVG-GND = 0
170
250
mA
Low Side Driver Sink Current
VLVG - VS = 0
300
450
mA
Low/High Side Output Rise
Time
Cload = 1nF
80
120
ns
Cload = 1nF
40
80
ns
48
50
52
%
tfall
OSCILLATOR
DC
14
Output Duty Cycle
fmin
Minimum Output Oscillation
Frequency
Cf = 470pF; Rfmin = 50k
58.2
60
61.8
kHz
fstart
Soft Start Output Oscillation
Frequency
Cf = 470pF; Rfmin = 50k;
Rfstart = 47k
114
120
126
kHz
Vref
2, 4
Voltage to Current Converters
Threshold
1.9
2
2.1
V
td
14
Dead Time between Low and
High Side Conduction
0.2
0.27
0.35
µs
0.115
0.15
0.185
s/µF
0.1
µA
TIMING SECTION
kss
1
Soft Start Timing constant
Css = 330nF
SENSE OP AMP
lIB
6, 7
Vio
Rout
5
IoutIout+
Vic
4/17
6,7
Input Bias Current
Input Offset Voltage
-10
10
mV
Output Resistance
200
300
Ω
Source Output Current
Vout = 4.5V
Sink Output Current
Vout = 0.2V
OP AMP input common mode
range
1
mA
1
-0.2
mA
3
V
L6598
Table 6. Electrical Characteristcs (continued)
(VS = 12V; VBOOT - VOUT = 12V; Tamb = 25°C)
Symbol
Pin
GBW
Gdc
Min.
Typ.
Sense Op Amp Gain Band
Width Product (*)
Parameter
Test Condition
0.5
1
Max.
MHz
Unit
DC Open Loop Gain
60
80
dB
COMPARATORS
8
Enabling Comparator Threshold
0.56
0.6
0.64
Vthe2
9
Enabling Comparator Threshold
1.05
1.2
1.35
V
tpulse
8,9
200
ns
Vthe1
Minimum Pulse lenght
V
(*) Guaranted by design
Figure 4. EN2 Timing Diagrams
VS
fOUT
fstart
fmin
EN2
VCss
TSS
TSS
D98IN889
Figure 5. EN1 Timing Diagrams
HVG
LVG
EN1
EN2
D98IN890
5/17
L6598
Figure 6. Oscillator/Output Timing Diagram
Cf
HVG
LVG
D98IN897
3
BLOCK’S DIAGRAM DESCRIPTION
3.1 High/Low Side driving section
An High and Low Side driving Section provide the proper driving to the external Power MOS or IGBT. An high
sink/source driving current (450/250 mA typ) ensure fast switching times also when size4 Power MOS are used.
The internal logic ensures a minimum dead time to avoid cross-conduction of the power devices.
3.2 Timing and Oscillator Section
The device is provided of a soft start function. It consists in a period of time, TSS, in which the switching frequency shifts from fstart to fmin. This feature is explained in the following description (ref. fig.7 and fig.8).
Figure 7. Soft Start and frequency shifting block
Iss
Ifstart
Ifmin
Iosc
gm
Css
6/17
OSC
L6598
During the soft start time the current ISS charges the capacitor CSS, generating a voltage ramp which is delivered
to a transconductance amplifier, as shown in fig. 7. Thus this voltage signal is converted in a growing current
which is subtracted to Ifstart. Therefore the current which drives the oscillator to set the frequency during the soft
start is equal to:
g m I ss
I osc = I fmin + ( I fstart – g m V Css ( t ) ) = I fmin +  I fstart – -------------- t

C ss 
V REF
[1]
V REF
where I fmin = --------------, I fsart = ----------------, V REF = 2V [2]
R fmin
R fstart
At the start-up (t=0) the oscillator frequency is set by:
1
1
I osc ( 0 ) = I fmin + I fstart = V REF  -------------- + ---------------- [3]
R

R
fmin
fstart
At the end of soft start (t = TSS) the second term of eq.1 decreases to zero and the switching frequency is set
only by Imin (i.e. Rfmin):
V REF
- [4]
I osc ( T ss ) = I fmin = ------------R fmin
Since the second term of eq.1 is equal to zero, we have:
g m I ss
C ss I fstart
I fstart – -------------- T SS = 0 → T SS = ----------------------- [5]
C ss
g m I ss
Note that there is not a fixed threshold of the voltage across CSS in which the soft start finishes (i.e. the end of
the frequency shifting), and TSS depends on CSS, Ifstart, gm, and ISS (eq. 5). Making TSS independent of Ifstart,
the ISS current has been designed to be a fraction of Ifstart, so:
C ss I fstart
C ss
I fstart
I SS = -------------- → T SS = -------------------------- → T SS = ----------- → T SS – k SS C SS [6]
K
g m I fstart K
gm K
In this way the soft start time depends only on the capacitor CSS. The typical value of the kSS constant (Soft
Start Timing Constant) is 0.15 s/µF.
The current Iosc is fed to the oscillator as shown in fig. 7. It is twice mirrored (x4 and x8) generating the triangular
wave on the oscillator capacitor Cf. Referring to the internal structure of the oscillator (fig.7), a good relationship
to compute an approximate value of the oscillator frequency in normal operation is:
1.41
f min = -------------------- [7]
R fmin C f
The degree of approximation depends on the frequency value, but it remains very good in the range from 30kHz
to 100kHz (figg.9-13)
7/17
L6598
Figure 8. Oscillator Block
Iosc
Vth+
X4
+
S
Cf
R
Vth-
+
X8
8/17
L6598
Figure 9. Typ. fmin vs. Rfmin @ Cf = 470pF
fmin
(KHz)
D98IN891
Figure 12. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
∆f
(KHz)
D98IN894
100
100
Rfmin=100KΩ
80
80
60
60
40
40
20
20
40
60
80
100 Rfmin(KΩ)
20
20
Figure 10. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
∆f
(KHz)
D98IN892
40
60
80
100 Rfstart(KΩ)
Figure 13. fmin @ different Rf vs Cf
fmin
(KHz)
80
400
Rf=19.9Kohm - calc.
Rf=19.9Kohm - meas.
Rfmin=33KΩ
60
200
Rf=90Kohm - meas.
40
Rf=90Kohm - calc.
0
20
20
40
60
80
100 Rfstart(KΩ)
0
200
400
Cf (pF)
Figure 11. Typ. (fstart-fmin) vs. Rfstar @
Cf = 470pF
∆f
(KHz)
D98IN893
100
Rfmin=50KΩ
80
60
40
20
20
40
60
80
100 Rfstart(KΩ)
9/17
L6598
3.3 Bootstrap Section
The supply of the high voltage section is obtained by means of a bootstrap circuitry. This solution normally requires an high voltage fast recovery diode for charging the bootstrap capacitor (fig. 14a). In the device a patented integrated structure, replaces this external diode. It is realised by means of a high voltage DMOS, driven
synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 14b.
Figure 14. Bootstrap driver
DBOOT
VS
VS
VBOOT
VBOOT
CBOOT
CBOOT
VOUT
VOUT
LVG
a
b
To drive the synchronised DMOS it is necessary a voltage higher than the supply voltage Vs. This voltage is
obtained by means of an internal charge pump (fig. 14b).
The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. The introduction
of the diode prevents any current can flow from the Vboot pin to the VS one in case that the supply is quickly
turned off when the internal capacitor of the pump is not fully discharged.
The bootstrap driver introduces a voltage drop during the recharging of the capacitor Cboot (i.e. when the low
side driver is on), which increases with the frequency and with the size of the external power MOS. It is the sum
of the drop across the RDSON and of the diode threshold voltage. At low frequency this drop is very small and
can be neglected. Anyway increasing the frequency it must be taken in to account. In fact the drop, reducing
the amplitude of the driving signal, can significantly increase the RDSON of the external power MOS (and so the
dissipation).
To be considered that in resonant power supplies the current which flows in the power MOS decreases increasing the switching frequency and generally the increases of RDSON is not a problem because power dissipation
is negligible. The following equation is useful to compute the drop on the bootstrap driver:
Qg
V drop = I ch arg e R dson + V diode → V drop = ------------------- R dson + V diode [8]
T ch arg e
where Qg is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and
Tcharge is the time in which the bootstrap driver remains on (about the semiperiod of the switching frequency
minus the dead time). The typical resistance value of the bootstrap DMOS is 150 Ohm. For example using a
power MOS with a total gate charge of 30nC the drop on the bootstrap driver is about 3V, at a switching frequency of 200kHz. In fact:
30nC
V drop = ------------------ 150Ω + 0.6V~2.6V
2.23µs
To summarise, if a significant drop on the bootstrap driver (at high switching frequency when large power MOS
are used) represents a problem, an external diode can be used, avoiding the drop on the RDSON of the DMOS.
10/17
L6598
3.4 OP AMP Section
The integrated OP AMP is designed to offer Low Output Impedance, wide band, High input Impedance and wide
Common Mode Range. It can be readily used to implement protection features or a closed loop control. For this
purpose the OP AMP Output can be properly connected to Rfmin pin to adjust the oscillation frequency.
3.5 Comparators
Two CMOS comparators are available to perform protection schemes. Short pulses (>= 200ns) on Comparators
Input are recognised. The EN1 input (active High), has a threshold of 0.6V (typical value) forces the device in a
latched shut down state (e.g. LVG Low, HVG low, Oscillator stopped), as in the Under Voltage Conditions. Normal Operating conditions are resumed after a power-off power-on sequence. The EN2 input (active high), with
a threshold of 1.2V (typical value) restarts a Soft Start sequence (see Timing Diagrams). In addition the EN2
Comparator, when activated, removes a latched shutdown caused by EN1.
Figure 15. Switching Time Waveform Definitions
90%
90%
HVG
10%
10%
tr
90%
90%
LVG
tf
10%
10%
tr
tf
D98IN898
Figure 16. Dead Time and Duty Cycle Waveform Definition
T1
td
td
Dc =
50%
T1
Tperiod
50%
HVG
50%
50%
50%
LVG
Tperiod
D98IN899
11/17
L6598
Figure 17. Typ. fmin vs. Temperature
fmin
(KHz)
Figure 20. Start Up Current vs Temperature
D98IN895
Isu
(µA)
200
70
150
60
100
50
50
40
-50
0
50
100
Figure 18. Typ. fstart vs. Temperature
ffstart
(KHz)
-50
T(˚C)
0
50
T (°C)
100
Figure 21. Quiescent Current vs Temperature
D98IN896
Iq
(mA)
2.3
130
Iq @ Vclamp
2.1
Iq @ 12V
120
1.9
110
1.7
100
1.5
-50
0
50
T(˚C)
100
Figure 19. Vs thresholds and clamp vs temp.
Vs
(V)
-50
0
50
100
T (°C)
Figure 22. HVG Source and Sink Current vs.
Temperature
Ihvg
(mA)
Vclamp
14
500
12
400
Vsuvp
10
Ihvg sink curr.
300
8
Vsuvn
Ihvg source curr.
200
6
-50
0
50
100
T (°C)
100
-50
12/17
0
50
100
T (°C)
L6598
Figure 23. LVG Source and Sink Current vs.
Temperature
Figure 24. Soft Start Timing Constant vs.
Temperature
kss
(s/µF)
Ilvg
(mA)
500
0.16
400
Ilvg sink curr.
300
0.14
Ilvg source curr.
200
100
-50
0
50
100
T (°C)
0.12
-50
0
50
100
T (°C)
Figure 25. Wide Range AC/DC Adapter Application
85 to 270
Vac
L6561/2
Vo
L6598
DRIVER
VCO
&
CONTROL
TL431
ENABLE
D98IN874A_MOD2
13/17
L6598
Figure 26. DIP-16 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
OUTLINE AND
MECHANICAL DATA
3.3
0.130
DIP16
Z
14/17
1.27
0.050
L6598
Figure 27. SO-16N Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
A
a1
MAX.
MIN.
TYP.
1.75
0.1
0.25
a2
MAX.
0.069
0.004
0.009
1.6
0.063
b
0.35
0.46
0.014
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
c1
D(1)
E
(typ.)
9.8
10
0.386
0.394
5.8
6.2
0.228
0.244
1.27
e3
F
(1)
0.020
45°
e
0.050
8.89
3.8
0.350
4.0
0.150
0.157
G
4.60
5.30
0.181
0.208
L
0.4
1.27
0.150
0.050
M
S
OUTLINE AND
MECHANICAL DATA
0.62
0.024
8 ° (max.)
SO16 (Narrow)
(1) "D" and "F" do not include mold flash or protrusions - Mold
flash or protrusions shall not exceed 0.15mm (.006inc.)
0016020 D
15/17
L6598
Figure 28. Revision History
16/17
Date
Revision
June 2004
5
Description of Changes
Changed the impagination following the new release of “Corporate
Technical Pubblication Design Guide”.
Done a few of corrections in the text.
L6598
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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