L6569 L6569A HIGH VOLTAGE HALF BRIDGE DRIVER WITH OSCILLATOR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH VOLTAGE RAIL UP TO 600V BCD OFF LINE TECHNOLOGY INTERNAL BOOTSTRAP DIODE STRUCTURE 15.6V ZENER CLAMP ON VS DRIVER CURRENT CAPABILITY: - SINK CURRENT = 270mA - SOURCE CURRENT = 170mA VERY LOW START UP CURRENT: 150µA UNDER VOLTAGE LOCKOUT WITH HYSTERESIS PROGRAMMABLE OSCILLATOR FREQUENCY DEAD TIME 1.25µs dV/dt IMMUNITY UP TO ±50V/ns ESD PROTECTION Minidip SO8 ORDERING NUMBERS: L6569 L6569D L6569A L6569AD be programmed using external resistor and capacitor. The internal circuitry of the device allows it to be driven also by external logic signal. DESCRIPTION The output drivers are designed to drive external nchannel power MOSFET and IGBT. The internal logic assures a dead time [typ. 1.25µs] to avoid crossconduction of the power devices. The device is a high voltage half bridge driver with built in oscillator. The frequency of the oscillator can Two version are available: L6569 and L6569A. They differ in the low voltage gate driver start up sequence. ■ BLOCK DIAGRAM H.V. CVS RHV VS 1 BOOT 8 Source CHARGE PUMP BIAS REGULATOR 7 LEVEL SHIFTER VS RF 2 CF 3 BUFFER VS COMP 4 OUT LOAD COMP CF GND CBOOT HIGH SIDE DRIVER 6 RF HVG LOGIC LOW SIDE DRIVER LVG 5 D94IN058D June 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/13 L6569 L6569A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit IS (*) Supply Current 25 mA VCF Oscillator Resistor Voltage 18 V V LVG Low Side Switch Gate Output 14.6 V VOUT High Side Switch Source Output -1 to VBOOT - 18 V V HVG High Side Switch Gate Output -1 to VBOOT V VBOOT Floating Supply Voltage 618 V VBOOT/OUT Floating Supply vs OUT Voltage 18 V dV BOOT/dt VBOOT Slew Rate (Repetitive) ± 50 V/ns dVOUT/dt VOUT Slew Rate (Repetitive) ± 50 V/ns Tstg Storage Temperature -40 to 150 °C Tj Junction Temperature -40 to 150 °C Ambient Temperature (Operative) -40 to 125 °C Tamb (*)The device has an internal zener clamp between GND and VS (typical 15.6V).Therefore the circuit should not be driven by a DC low impedance power source. Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model) THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-Ambient Max Minidip SO8 Unit 100 150 °C/W Min. Max. Unit 10 VCL V RECOMMENDED OPERATING CONDITIONS Symbol VS Parameter Supply Voltage VBOOT Floating Supply Voltage - 500 V VOUT High Side Switch Source Output -1 VBOOT -VCL V 200 kHz fout Oscillation Frequency PIN CONNECTION VS 1 8 BOOT RF 2 7 HVG CF 3 6 OUT GND 4 5 LVG D94IN059 2/13 L6569 L6569A PIN FUNCTION N° Pin Description 1 VS Supply input voltage with internal clamp [typ. 15.6V] 2 RF Oscillator timing resistor pin. A buffer set alternatively to VS and GND can provide current to the external resistor RF connected between pin 2 and 3. Alternatively, the signal on pin 2 can be used also to drive another IC (i.e. another L6569 to drive a full H-bridge) 3 CF Oscillator timing capacitor pin. A capacitor connected between this pin and GND fixes (together with RF) the oscillating frequency Alternatively an external logic signal can be applied to the pin to drive the IC. 4 GND Ground 5 LVG Low side driver output. The output stage can deliver 170mA source and 270mA sink [typ.values]. 6 OUT Upper driver floating reference 7 HVG High side driver output. The output stage can deliver 170mA source and 270mA sink [typ.values]. 8 BOOT Bootstrap voltage supply. It is the upper driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named “bootstrap driver” (a patented structure). This structure can replace the external bootstrap diode. ELECTRICAL CHARACTERISTCS (VS = 12V; VBOOT - VOUT = 12V; Tj = 25°C; unless otherwise specified.) Symbol Pin VSUVP 1 Parameter Test Condition Min. Typ. Max. Unit VS Turn On Threshold 8.3 9 9.7 V VSUVN VS Turn Off Threshold 7.3 8 8.7 V VSUVH VS Hysteresis 0.7 1 1.3 V 14.6 15.6 16.6 V VCL VS Clamping Voltage IS = 5mA I SU Start Up Current VS < VSUVN 150 250 µA Quiescent Current VS > VSUVP 500 700 µA Iq IBOOTLK 8 Leakage Current BOOT pin vs GND VBOOT = 580V 5 µA IOUTLK 6 Leakage Current OUT pin vs GND VOUT = 562V 5 µA IHVG SO 7 High Side Driver Source Current VHVG = 6V 110 175 mA High Side Driver Sink Current VHVG = 6V 190 275 mA Low Side Driver Source Current VLVG = 6V 110 175 mA Low Side Driver Sink Current VLVG = 6V 190 275 mA IHVG SI ILVG SO ILVG S I 5 3/13 L6569 L6569A ELECTRICAL CHARACTERISTCS (continued) Symbol Pin VRFON 2 VRF OFF VCFU 3 Parameter Test Condition Min. Typ. Max. Unit RF High Level Output Voltage IRF = 1mA VS -0.05 VS -0.2 V RF Low Level Output Voltage IRF = -1mA 50 200 mV CF Upper Threshold 7.7 8 8.2 V VCFL CF Lower Threshold 3.80 4 4.3 V td Internal Dead Time 0.85 1.25 1.65 µs DC Duty Cycle, Ratio Between Dead Time + Conduction Time of High Side and Low Side Drivers 0.45 0.5 0.55 R ON On resistance of Boostrap LDMOS VBC Boostrap Voltage before UVLO VS = 8.2 2.5 IAVE 1 Average Current from Vs No Load, fs = 60KHz fout 6 Oscillation Frequency RT = 12K; CT = 1nF 57 120 Ω 3.6 V 1.2 1.5 mA 60 63 kHz OSCILLATOR FREQUENCY The frequency of the internal oscillator can be programmed using external resistor and capacitor. The nominal oscillator frequency can be calculated using the following equation: 1 1 fOSC = ----------------------------------------- = -----------------------------------------2 ⋅ RF ⋅ CF ⋅ I n2 1.3863 ⋅ RF ⋅ C F Where RF and CF are the external resistor and capacitor. The device can be driven in ”shut down” condition keeping the CF pin close to GND, but some cares have to be taken: 1. When CF is to GND the high side driver is off and the low side is on 2. The forced discharge of the oscillator capacitor CF must not be shorter than 1us: a simple way to do this is to limit the current discharge with a resistive path imposing R · CF >1µs (see fig.1) Figure 1. R fault signal 8 2 7 3 6 4 5 RF CF GNDM 4/13 1 L6569 L6569A Bootstrap Function The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed, in similar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the Upper External Mosfet. The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS driven by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side Gate driver (LVG pin), actually working as a synchronous rectifier . The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON (i.e. LVG High) for a time interval: T C = RF · CF · In2 → 1.1 · RF · CF starting from the time the Supply Voltage VS has reached the Turn On Voltage (VSUVP = 9 V typical value). After time T1 (see waveform Diagram) the LDMOS that charges the Bootstrap Capacitor, is on with a RON=120Ω (typical value). In the L6569A a different start up procedure is followed (see waveform Diagram). The Lower External Mosfet is drive OFF until VS has reached the Turn On Threshold (VSUVPp), then again the TC time interval starts as above. Being the LDMOS used to implement the bootstrap operation a ”bi-directional” switch the current flowing into the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING operations is not ensured, and then an high voltage is applied to the BOOT pin. This condition can occur, for example, when the load is removed and an high resistive value is placed in series with the gate of the external Power Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided (fig. 7). Let’s consider the steps that should be taken. 1) Calculate the Turn on delay ( td ) of your Lower Power MOS: 1 t d = ( R g + Rid ) ⋅ C iss ⋅ ln -------------------VT H 1 – ---------VS 2) Calculate the Fall time ( tf ) of your Lower Power MOS: R g + R id - ⋅ Q gd t f = ----------------------VS – VT H where: Rg = External gate resistor Rid = 50Ω, typical equivalent output resistance of the driving buffer (when sourcing current) VTH, C iss and Qgd are Power MOS parameters VS = Low Voltage Supply. 3) Sketch the VBOOT waveform (using log-log scales) starting from the Drain Voltage of the Lower Power MOS (remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example is given where: VS = Low Voltage Supply VHV = High Voltage Supply Rail The VBOOT voltage swing must fall below the curve identified by the actual operating frequency of your application. 5/13 L6569 L6569A DEMO BOARD To allow an easy evaluation of the device, a P.C. board dedicated to lamp ballast application has been designed. Fig.11 shows the electrical schematic of a typical ballast application, while the PC and component layout is given in Fig12. This application has been designed to work with both the 110+/-20%V and the 220 +/- 20%V mains by means of a voltage doubler configuration at the bulk capacitor. The ballast inductance and the operating frequency are especially designed for a 18 W Sylvania De-luxe T/E type bulb. The PTC for preheat at the start up and the two back to back synchronization diodes, makes this application easy to implement and safe in operation. part 6/13 value R1 15ohm 1W R2, R3 22 ohm R4 27K R5 100K 1/2W R6 47ohm R7, R9 180K R8 120K 1/2W D1 18V zener D2, D3 BYW100-100 D4,D5,D6,D7 1N4007 D8 1N4148 C1 560pF 50V C2, C5 47µF 250V C3 4.7µF 25V C4 100nF 50V C6 100nF 250V C7-C8 8.2nF 630V C9 470pF 630V RV1 PTC 150ohm Q1, Q2 STD2NB50-1 L1 2.4mH L6569 L6569A Figure 2. Waveforms (L6569) VS VSUVP VBOOT-VOUT VS 4.6V(typ) τ=Ron*CBOOT VCF LVG T1 TC D95IN250B Figure 3. Waveforms (L6569A) VS VSUVP VBOOT-VOUT VS 4.6V(typ) τ=Ron*CBOOT VCF LVG T1 TC D95IN251B 7/13 L6569 L6569A Figure 4. Typical Dead Time vs. Temperature Dependency Dead time [µsec] 1.7 D96IN378A Figure 7. Vboot pin SOA for different Operating Frequency @ Tj = 125°C VBOOT (V) D96IN381 500 110KHz 1.6 70KHz 300 50KHz 1.5 200 1.4 20KHz 100 1.3 1.2 50 1.1 30 1 20 150KHz 0.9 -50 0 50 100 Temperature [C] 150 Figure 5. Typical Frequency vs Temperature Dependency Frequency [KHz] 65 D96IN379A 10 20 50 100 200 500 1,000 2,000 Time (ns), from LVG Transition High 5,000 10,000 Figure 8. Vboo t pin SOA @ Tj = 125°C VBOOT (V) D96IN416 500 64 300 63 200 VHV+VS 62 ACTUAL OPERTATING FREQUENCY 100 61 60 50 59 58 30 57 20 VBOOT td 56 55 tf VS 10 20 -50 -25 0 25 50 75 Temperature [C] 100 100 200 500 1,000 2,000 Time (ns), from LVG Transition High 125 Figure 6. Typical and Theoretical Oscillator Frequency vs Resistor Value f (KHz) 150 50 D96IN380 5,000 10,000 Figure 9. Typical Rise and Fall Times vs. Load Capacitance time [nsec] 300 D96IN417 Theoretical 250 100 90 80 Tr C=330pF 200 C=560pF 70 C=1nF 60 150 50 Tf 100 30 50 0 20 0 5 8/13 6 7 8 9 10 15 20 30 Resistor Value (Kohm) 40 50 1 2 3 4 5 6 C [nF] For both high and low side buffers @25°C Tamb L6569 L6569A Figure 10. Quiescent Current vs. Supply Voltage. Iq (µA) D96IN418 104 103 102 10 0 2 4 6 8 10 12 14 VS(V) Figure 11. CFL Demoboard 110/220V Inputs. R8 120K 1/2W C2 47µF 250V R4 27K 1/4W 4 x 1N4006 D7 D4 D6 D5 R5 100K 220V N R1 15 1W 110V 1/2W C5 47µF 250V C3 4.7µF 25V D8 1N4148 VS BOOT RF HVG L6569 CF C1 560pF 50V OUT LVG Q1 STD2NB50-1 C4100nF 50V R9 180K 1/4W R10 10K R2 22 1/4W R3 22 1/4W GND C9 470pF 630V 1/4W L1=2.4mH Q2 STD2NB50-1 R7 180K 1/4W R6 47 1/4W D1 ZPD 18V C7 8.2nF 630V C6 100nF 250V C8 8.2nF 630V BYW100-100 RV1 PTC 150 350V D2 L1=2.4mH core TH LCC E2006-B4 Ref also VOGH 575 0409200 2.4mH C7-C8=PS8n2J H3 630-2A TH D96IN419B D3 BYW100-100 CFL LAMP SYLVANIA DELUX T/E 18W 9/13 L6569 L6569A Figure 12. PC Board and Components Layout. Component Side Copper Side 10/13 L6569 L6569A mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.010 0.065 1.65 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45° (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.6 0.024 SO8 8 ° (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 11/13 L6569 L6569A mm DIM. MIN. A TYP. inch MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 12/13 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 0.060 Minidip L6569 L6569A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com 13/13