L6384 HIGH-VOLTAGE HALF BRIDGE DRIVER HIGH VOLTAGE RAIL UP TO 600 V dV/dt IMMUNITY +- 50 V/nsec IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY: 400 mA SOURCE, 650 mA SINK SWITCHING TIMES 50/30 nsec RISE/FALL WITH 1nF LOAD CMOS/TTL SCHMITT TRIGGER INPUTS WITH HYSTERESIS AND PULL DOWN SHUT DOWN INPUT DEAD TIME SETTING UNDER VOLTAGE LOCK OUT INTEGRATED BOOTSTRAP DIODE CLAMPING ON Vcc SO8/MINIDIP PACKAGES DESCRIPTION The L6384 is an high-voltage device, manufactured with the BCD”OFF-LINE” technology. It has SO8 Minidip ORDERING NUMBERS: L6384D L6384 an Half - Bridge Driver structure that enables to drive N Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. Matched delays between Lower and Upper Section simplify high frequency operation. Dead time setting can be readily accomplished by means of an external resistor. BLOCK DIAGRAM H.V. VCC 2 8 VBOOT BOOTSTRAP DRIVER HVG DRIVER UV DETECTION R IN 1 DT/SD 3 OUT LEVEL SHIFTER Idt DEAD TIME HVG 7 S LOGIC VCC CBOOT LVG DRIVER VCC 6 5 LVG 4 GND LOAD Vthi D97IN518A May 2000 1/10 L6384 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vout Output Voltage Vcc Supply Voltage (*) Is Value Supply Current (*) mA V Upper Gate Output Voltage -1 to Vboot V Lower Gate Output Voltage -0.3 to Vcc +0.3 V Logic Input Voltage -0.3 to Vcc +0.3 V Shut Down/Dead Time Voltage -0.3 to Vcc +0.3 V Allowed Output Slew Rate 50 V/ns Total Power Dissipation (Tj = 85 °C) 750 mW Vhvg Vlvg dVout/dt Ptot V 25 Floating Supply Voltage Vi V - 0.3 to 14.6 -1 to 618 Vboot Vsd Unit -3 to Vboot -18 Tj Junction Temperature 150 °C Ts Storage Temperature -50 to 150 °C (*) The device has an internal Clamping Zener between GND and the Vcc pin, It must not be supplied by a Low Impedence Voltage Source. Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model) PIN CONNECTION IN 1 8 VBOOT VCC 2 7 HVG DT/SD 3 6 VOUT GND 4 5 LVG D97IN519 THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO8 Minidip Unit 150 100 °C/W PIN DESCRIPTION N. Name Type 1 IN I Logic Input: it is in phase with HVG and in opposition of phase with LGV. It is compatible to VCC voltage. [Vil Max = 1.5V, Vih Min = 3.6V] 2 Vcc I Supply input voltage: there is an internal clamp [Typ. 15.6V] 3 DT/SD I High impedance pin with two functionalities. When pulled lower than Vdt [Typ. 0.5V] the device is shut down. A voltage higher than Vdt sets the dead time between high side gate driver and low side gate driver. The dead time value can be set forcing a certain voltage level on the pin or connecting a resistor between pin 3 and ground. Care must be taken to avoid below threshold spikes on pin 3 that can cause undesired shut down of the IC. For this reason the connection of the components between pin 3 and ground has to be as short as possible. This pin can not be left floating for the same reason. The pin has not be pulled through a low impedance to VCC, because of the drop on the current source that feeds Rdt. The operative range is: Vdt....270K ⋅ Idt, that allows a dt range of 0.4 - 3.1µs. 4 GND 2/10 Function Ground L6384 PIN DESCRIPTION (continued) N. Name Type Function 5 LVG O Low Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit guarantees 0.3V max on the pin (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 6 Vout O Upper Driver Floating Reference: layout care has to be taken to avoid below ground spikes on this pin. 7 HVG O High Side Driver Output: the output stage can deliver 400mA source and 650mA sink [Typ. Values]. The circuit gurantees 0.3V max between this pin and Vout (@ Isink = 10mA) with VCC > 3V and lower than the turn on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external mosfet normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 8 Vboot Bootstrap Supply Voltage: it is the upper driver floating supply. The bootstrap capacitor connected between this pin and pin 6 can be fed by an internal structure named ”bootstrap driver” (a patented structure). This structure can replace the external bootstrap diode. RECOMMENDED OPERATING CONDITIONS Symbol Pin Max. Unit Vout 6 Output Voltage Note1 580 V Vboot Vout 8 Floating Supply Voltage Note1 17 V 2 Supply Voltage fsw Vcc Parameter Switching Frequency Test Condition Typ. HVG,LVG load CL = 1nF Junction Temperature Tj Min. -45 400 kHz Vclamp V 125 °C Max. Unit Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V. ELECTRICAL CHARACTERISTICS AC Operation (VCC = 14.4V; Tj = 25°C) Symbol Pin ton 1 vs 5,7 High/Low Side Driver Turn-On Propagation Delay Parameter tonsd 3 vs 5,7 Shut Down Input Propagation Delay toff 1 vs 5,7 High/Low Side Driver Turn-Off Propagation Delay Test Condition Min. Vout = 0V R dt = 47kΩ Typ. 200+dt ns 220 280 ns Vout = 0V R dt = 47kΩ 250 300 ns Vout = 0V R dt = 146kΩ 200 250 ns Vout = 0V R dt = 270kΩ 170 200 ns tr 7,5 Rise Time CL = 1000pF 70 ns tf 7,5 Fall Time CL = 1000pF 30 ns DC Operation (VCC = 14.4V; Tj = 25°C) Supply Voltage Section Vclamp 2 Supply Voltage Clamping 14.6 15.6 16.6 V Vccth1 2 Vcc UV Turn On Threshold Is = 5mA 11.5 12 12.5 V Vccth2 2 Vcc UV Turn Off Threshold 9.5 10 10.5 V 3/10 L6384 DC Operation (continued) Symbol Pin Vcchys 2 Vcc UV Hysteresis Parameter Iqccu 2 Undervoltage Quiescent Supply Current Iqcc 2 Quiescent Current Test Condition Min. Typ. Max. Unit 2 V Vcc ≤ 11V 150 µA Vin = 0 380 500 µA Bootstrapped supply Voltage Section Vboot 8 IQBS ILK Rdson Bootstrap Supply Voltage 17 V Quiescent Current Vout = Vboot; IN = HIGH 200 µA High Voltage Leakage Current VHVG = Vout = Vboot = 600V 10 µA Bootstrap Driver on Resistance (*) Vcc ≥ 12.5V; IN = LOW Ω 125 High/Low Side Driver Iso 5,7 Isi Source Short Circuit Current VIN = Vih (tp < 10µs) 300 400 mA Sink Short Circuit Current VIN = Vil (tp < 10µs) 500 650 mA Logic Inputs Vil 2,3 Low Level Logic Threshold Voltage Vih High Level Logic Threshold Voltage Iih High Level Logic Input Current VIN = 15V Low Level Logic Input Current VIN = 0V Iil Iref 3 dt 3 vs 5,7 Vdt 3 70 µA 1 µA Rdt = 47k Rdt = 146 Rdt = 270k V 50 0.4 Shutdown Threshold (*) RDSON is tested in the following way: RDSON = V 3.6 Dead Time Setting Current Dead Time Setting Range (**) 1.5 28 µA 0.5 1.5 2.7 µs µs µs V 0.5 3.1 (VCC − VCBOOT1) − (VCC − VCBOOT2) I1(VCC,VCBOOT1) − I2(VCC,VCBOOT2) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 (**) Pin 3 is a high impedence pin. Therefore dt can be set also forcing a certain voltage V3 on this pin. The dead time is the same obtained with a Rdt if it is: Rdt ⋅ Iref = V3. Figure 1. Input/Output Timing Diagram IN SD HVG LVG D99IN1017 4/10 L6384 Figure 2. Typical Rise and Fall Times vs. Load Capacitance Figure 3. Quiescent Current vs. Supply Voltage time (nsec) Iq (µA) 104 D99IN1015 250 D99IN1016 200 Tr 103 150 Tf 100 102 50 0 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25°C Tamb BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 4a). In the L6384 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 4b An internal charge pump (fig. 4b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. CBOOT selection and charging: To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : Qgate CEXT = Vgate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200µA, so if HVG TON is 5ms, CBOOT has to supply 1µC to CEXT. This charge on a 1µF ca- 0 2 4 6 8 10 12 14 VS(V) pacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Vdrop = IchargeRdson → Vdrop = Qgate Rdson Tcharge where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5µs. In fact: Vdrop = 30nC ⋅ 125Ω ~ 0.8V 5µs Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. 5/10 L6384 Figure 4. Bootstrap Driver DBOOT VS VBOOT V BOOT VS H.V. H.V. HVG HVG CBOOT CBOOT VOUT V OUT TO LOAD TO LOAD LVG LVG a D99IN1067 b Figure 7. Driver Propagation Delay vs. Temperature. Figure 5. Dead Time vs. Resistance. 3.5 400 @ Vcc = 14.4V @ Vcc = 14.4V 3.0 300 Ton,Toff(ns) 2.5 dt (µs) 2.0 Typ. 1.5 1.0 @ Rdt = 47kOhm Typ. 200 100 Typ. Typ. @ Rdt = 270kOhm @ Rdt = 146kOhm 0.5 0.0 50 100 150 200 250 0 300 -45 Rdt (kOhm) 0 25 50 Tj (°C) 75 100 125 Figure 8. Shutdown Threshold vs. Temperature Figure 6. Dead Time vs. Temperature. 1 3 2.5 -25 Typ. R=270K 0.8 @ Vcc = 14.4V @ Vcc = 14.4V Vdt (V) dt (us) 2 1.5 Typ. R=146K Typ. R=47K 0.6 0.4 Typ. 1 0.2 0.5 0 -45 -25 0 25 50 Tj (°C) 6/10 75 100 125 0 -45 -25 0 25 50 Tj (°C) 75 100 125 L6384 Figure 9. Vcc UV Turn On vs. Temperature Figure 11. Output Source Current vs. Temperature. 15 1000 800 13 12 Current (mA) Vccth1 (V) 14 Typ. 11 @ Vcc = 14.4V 600 Typ. 400 200 10 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 10. Vcc UV Turn Off vs. Temperature 0 -45 -25 0 25 50 Tj (°C) 75 100 125 Figure 12. Output Sink Current vs.Temperature 13 1000 @ Vcc = 14.4V 12 11 10 Current (mA) Vccth2 (V) 800 Typ. 9 Typ. 600 400 200 8 -45 -25 0 25 50 Tj (°C) 75 100 125 0 -45 -25 0 25 50 Tj (°C) 75 100 125 7/10 L6384 mm DIM. MIN. A TYP. inch MAX. MIN. 3.32 TYP. MAX. 0.131 a1 0.51 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 0.020 D E 10.92 7.95 9.75 0.430 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L Z 8/10 3.18 OUTLINE AND MECHANICAL DATA 3.81 1.52 0.125 0.150 0.060 Minidip L6384 mm DIM. MIN. TYP. A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.069 0.004 0.010 0.065 1.65 a3 0.65 0.85 0.026 0.033 b 0.35 0.48 0.014 0.019 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.020 c1 45° (typ.) D (1) 4.8 5.0 0.189 0.197 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 F (1) 3.8 4.0 0.15 0.157 L 0.4 1.27 0.016 0.050 M S OUTLINE AND MECHANICAL DATA 0.6 0.024 SO8 8 ° (max.) (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). 9/10 L6384 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 10/10