STMICROELECTRONICS L6598D016TR

L6598
High voltage resonant controller
Features
■
High voltage rail up to 600 V
■
dV/dt immunity ±50 V/ns in full temperature
range
■
Driver current capability: 250 mA source
450 mA sink
■
Switching times 80/40 ns rise/fall with 1 nF load
■
CMOS shutdown input
■
Undervoltage lock-out
■
Soft-start frequency shifting timing
■
Sense op amp for closed loop control or
protection features
■
High accuracy current controlled oscillator
■
Integrated bootstrap diode
■
Clamping on Vs
■
SO16, DIP16 packages
Figure 1.
3/.
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Description
The device is manufactured with the BCD OFF
LINE technology, able to ensure voltage ratings
up to 600 V, making it perfectly suited for AC/DC
Adapters and wherever a resonant topology can
be beneficial. The device is intended to drive two
power MOSFET, in the classical half bridge
topology. A dedicated timing section allows the
designer to set soft start time, soft start and
minimum frequency. An error amplifier, together
with the two enable inputs, are made available. In
addition, the integrated bootstrap diode and the
zener clamping on low voltage supply, reduces to
a minimum the external parts needed in the
applications.
Block diagram
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October 2009
Doc ID 6554 Rev 7
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www.st.com
24
Contents
L6598
Contents
1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
Block diagram description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1
High/low side driving section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Timing and oscillator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3
Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4
Op amp section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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L6598
1
Maximum ratings
Maximum ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
25
mA
14.6
V
-1 to VBOOT -18
V
-1 to VBOOT
V
Supply current at Vcl (1)
IS
VLVG
Low side output
VOUT
High side reference
VHVG
High side output
VBOOT
Floating supply voltage
618
V
VBOOT pin slew rate (repetitive)
±50
V/ns
OUT pin slew rate (repetitive)
±50
V/ns
dVBOOT/dt
dVOUT/dt
Vir
Forced input voltage (pins Rfmin, Rfstart)
-0.3 to 5
V
Vic
Forced input voltage (pins Css, Cf)
-0.3 to 5
V
VEN1,
VEN2
Enable input voltage
-0.3 to 5
V
IEN1, IEN2
Enable input current
±3
mA
-0.3 to 5
V
Vopc
Sense op amp common mode range
Vopd
Sense op amp differential mode range
-5 to 5
V
Vopo
Sense op amp output voltage (forced)
4.6
V
Tstg
Storage temperature
-40 to +150
°C
Tj
Junction temperature
-40 to +150
°C
Tamb
Ambient temperature
-40 to +125
°C
1. The device is provided of an internal clamping zener between GND and the Vs pin, It must not be supplied
by a low impedance voltage source.
Note:
ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 (human body model).
Table 2.
Thermal data
Symbol
RthJA
Table 3.
Parameter
Thermal resistance junction to ambient
DIP16
Unit
120
80
°C/W
Recommended operating conditions
Symbol
Parameter
Supply voltage
VS
Vout
SO16N
Value
Unit
10 to Vcl
V
(1)
High side reference
-1 to Vboot-Vcl
V
(1)
Floating supply rail
500
V
Maximum switching frequency
400
kHz
Vboot
fmax
1. If the condition Vboot - Vout < 18 is guaranteed, Vout can range from -3 to 580 V.
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Electrical characteristics
2
L6598
Electrical characteristics
VS = 12 V; VBOOT - VOUT = 12 V; TA = 25 °C
Table 4.
Symbol
Electrical characteristics
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
Supply voltage
Vsuvp
VS turn on threshold
10
10.7
11.4
V
Vsuvn
VS turn off threshold
7.3
8
8.7
V
Vsuvh
Supply voltage under
voltage hysteresis
2.7
V
12
Vcl
Supply voltage clamping
14.6
Isu
Start up current
VS < Vsuvn
Iq
Quiescent current, fout =
60 kHz, no load
VS > Vsuvp
15.6
2
16.6
V
250
µA
3
mA
High voltage section
Ibootleak
16
BOOT pin leakage
current
VBOOT = 580 V
5
µA
Ioutleak
14
OUT pin leakage current
VOUT = 562 V
5
µA
RDSon
16
Bootstrap driver on
resistance
300
Ω
100
150
High/low side drivers
High side driver source
current
VHVG-VOUT = 0
170
250
mA
Ihvgsi
High side driver sink
current
VHVG-VBOOT = 0
300
450
mA
Ilvgso
Low side driver source
current
VLVG-GND = 0
170
250
mA
Low side driver sink
current
VLVG -VS = 0
300
450
mA
Ihvgso
15
11
Ilvgsi
trise
Low/high side output rise
15,11 time
tfall
Cload = 1nF
80
120
ns
Cload = 1nF
40
80
ns
48
50
52
%
Oscillator
DC
fmin
fstart
4/24
Output duty cycle
14
Minimum output
oscillation frequency
Cf = 470pF;
Rfmin = 50kΩ
58.2
60
61.8
kHz
Soft start output
oscillation frequency
Cf = 470pF; Rfmin =
50kΩ; Rfstart = 47kΩ
114
120
126
kHz
Doc ID 6554 Rev 7
L6598
Electrical characteristics
Table 4.
Electrical characteristics (continued)
Symbol
Pin
Vref
2, 4
td
IVref
Parameter
Test condition
Min.
Typ.
Max.
Unit
Voltage to current
converters threshold
1.9
2
2.1
V
14
Dead time between low
and high side conduction
0.2
0.27
0.35
µs
2, 4
Reference current
120
μA
Timing section
kss
1
Soft start timing constant
Css = 330nF
0.115
0.15
0.185
s/µF
0.1
µA
Sense op amp
lIB
Input bias current
6, 7
Vio
Input offset voltage
-10
10
mV
Rout
Output resistance
200
300
?
Iout-
5
Iout+
Vic
6,7
GBW
Gdc
Source output current
Vout = 4.5V
1
mA
Sink output current
Vout = 0.2V
1
mA
Op amp input common
mode range
-0.2
Sense op amp gain band
width product (1)
0.5
1
MHz
DC open loop gain
60
80
dB
3
V
Comparators
Vthe1
8
Enabling comparator
threshold
0.56
0.6
0.64
V
Vthe2
9
Enabling comparator
threshold
1.05
1.2
1.35
V
tpulse
8,9
Minimum pulse length
200
ns
1. Guaranteed by design
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Pin connections
3
L6598
Pin connections
Figure 2.
Pin connections
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Table 5.
6/24
Pin description
Pin n°
Name
Function
1
CSS
Soft start timing capacitor
2
Rfstart
Soft start frequency setting - low impedance voltage source -see also Cf
3
Cf
4
Rfmin
Minimum oscillation frequency setting - low impedance voltage source - see also Cf
5
OPout
Sense op amp output - low impedance
6
OPon-
Sense op amp inverting input -high impedance
7
OPon+
Sense op amp non inverting input - high impedance
8
EN1
Half bridge latched enable
9
EN2
Half bridge unlatched enable
10
GND
Ground
11
LVG
Low side driver output
12
Vs
13
N.C.
Not connected
14
OUT
High side driver reference
15
HVG
High side driver output
16
Vboot
Bootstrapped supply voltage
Oscillator frequency setting - see also Rfmin, Rfstart
Supply voltage with internal zener clamp
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L6598
4
Timing diagram
Timing diagram
Figure 3.
EN2 timing diagrams
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Figure 4.
EN1 timing diagrams
+9*
/9*
(1
(1
!-V
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Timing diagram
Figure 5.
L6598
Oscillator/output timing diagram
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+9*
/9*
!-V
8/24
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L6598
Block diagram description
5
Block diagram description
5.1
High/low side driving section
An high and low side driving section provide the proper driving to the external power MOS or
IGBT. An high sink/source driving current (450/250 mA typ) ensure fast switching times also
when size for power MOS are used. The internal logic ensures a minimum dead time to
avoid cross-conduction of the power devices.
5.2
Timing and oscillator section
The device is provided of a soft start function. It consists in a period of time, TSS, in which
the switching frequency shifts from fstart to fmin. This feature is explained in the following
description (ref. fig.7 and fig.8).
Figure 6.
Soft start and frequency shifting block
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During the soft start time the current ISS charges the capacitor CSS, generating a voltage
ramp which is delivered to a transconductance amplifier, as shown in fig. 7. Thus this
voltage signal is converted in a growing current which is subtracted to Ifstart. Therefore the
current which drives the oscillator to set the frequency during the soft start is equal to:
Equation 1
g m I ss⎞
I osc = I fmin + ( I fstart – g m V Css ( t ) ) = I fmin + ⎛⎝ I fstart – ------------C ss ⎠
Equation 2
where
V REF
V REF
I fmin = --------------, I fstart = ---------------- ,V REF = 2V
R fmin
R fstart
Doc ID 6554 Rev 7
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Block diagram description
L6598
At the start-up (t = 0) the oscillator frequency is set by:
Equation 3
1 - + --------------1 -⎞
I OSC ( 0 ) = I fmin + I fstart = V REF ⎛⎝ ------------R fmin R fstart⎠
At the end of soft start (t = TSS) the second term of eq.1 decreases to zero and the switching
frequency is set only by Imin (i.e. Rfmin):
Equation 4
V REF
I OSC ( T SS ) = I fmin = ------------R fmin
Since the second term of eq.1 is equal to zero, we have:
Equation 5
g m I ss
C ss I fstart
I fstart – -------------- T SS = 0 → T SS = ----------------------C ss
g m I ss
Note that there is not a fixed threshold of the voltage across CSS in which the soft start
finishes (i.e. the end of the frequency shifting), and TSS depends on CSS, Ifstart, gm, and ISS
(eq. 5). Making TSS independent of Ifstart, the ISS current has been designed to be a fraction
of Ifstart, so:
Equation 6
I fstart
C ss I fstart
C ss
I SS = -------------- → T SS = -------------------------- → T SS = ----------- → T SS – k SS C SS
K
g m I fstart K
gm K
In this way the soft start time depends only on the capacitor CSS. The typical value of the kSS
constant (Soft start timing constant) is 0.15 s/μF.
The current Iosc is fed to the oscillator as shown in fig. 7. It is twice mirrored (x4 and x8)
generating the triangular wave on the oscillator capacitor Cf. Referring to the internal
structure of the oscillator (fig.7), a good relationship to compute an approximate value of the
oscillator frequency in normal operation is:
Equation 7
1.41 f min = ------------------R fmin C f
10/24
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L6598
Block diagram description
The degree of approximation depends on the frequency value, but it remains very good in
the range from 30 kHz to 100 kHz (figg.9-13)
Figure 7.
Oscillator block
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Doc ID 6554 Rev 7
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Block diagram description
Figure 8.
Typ. fmin vs. Rfmin @ Cf = 470 pF
Figure 10. Typ. (fstart-fmin) vs.
Rfstar @ Cf = 470 pF
12/24
L6598
Figure 9.
Typ. (fstart-fmin) vs. Rfstar @
Cf = 470 pF
Figure 11. fmin @ different Rf vs Cf
Doc ID 6554 Rev 7
L6598
Block diagram description
Figure 12. Typ. (fstart-fmin) vs.
Rfstar @ Cf = 470 pF
5.3
Bootstrap section
The supply of the high voltage section is obtained by means of a bootstrap circuitry. This
solution normally requires an high voltage fast recovery diode for charging the bootstrap
capacitor (fig. 14a). In the device a patented integrated structure, replaces this external
diode. It is released by means of a high voltage DMOS, driven synchronously with the low
side driver (LVG), with in series a diode, as shown in fig. 14b.
Figure 13. Bootstrap driver
To drive the synchronized DMOS it is necessary a voltage higher than the supply voltage
Vs. This voltage is obtained by means of an internal charge pump (fig. 14b).
The diode connected in series to the DMOS has been added to avoid undesirable turn on of
it. The introduction of the diode prevents any current can flow from the Vboot pin to the VS
one in case that the supply is quickly turned off when the internal capacitor of the pump is
not fully discharged.
Doc ID 6554 Rev 7
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Block diagram description
L6598
The bootstrap driver introduces a voltage drop during the recharging of the capacitor Cboot
(i.e. when the low side driver is on), which increases with the frequency and with the size of
the external power MOS. It is the sum of the drop across the RDSON and of the diode
threshold voltage. At low frequency this drop is very small and can be neglected. Anyway
increasing the frequency it must be taken in to account. In fact the drop, reducing the
amplitude of the driving signal, can significantly increase the RDSON of the external power
MOS (and so the dissipation).
To be considered that in resonant power supplies the current which flows in the power MOS
decreases increasing the switching frequency and generally the increases of RDSON is not a
problem because power dissipation is negligible. The following equation is useful to
compute the drop on the bootstrap driver:
Equation 8
Qg
V drop = I ch arg e R dson + V diode → V drop = ------------------- R dson + V diode
T ch arg e
where Qg is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS, and Tcharge is the time in which the bootstrap driver remains on (about the
semi-period of the switching frequency minus the dead time). The typical resistance value of
the bootstrap DMOS is 150 Ω. For example using a power MOS with a total gate charge of
30 nC the drop on the bootstrap driver is about 3 V, at a switching frequency of 200 kHz. In
fact:
Equation 9
30nC
V drop = ------------------ 150Ω + 0.6V ∼ 2.6V
2.23μs
To summaries, if a significant drop on the bootstrap driver (at high switching frequency when
large power MOS are used) represents a problem, an external diode can be used, avoiding
the drop on the RDSON of the DMOS.
5.4
Op amp section
The integrated op amp is designed to offer low output impedance, wide band, high input
impedance and wide common mode range. It can be readily used to implement protection
features or a closed loop control. For this purpose the op amp output can be properly
connected to Rfmin pin to adjust the oscillation frequency.
14/24
Doc ID 6554 Rev 7
L6598
5.5
Block diagram description
Comparators
Two CMOS comparators are available to perform protection schemes.
Short pulses (≥ 200 ns) on comparators input are recognized. The EN1 input (active high),
has a threshold of 0.6 V (typical value) forces the device in a latched shut down state (e.g.
LVG low, HVG low, oscillator stopped), as in the under voltage conditions. Normal operating
conditions are resumed after a power-off power-on sequence. The EN2 input (active high),
with a threshold of 1.2 V (typical value) restarts a Soft Start sequence (see timing
diagrams). In addition the EN2 comparator, when activated, removes a latched shutdown
caused by EN1.
Figure 14. Switching time waveform definitions
Figure 15. Dead time and duty cycle waveform definition
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Block diagram description
L6598
Figure 16. Typ. fmin vs. temperature
Figure 17. Start-up current vs temperature
Figure 18. Typ. fstart vs. temperature
Figure 19. Quiescent current vs temperature
16/24
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L6598
Block diagram description
Figure 20. Vs thresholds and clamp vs temp.
Figure 21. HVG source and sink current vs.
temperature
Figure 22. LVG source and sink current vs.
temperature
Figure 23. Soft-start timing constant vs.
temperature
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Block diagram description
L6598
Figure 24. Wide range AC/DC adapter application
18/24
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L6598
6
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Doc ID 6554 Rev 7
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Package mechanical data
L6598
Plastic DIP-16 (0.25) MECHANICAL DATA
mm.
inch
DIM.
MIN.
a1
0.51
B
0.77
TYP
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
20/24
Doc ID 6554 Rev 7
L6598
Package mechanical data
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.25
a2
0.004
0.010
1.64
0.063
b
0.35
0.46
0.013
b1
0.19
0.25
0.007
C
MAX.
0.5
0.018
0.010
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
e3
8.89
0.050
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
M
0.62
S
0.050
0.024
8° (max.)
0016020D
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Ordering codes
7
L6598
Ordering codes
Table 6.
Ordering information
Order codes
Package
Packing
L6598
DIP16
Tube
L6598D
Tube
SO16N
L6598D016TR
22/24
Tape and reel
Doc ID 6554 Rev 7
L6598
8
Revision history
Revision history
Table 7.
Document revision history
Date
Revision
Changes
21-Jun-2004
5
Changed the impagination following the new release of “corporate
technical pubblication design guide”. Done a few of corrections in
the text.
09-Sep-2004
6
Added ordering number fot the tape and reel version, updated
Table 4 on page 4
02-Oct-2009
7
Updated Table 4 on page 4
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L6598
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