STMICROELECTRONICS M41T83SMY6E

M41T82
M41T83
Serial RTC with battery switchover
Features
■
2.0 to 5.5V clock operating voltage
■
Ultra-low battery supply current of 365nA
■
Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■
■
QFN16, 4mm x 4mm (QA)
(VFQFPN16)
Programmable clock calibration (analog and
digital)
18
Automatic switchover and reset output circuitry
(fixed reference)
– M41T83S
VCC = 3.00V to 5.50V
(2.85V ≤ VRST ≤ 3.00V)
– M41T83R
VCC = 2.70V to 5.50V
(2.55V ≤ VRST ≤ 2.70V)
– M41T83Z
VCC = 2.38V to 5.50V
(2.25V ≤ VRST ≤ 2.38V)
1
SOX18 (MY, 18-pin, 300mil SOIC
with Embedded Crystal)1
SO8 (M)
■
Serial interface supports I2C Bus (400kHz
protocol)
■
Programmable alarm with interrupt function
(valid even during battery back-up mode)
■
Oscillator stop detection
■
Battery or Super-cap™ back-up
■
Optional 2nd programmable alarm available
■
Operating temperature of –40°C to 85°C
■
Square wave output defaults to 32KHz on
power-up (M41T83 only)
■
■
RESET (RST) output
■
Watchdog timer
■
Programmable 8-bit counter/timer
Package options include:
– a 16-lead QFN (M41T83),
– an 18-lead embedded crystal SOIC
(M41T83), or
– an 8-lead SOIC (M41T82)
■
7 bytes of battery-backed user SRAM
■
■
Battery low flag
RoHS compliance: lead-free components are
compliant with the RoHS directive.
■
Power-down time stamp (HT bit)
■
Low operating current of 80µA
March 2007
1. Contact local ST sales office for availability of SOX18
package.
Rev 4
1/58
www.st.com
1
Contents
M41T82 M41T83
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
3
2/58
2-Wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4
Data retention and battery switchover (VSO = VRST) . . . . . . . . . . . . . . . . 20
2.5
Power-on reset (trec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
Power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2
Clock/control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
Real Time Clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.4.1
Digital calibration (periodic counter correction) . . . . . . . . . . . . . . . . . . . 28
3.4.2
Analog calibration (programmable load capacitance) . . . . . . . . . . . . . . 30
3.5
Setting the alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6
Optional second programmable alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.7
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.8
8-bit (countdown) timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.8.1
Timer Interrupt/Timer Pulse (TI/TP, M41T83 only) . . . . . . . . . . . . . . . . . 38
3.8.2
Timer Flag (TF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.3
Timer Interrupt Enable (TIE, M41T83 only) . . . . . . . . . . . . . . . . . . . . . . 39
3.8.4
Timer Enable (TE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.8.5
TD1/0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.9
Square wave output (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.10
Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.11
Century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
M41T82 M41T83
Contents
3.12
Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.13
Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.14
Oscillator Fail Interrupt Enable (M41T83 only) . . . . . . . . . . . . . . . . . . . . . 43
3.15
Initial power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.16
OTP bit operation (M41T83 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3/58
List of tables
M41T82 M41T83
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
4/58
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
M41T82 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Key to Table 2 (M41T82 clock/control register map (32 bytes)) . . . . . . . . . . . . . . . . . . . . . 24
M41T83 clock/control register map (32 bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Key to Table 4 (M41T83 clock/control register map (32 bytes)) . . . . . . . . . . . . . . . . . . . . . 26
Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interrupt operation (bit TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Timer source clock frequency selection (244.1µs to 4.25 hrs) . . . . . . . . . . . . . . . . . . . . . . 39
Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data . . . . . . . . . . . . . . . . 52
SOX18 – 18-lead plastic small outline, 300mils, embedded crystal, package mech. . . . . . 54
SO8 – 8-lead plastic small outline (150 mils body width), package mech. data . . . . . . . . . 55
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
M41T82 M41T83
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
M41T82 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
M41T83 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SO8 (M) connections (M41T82) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
QFN16 (QA) connections (M41T83) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SOX18 (MY) connections (M41T83). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
M41T82 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
M41T82 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M41T83 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
M41T83 hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Internal load capacitance adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock accuracy vs. on-chip load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock divider chain and calibration circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Measurement ac I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Bus timing requirement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline . . . . . . . . . . . 52
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended footprint . . . . . . 53
32KHz crystal + QFN16 vs. VSOJ20 mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SOX18 – 18-lead plastic small outline, 300mils, embedded crystal, outline. . . . . . . . . . . . 54
SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5/58
Description
1
M41T82 M41T83
Description
The M41T8x are low power Serial I2C Real Time Clocks with a built-in 32.768kHz oscillator
(external crystal-controlled for the QFN16 and SO8 packages, embedded crystal for the
SOX18 package). Eight bytes of the Register Map (see Table 2 on page 23) are used for
the clock/calendar function and are configured in binary coded decimal (BCD) format. An
additional 17 bytes of the Register Map provide status/control of the two Alarms, Watchdog,
8-bit Counter, and Square Wave functions. An additional seven bytes are made available as
user SRAM.
Addresses and data are transferred serially via a two line, bi-directional I2C interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T8x has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the clock operations can be supplied by a small lithium button battery
when a power failure occurs.
Functions available to the user include a non-volatile, time-of-day clock/calendar, two Alarm
interrupts, Watchdog Timer, programmable 8-bit Counter, and Square Wave outputs. The
eight clock address locations contain the century, year, month, date, day, hour, minute,
second, and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29
(leap year), 30, and 31 day months are made automatically. The M41T83 is supplied in
either a QFN16 (QA) or an SOX18 (MY), 300mil SOIC which includes an embedded 32KHz
crystal. The SOX18 package requires only a user-supplied battery to provide non-volatile
operation. The M41T82 is available only in an SO8 package.
6/58
M41T82 M41T83
Figure 1.
Description
M41T82 logic diagram
VBAT
VCC
XI
XO
FT/RST(1)
SDA
SCL
VSS
AI11196
1. Open drain
Figure 2.
M41T83 logic diagram
VBAT VCC
SQW(2)
XI(1)
XO(1)
IRQ1/OUT/FT(3)
SDA
RST(3)
SCL
IRQ2(3)
VSS
AI11195
1. For QFN16 package only.
2. Defaults to 32KHz on power-up.
3. Open drain
7/58
Description
M41T82 M41T83
Table 1.
Signal names
Symbol
Description
XI(1)
32KHz oscillator input
XO(1)
32KHz oscillator output
IRQ1/OUT/FT
(2)
SQW
RST
FT/RST
(3)
IRQ2
Interrupt 1/Output driver/Frequency Test output (open drain)
32KHz programmable Square Wave output
Power-on Reset output (open drain)
Frequency Test output/Power-on Reset (open drain - M41T82 only)
Interrupt for alarm 2 (open drain)
SDA
Serial Data Address input/output
SCL
Serial Clock Input
VBAT
Battery supply voltage (Tie VBAT to VSS if no battery is connected.)
DU(4)
Do not use
VCC
Supply voltage
VSS
Ground
1. For SO8 and QFN16 packages only.
2. Defaults to 32KHz on power-up.
3. For SOX18 and QFN16 packages only.
4. DU pin must be tied to VCC.
8/58
M41T82 M41T83
Figure 3.
Description
SO8 (M) connections (M41T82)
1
2
3
4
XI
XO
VBAT
VSS
M41T82
8
7
6
5
VCC
FT/RST(1)
SCL
SDA
AI11199
1. Open drain output
RST(1)
1
NC
2
XI
VCC
NC
QFN16 (QA) connections (M41T83)
XO
Figure 4.
16
15
14
13
12
IRQ2(1)
11
IRQ1/FT/OUT(1)
M41T83
SQW(2)
4
9
SDA
5
6
7
8
NC
SCL
NC
10
VSS
3
VBAT
NC
AI11197
1. Open drain output
2. Defaults to 32KHz on Power-up.
Figure 5.
SOX18 (MY) connections (M41T83)
NC
(1)
NF
NF(1)
NC
(2)
RST
DU(3)
SQW(4)
VBAT
VSS
1
2
3
4
5
6
7
8
9
M41T83
18
17
16
15
14
13
12
11
10
NC
(1)
NF
NF(1)
VCC
IRQ2(2)
NC
IRQ1/FT/OUT(2)
SCL
SDA
AI11198
1. NF pins must be tied to VSS. Pins 2 and 3, and 16 and 17 are internally shorted together.
2. Open drain output
3. Do not use (must be tied to VCC)
4. Defaults to 32KHz on power-up.
9/58
Description
M41T82 M41T83
Figure 6.
M41T82 block diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
XI
32KHz
OSCILLATOR
XO
CRYSTAL
ALARM1
ALARM2
WATCHDOG
SDA
I2C
INTERFACE
SCL
WRITE
PROTECT
VCC < VRST
FT
FREQUENCY TEST
OUTPUT DRIVER
8-BIT COUNTER
USER SRAM (7 Bytes)
INTERNAL
POWER
VCC
VBAT
VRST/VSO(1)
COMPARE
trec
TIMER
RST(2)
AI11812
1. VRST = VSO = 2.93V (S), 2.63V (R), and 2.32V (Z).
2. Open drain output
10/58
M41T82 M41T83
Description
Figure 7.
M41T82 hardware hookup
VCC
MCU
M41T82
VCC
XI
VCC
(1)
FT/RST
Reset Input
XO
VBAT
VSS
SCL
Serial Clock Line
SDA
Serial Data Line
AI11813
1. Open drain output
11/58
Description
M41T82 M41T83
Figure 8.
M41T83 block diagram
REAL TIME CLOCK
CALENDAR
OSCILLATOR FAIL
CIRCUIT
XI
CRYSTAL
32KHz
OSCILLATOR
XO
OFIE
A1IE
ALARM1
A2IE
ALARM2
(1)
IRQ1/FT/OUT
WATCHDOG
SDA
IRQ2(1)
I2C
INTERFACE
SCL
FT
FREQUENCY TEST
OUT
OUTPUT DRIVER
WRITE
PROTECT
VCC < VRST
TIE
8-BIT COUNTER
SQWE
SQUARE WAVE
SQW
8 BITS OF OTP
USER SRAM (7 Bytes)
INTERNAL
POWER
VCC
VBAT
VRST/VSO(2)
COMPARE
trec
TIMER
RST(1)
AI11800
1. Open drain output
2. VRST = VSO = 2.93V (S), 2.63V (R), and 2.32V (Z).
12/58
M41T82 M41T83
Figure 9.
Description
M41T83 hardware hookup
VCC
MCU
M41T83
VCC
VCC
(1)
IRQ1/FT/OUT
XI
(1)
RST
(1)
XO
IRQ2
VBAT
VSS
INT
Reset Input
Port
SCL
Serial Clock Line
SDA
Serial Data Line
SQW
32KHz CLKIN
AI11801
1. Open drain output
13/58
Operation
2
M41T82 M41T83
Operation
The M41T8x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 32 bytes
contained in the device can then be accessed sequentially in the following order:
●
1st byte: tenths/hundredths of a second register
●
2nd byte: seconds register
●
3rd byte: minutes register
●
4th byte: century/hours register
●
5th byte: day register
●
6th byte: date register
●
7th byte: month register
●
8th byte: year register
●
9th byte: digital calibration register
●
10th byte: watchdog register
●
11th - 15th bytes: alarm 1 registers
●
16th byte: flags register
●
17th byte: timer value register
●
18th byte: timer control register
●
19th byte: analog calibration register
●
20th byte: square wave register
●
21st - 25th bytes: alarm 2 registers
●
26th - 32nd bytes: user RAM
The M41T8x clock continually monitors VCC for an out-of-tolerance condition. Should VCC
fall below VRST, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out-of-tolerance system. The power input will also
be switched from the VCC pin to the battery when VCC falls below the battery back-up
switchover voltage (VSO = VRST). At this time the clock registers will be maintained by the
attached battery supply. As system power returns and VCC rises above VSO, the battery is
disconnected, and the power supply is switched to external VCC.
14/58
M41T82 M41T83
2.1
Operation
2-Wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is High.
●
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
2.1.2
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
15/58
Operation
2.1.5
M41T82 M41T83
Acknowledge
Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 10. Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 11. Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
16/58
M41T82 M41T83
2.2
Operation
READ mode
In this mode the master reads the M41T8x slave after setting the slave address (see
Figure 13 on page 18). Following the WRITE Mode control bit (R/W = 0) and the
Acknowledge bit, the word address 'An' is written to the on-chip address pointer. Next the
START condition and slave address are repeated followed by the READ Mode control bit
(R/W = 1). At this point the master transmitter becomes the master receiver. The data byte
which was addressed will be transmitted and the master receiver will send an Acknowledge
bit to the slave transmitter. The address pointer is only incremented on reception of an
Acknowledge clock. The M41T8x slave transmitter will now place the data byte at address
An+1 on the bus, the master receiver reads and acknowledges the new byte and the
address pointer is incremented to “An+2.”
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter. The system-to-user transfer of clock data will be
halted whenever the address being read is a clock address (00h to 07h). The update will
resume due to a Stop Condition or when the pointer increments to any non-clock address
(08h-1Fh).
This is true both in READ Mode and WRITE Mode.
An alternate READ Mode may also be implemented whereby the master reads the M41T8x
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 14 on page 18).
Figure 12. Slave address location
R/W
SLAVE ADDRESS
START
1
A
LSB
MSB
Note:
1
0
1
0
0
0
AI00602
17/58
Operation
M41T82 M41T83
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 13. READ mode sequence
STOP
SLAVE
ADDRESS
DATA n+X
P
NO ACK
AI00899
ACK
DATA n+X
P
NO ACK
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
BUS ACTIVITY:
18/58
STOP
R/W
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 14. Alternative READ mode sequence
AI00895
M41T82 M41T83
2.3
Operation
WRITE mode
In this mode the master transmitter transmits to the M41T8x slave receiver. Bus protocol is shown in
Figure 15. Following the START condition and slave address, a logic '0' (R/W = 0) is placed on the bus
and indicates to the addressed device that word address “An” will follow and is to be written to the onchip address pointer. The data word to be written to the memory is strobed in next and the internal
address pointer is incremented to the next address location on the reception of an acknowledge clock.
The M41T8x slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address see Figure 12 on page 17 and again after it has received the word address and each
data byte.
SLAVE
ADDRESS
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 15. WRITE mode sequence
AI00591
19/58
Operation
2.4
M41T82 M41T83
Data retention and battery switchover (VSO = VRST)
Once VCC falls below the switchover voltage (VSO = VRST), the device automatically
switches over to the battery and powers down into an ultra low current mode of operation to
preserve battery life. If VBAT is less than, or greater than VRST, the device power is switched
from VCC to VBAT when VCC drops below VRST (see Figure 24 on page 49). At this time the
clock registers and user RAM will be maintained by the attached battery supply.
When it is powered back up, the device switches back from battery to VCC at VSO +
hysteresis. When VCC rises above VRST, it will recognize the inputs. For more information
on battery storage life refer to Application Note AN1012.
2.5
Power-on reset (trec)
The M41T8x continuously monitors VCC. When VCC falls to the power fail detect trip point,
the RST output pulls low (open drain) and remains low after power-up for trec (210ms
typical) after VCC rises above VRST (max).
Note:
The trec period does not affect the RTC operation. Write protect only occurs when VCC is
below VRST. When VCC rises above VRST, the RTC will be selectable immediately. Only
the RST output is affected by the trec period.
The RST pin is an open drain output and an appropriate pull-up resistor to VCC should be
chosen to control the rise time.
20/58
M41T82 M41T83
3
Clock operation
Clock operation
The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of
32.768kHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz
crystal that is used as the time-base for the RTC.
The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both
set the clock and to read the date and time from the clock, in binary coded decimal format.
Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first
four registers.
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical).
Note:
Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST
bit to '0.' This provides an additional “kick-start” to the oscillator circuit.
Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the digital calibration register, while the analog calibration register is
found at address 12h (these are both described in the clock calibration section). For the
M41T83, bit D7 of register 09h (Watchdog register) contains the Oscillator Fail Interrupt
Enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the Oscillator
Fail bit (OF) (see Section 3.13: Oscillator fail detection on page 43) will also generate an
interrupt output.
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the ST bit and CB0-CB1 bits will result in an update of the system clock and a
reset of the divider chain. This could result in an inadvertent change of the current time.
These non-clock related bits should be written prior to setting the clock, and remain
unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
3.1
Power-down time-stamp
When a power failure occurs, the Halt Update bit (HT) will automatically be set to a “1”. This
will prevent the clock from updating the clock registers, and will allow the user to read the
exact time of the power-down event. Resetting the HT bit to a “0” will allow the clock to
update the clock with the current time. For more information, see Application note AN1572.
21/58
Clock operation
3.2
M41T82 M41T83
Clock/control register map
The M41T8x offers 32 internal registers which contain clock, calibration (digital and analog),
Alarm 1 and 2, Watchdog, Flags, Timer, and Square Wave (M41T83 only). The clock
registers are memory locations which contain external (user accessible) and internal copies
of the data (usually referred to as BiPORT™ TIMEKEEPER® cells). The external copies are
independent of internal functions except that they are updated periodically by the
simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain
will be reset upon the completion of a WRITE to any clock address (00h to 07h). The
system-to-user transfer of clock data will be halted whenever the address being read is a
clock address (00h to 07h). The update will resume either due to a Stop Condition or when
the pointer increments to a non-clock address. Clock and alarm registers store data in BCD
format. Calibration, Timer, Watchdog, and Square Wave bits are written in a binary format.
22/58
M41T82 M41T83
Table 2.
Clock operation
M41T82 clock/control register map (32 bytes)(1)
Addr
D7
00h
D6
D5
D4
D3
D2
0.1 seconds
D1
D0
Function/range BCD
format
0.01 seconds
seconds
00-99
01h
ST
10 seconds
seconds
seconds
00-59
02h
0
10 minutes
minutes
minutes
00-59
03h
CB1
CB0
Hours (24 hour format)
Century/hours
0-3/00-23
04h
0
0
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 hours
0
0
0
10 date
0
Day of week
10M
10 years
08h
0
FT
DCS
DC4
DC3
DC2
DC1
DC0
Digital calibration
09h
0
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
0Ah
0
0
ABE
Al1 10M
0Bh
RPT14
RPT15
0Ch
RPT13
HT
0Dh
RPT12
0Eh
RPT11
0Fh
WDF
Alarm1 month
Al1 month
01-12
AI1 10 date
Alarm1 date
Al1 date
01-31
AI1 10 hour
Alarm1 hour
Al1 hour
00-23
Alarm1 10 minutes
Alarm1 minutes
Al1 min
00-59
Alarm1 10 seconds
Alarm1 seconds
Al1 sec
00-59
AF1
AF2(2)
10h
BL
TF
OF
0
0
Timer countdown value
Flags
Timer value
11h
TE
0
0
0
0
0
TD1
TD0
Timer control
12h
ACS
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Analog calibration
13h
0
0
0
0
0
0
AL2E
0
SQW
14h
0
0
0
Al2 10M
15h
RPT24
RPT25
16h
RPT23
0
17h
RPT22
18h
RPT21
19h-1Fh
Alarm2 month
SRAM/Al2 month
01-12
AI2 10 date
Alarm2 month
SRAM/Al2 date
01-31
AI2 10 hour
Alarm2 date
SRAM/Al2 hour
00-23
Alarm2 10 minutes
Alarm2 minutes
SRAM/Al2 min
00-59
Alarm2 10 seconds
Alarm2 seconds
SRAM/Al2 sec
00-59
User SRAM (7 bytes)
SRAM
1. See Table 3: Key to Table 2 (M41T82 clock/control register map (32 bytes))
2. AF2 will always read ‘0’, if the AL2E bit is set to ‘0’.
23/58
Clock operation
Table 3.
M41T82 M41T83
Key to Table 2 (M41T82 clock/control register map (32 bytes))
Code
24/58
Explanation
0
Must be set to zero
ABE
Alarm in battery back-up Enable bit
AC0-AC6
Analog Calibration bits
ACS
Analog Calibration Sign bit
AF1, AF2
Alarm Flag bits
AL2E
Alarm 2 Enable bit
BL
Battery Low bit
BMB0-BMB4
Watchdog Multiplier bits
CB0, CB1
Century bits
DC0-DC4
Digital Calibration bits
DCS
Digital Calibration Sign bit
FT
Frequency test bit
HT
Halt Update bit
OF
Oscillator Fail bit
RB0-RB2
Watchdog Resolution bits
RPT11-RPT15
Alarm 1 Repeat Mode bits
RPT21-RPT25
Alarm 2 Repeat Mode bits
ST
Stop bit
TD0, TD1
Timer Frequency bits
TE
Timer Enable bit
TF
Timer Flag
WDF
Watchdog Flag
M41T82 M41T83
Clock operation
M41T83 clock/control register map (32 bytes)(1)
Table 4.
Addr
D7
00h
D6
D5
D4
D3
D2
0.1 seconds
D1
D0
Function/range BCD
format
0.01 seconds
seconds
00-99
01h
ST
10 seconds
seconds
seconds
00-59
02h
0
10 minutes
Minutes
Minutes
00-59
03h
CB1
CB0
Hours (24 hour format)
Century/hours
0-3/00-23
04h
0
0
Day
01-7
05h
0
0
Date: day of month
Date
01-31
06h
0
0
Month
Month
01-12
Year
Year
00-99
07h
10 hours
0
0
0
10 date
0
Day of week
10M
10 years
08h
OUT
FT
DCS
DC4
DC3
DC2
DC1
DC0
Digital calibration
09h
OFIE
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
0Ah
A1IE
SQWE
ABE
Al1
10M
0Bh
RPT14
RPT15
0Ch
RPT13
HT
0Dh
RPT12
0Eh
RPT11
0Fh
WDF
Alarm 1month
Al1 month
01-12
AI1 10 date
Alarm1 date
Al1 date
01-31
AI1 10 hour
Alarm1 hour
Al1 hour
00-23
Alarm1 10 minutes
Alarm1 minutes
Al1 min
00-59
Alarm1 10 seconds
Alarm1 seconds
Al1 sec
00-59
AF1
(2)
AF2
10h
BL
TF
OF
0
0
Timer countdown value
Flags
Timer value
11h
TE
TI/TP
TIE
0
0
0
TD1
TD0
Timer control
12h
ACS
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Analog
calibration
13h
RS3
RS2
RS1
RS0
0
0
AL2E
OTP
SQW
14h
A2IE
0
0
Al2
10M
15h
RPT24
RPT25
16h
RPT23
0
17h
RPT22
18h
RPT21
19h1Fh
Alarm2 month
SRAM/Al2 month
01-12
AI2 10 date
Alarm2 date
SRAM/Al2 date
01-31
AI2 10 hour
Alarm2 hour
SRAM/Al2 hour
00-23
Alarm2 10 minutes
Alarm2 minutes
SRAM/Al2 min
00-59
Alarm2 10 seconds
Alarm2 seconds
SRAM/Al2 sec
00-59
User SRAM (7 bytes)
SRAM
1. See Table 5: Key to Table 4 (M41T83 clock/control register map (32 bytes)).
2. AF2 will always read ‘0’, if the AL2E bit is set to ‘0’.
25/58
Clock operation
Table 5.
M41T82 M41T83
Key to Table 4 (M41T83 clock/control register map (32 bytes))
Code
26/58
Explanation
0
Must be set to zero
ABE
Alarm in battery back-up Enable bit
A1IE, A2IE
Alarm Interrupt Enable bits
AC0-AC6
Analog Calibration bits
ACS
Analog Calibration Sign bit
AF1, AF2
Alarm Flag
AL2E
Alarm 2 Enable bit
BL
Battery Low bit
BMB0-BMB4
Watchdog Multiplier bits
CB0, CB1
Century bits
DC0-DC4
Digital Calibration bits
DCS
Digital Calibration Sign bit
FT
Frequency Test bit
HT
Halt Update bit
OF
Oscillator Fail bit
OUT
Output level
OFIE
Oscillator Fail Interrupt Enable
OTP
OTP Control bit
RB0-RB2
Watchdog Resolution bits
RPT11-RPT15
Alarm 1 Repeat Mode bits
RPT21-RPT25
Alarm 2 Repeat Mode bits
RS0-RS3
SQW frequency
SQWE
Square Wave Enable
SRAM/ALM2
SRAM/Alarm 2 bit
ST
Stop bit
TD0, TD1
Timer Frequency bits
TE
Timer Enable bit
TF
Timer Flag
TI/TP
Timer Interrupt or Pulse
TIE
Timer Interrupt Enable
WDF
Watchdog Flag
M41T82 M41T83
3.3
Clock operation
Real Time Clock accuracy
The M41T8x is driven by a quartz controlled oscillator with a nominal frequency of
32,768Hz. The accuracy of the Real Time Clock is dependent upon the accuracy of the
crystal, and the match between the capacitive load of the oscillator circuit and the capacitive
load for which the crystal was trimmed. Temperature also affects the crystal frequency,
causing additional error (see Figure 17 on page 31).
The M41T8x provides the option of clock correction through either manufacturing calibration
or in-application calibration. The total possible compensation is typically –93 ppm to +156
ppm. The two compensation circuits that are available are:
1.
An Analog Calibration register (12h) can be used to adjust internal (on-chip) load
capacitors for oscillator capacitance trimming. The individual load capacitors CXI and
CXO (see Figure 16), are selectable from a range of –18pF to +9.75pF in steps of
0.25pF. This translates to a calculated compensation of approximately ±30 ppm (see
Section 3.4.2: Analog calibration (programmable load capacitance) on page 30).
2.
A Digital Calibration register (08h) can also be used to adjust the clock counter by
adding or subtracting a pulse at the 512Hz divider stage. This approach provides
periodic compensation of approximately –63 ppm to +126 ppm (see Section 3.4.1:
Digital calibration (periodic counter correction) on page 28).
Figure 16. Internal load capacitance adjustment
XI
CXI
Crystal Oscillator
XO
CXO
AI11804
27/58
Clock operation
3.4
M41T82 M41T83
Clock calibration
The M41T8x oscillator is designed for use with a 12.5pF crystal load capacitance. When the
calibration circuit is properly employed, accuracy improves to better than ±1 ppm at 25°C.
The M41T8x design provides the following two methods for clock error correction.
3.4.1
Digital calibration (periodic counter correction)
This method employs the use of periodic counter correction by adjusting the ratio of the
100Hz divider stage to the 512Hz divider stage. Under normal operation, the 100Hz divider
stage outputs precisely 100 pulses for every 512 pulses of the 512Hz input stage to provide
the input frequency to the Fraction of Seconds Clock register. By adjusting the number of
512Hz input pulses used to generate 100 output pulses, the clock can be sped up or slowed
down, as shown in Figure 19 on page 34.
When a non-zero value is loaded into the five Calibration bits (DC4 – DC0) found in the
Digital Calibration Register (08h) and the sign bit is ‘1’, (indicating positive calibration), the
100Hz stage outputs 100 pulses for every 511 input pulses instead of the normal 512. Since
the 100 pulses are now being output in a shorter window, this has the effect of speeding up
the clock by 1/512 seconds for each second the circuit is active. Similarly, when the sign bit
is ‘0’, indicating negative calibration, the block outputs 100 pulses for every 513 input
pulses. Since the 100 pulses are then being output in a longer window, this has the effect of
slowing down the clock by 1/512 seconds for each second the circuit is active.
The amount of calibration is controlled by using the value in the calibration register (N) to
generate the adjustment in one second increments. This is done N times per minute, for
every minute, for positive calibration, and N times per minute every other minute for
negative calibration (see Table 6 on page 29).
For example, if the Calibration register is set to '100010,' then the adjustment will occur for
two seconds in every minute. Similarly, if the calibration register is set to '000011,' then the
adjustment will occur for 3 seconds in every alternating minute.
The Digital Calibration bits (DC4 – DC0) occupy the five lower order bits in the Digital
Calibration Register (08h). These bits can be set to represent any value between 0 and 31
in binary form. The sixth bit (DCS) is a Sign bit; '1' indicates positive calibration, '0' indicates
negative calibration. Calibration occurs within an 8-minute (positive) or 16-minute (negative)
cycle. Therefore, each calibration step has an effect on clock accuracy of +4.068 or –2.034
ppm. Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments
in the Calibration byte would represent +10.7 or –5.35 seconds per month, which
corresponds to a total range of +5.5 or –2.75 minutes per month.
Note:
28/58
The modified pulses are not observable on the Frequency Test (FT) output, nor will the
effect of the calibration be measurable real-time, due to the periodic nature of the error
compensation.
M41T82 M41T83
Table 6.
Clock operation
Digital calibration values
Calibration value (binary)
Calibration value rounded to the nearest ppm
DC4 – DC0
Negative calibration (DCS = 0) Positive calibration (DCS = 1)
0 (00000)
0
0
1 (00001)
-2
4
2 (00010)
-4
8
3 (00011)
-6
12
4 (00100)
-8
16
5 (00101)
-10
20
6 (00110)
-12
24
7 (00111)
-14
28
8 (01000)
-16
33
9 (01001)
-18
37
10 (01010)
-20
41
11 (01011)
-22
45
12 (01100)
-24
49
13 (01101)
-26
53
14 (01110)
-28
57
15 (01111)
-31
61
16 (10000)
-33
65
17 (10001)
-35
69
18 (10010)
-37
73
19 (10011)
-39
77
20 (10100)
-41
81
21 (10101)
-43
85
22 (10110)
-45
90
23 (10111)
-47
94
24 (11000)
-49
98
25 (11001)
-51
102
26 (11010)
-53
106
27 (11011)
-55
110
28 (11100)
-57
114
29 (11101)
-59
118
30 (11110)
-61
122
31 (11111)
-63
126
N
N/491520 (per minute)
N/245760 (per minute)
29/58
Clock operation
3.4.2
M41T82 M41T83
Analog calibration (programmable load capacitance)
A second method of calibration employs the use of programmable internal load capacitors
to adjust (or trim) the oscillator frequency.
By design, the oscillator is intended to be 0 ppm ± crystal accuracy at room temperature
(25°C, see Figure 17 on page 31). For a 12.5pF crystal, the default loading on each side of
the crystal will be 25pF. For incrementing or decrementing the calibration value,
capacitance will be added or removed in increments of 0.25pF to each side of the crystal.
Internally, CLOAD of the oscillator is changed via two digitally controlled capacitors, CXI and
CXO, connected from the XI and XO pins to ground (see Figure 16 on page 27). The
effective on-chip series load capacitance, CLOAD, ranges from 3.5pF to 17.4pF, with a
nominal value of 12.5pF (AC0-AC6 = ‘0’).
The effective series load capacitance (CLOAD) is the combination of CXI and CXO:
C LOAD = 1 ⁄ ( 1 ⁄ C XI + 1 ⁄ C XO )
Seven analog calibration bits, AC0 to AC6, are provided in order to adjust the on-chip load
capacitance value for frequency compensation of the RTC. Each bit has a different weight
for capacitance adjustment. An Analog Calibration Sign (ACS) bit determines if capacitance
is added (ACS bit = ‘0’, negative calibration) or removed (ACS bit = ‘1’, positive calibration).
The majority of the calibration adjustment is positive (i.e. to increase the oscillator frequency
by removing capacitance) due to the typical characteristic of quartz crystals to slow down
due to changes in temperature, but negative calibration is also available.
Since the Analog Calibration Register adjustment is essentially “pulling” the frequency of the
oscillator, the resulting frequency changes will not be linear with incremental capacitance
changes. The equations which govern this mechanism indicate that smaller capacitor
values of Analog Calibration adjustment will provide larger increments. Thus, the larger
values of Analog Calibration adjustment will produce smaller incremental frequency
changes. These values typically vary from 6-10 ppm/bit at the low end to <1 ppm/bit at the
highest capacitance settings. The range provided by the Analog Calibration Register
adjustment with a typical surface mount crystal is approximately ±30 ppm around the AC6AC0 = 0 default setting because of this property (see Table 7 on page 31).
30/58
M41T82 M41T83
Clock operation
Figure 17. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
ΔF = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Table 7.
Addr
Analog calibration values
Analog
calibration
value
CXI,
CXO
CLOAD(1)
D7
D6
D5
D4
D3
D2
D1
D0
ACS
AC6
AC5
AC4
AC3
AC2
AC1
AC0
(±)
(16pF)
(8pF)
(4pF)
(2pF)
(1pF)
0pF
x
0
0
0
0
0
0
0
25pF
12.5pF
3pF
0
0
0
0
1
1
0
0
28pF
14pF
5pF
0
0
0
1
0
1
0
0
30pF
15pF
–7pF
½(CXI, CXO)
(0.5pF) (0.25pF)
12h
1
0
0
1
1
1
0
0
18pF
9pF
(2))
0
0
1
0
0
1
1
1
34.75pF
17.4pF
–18pF(3)
1
1
0
0
1
0
0
0
7pF
3.5pF
9.75pF
1. CLOAD = 1/(1/CXI + 1/CXO)
2. Maximum negative calibration value
3. Maximum positive calibration value
31/58
Clock operation
M41T82 M41T83
The on-chip capacitance can be calculated as follows:
1
C LOAD = --- [ ( AC6 – AC0 value, decimal) × 0.25pF ] + 25pF
2
For example:
●
CLOAD (12h = x0000000) = 12.5pF,
●
CLOAD (12h =11001000) = 3.5pF, and
●
CLOAD (12h = 00100111) = 17.4pF.
The oscillator sees a minimum of 3.5pF with no programmable load capacitance selected.
Note:
These are typical values, and the total load capacitance seen by the crystal will include
approximately 1-2pF of package and board capacitance in addition to the Analog Calibration
register value.
Any invalid value of Analog Calibration will result in the default capacitance of 25pF.
The combination of analog and digital trimming can give up to –93 to +156 ppm of the total
adjustment.
Figure 18 on page 33 represents a typical curve of clock ppm adjustment versus the Analog
Calibration value. This curve may vary with different crystals, so it is good practice to
evaluate the crystal to be used with an M41T8x device before establishing the adjustment
values for the application in question.
32/58
M41T82 M41T83
Clock operation
Figure 18. Clock accuracy vs. on-chip load capacitance
100.0
XI
XO
PPM ADJUSTMENT
80.0
Crystal
Oscillator
60.0
CXI
CXO
40.0
CLOAD =
20.0
CXI * CXO
CXI + CXO
On-Chip
FASTER
DECREASING LOAD CAP.
INCREASING LOAD CAP.
0.0
SLOWER
-20.0
OFFSET TO
CXI, C XO (pF)
NET EQUIV. LOAD
CAP., C LOAD , (pF)
Analog Calibration
Value, AC,
register 0x12
-18.0 -15.0
3.5
5.0
0xC8 0xBC
-10.0
-5.0
0.0
5.0
9.75
7.5
10
12.5
15
17.4
0xA8
0x94
0x00
0x14
0x27
ai13906
33/58
Clock operation
M41T82 M41T83
Two methods are available for ascertaining how much calibration a given M41T8x may
require:
Note:
●
The first involves setting the clock, letting it run for a month and comparing it to a
known accurate reference and recording deviation over a fixed period of time. This
allows the designer to give the end user the ability to calibrate the clock as the
environment requires, even if the final product is packaged in a non-user serviceable
enclosure. The designer could provide a simple utility that accesses either or both of
the Calibration bytes.
●
The second approach is better suited to a manufacturing environment, and involves the
use of the IRQ1/FT/OUT pin. The IRQ1/FT/ OUT pin will toggle at 512Hz when FT and
OUT bits = '1' (M41T83 only) and ST = '0.' Any deviation from 512Hz indicates the
degree and direction of oscillator frequency shift at the test temperature. For example,
a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error,
requiring either a –10 (xx001010) to be loaded into the Digital Calibration byte, or +6pF
(00011000) into the Analog Calibration byte for correction.
Setting or changing the Digital Calibration byte does not affect the Frequency Test, Square
Wave, or Watchdog Timer frequency, but changing the Analog Calibration byte DOES affect
all functions derived from the low current oscillator (see Figure 19).
Figure 19. Clock divider chain and calibration circuits
512Hz Output
Frequency Test
÷2
÷2
÷2
÷2
÷2
Remainder of
Divider Circuit
Square Wave
Watchdog Timer
8-bit Timer
CXI
Low Current
Oscillator
32KHz
÷8
CXO
Clock
Registers
1Hz Signal
Analog Calibration
Circuitry
34/58
Digital Calibration Circuitry
(divide by 511/512/513)
AI11806c
M41T82 M41T83
Clock operation
Figure 20. Crystal isolation example
Crystal
Local Grounding
Plane (Layer 2)
XI XO
VSS
AI11814
1. Substrate pad should be tied to VSS.
3.5
Setting the alarm clock registers
Address locations 0Ah-0Eh (Alarm 1) and 14h-18h (Alarm 2) contain the alarm settings.
Either alarm can be configured independently to go off at a prescribed time on a specific
month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or
second. Bits RPT15–RPT11 and RPT25-RPT21 put the alarms in the repeat mode of
operation. Table 8 on page 37 shows the possible bit configurations.
Codes not listed in the table default to the once-per-second mode to quickly alert the user of
an incorrect alarm setting. When the clock information matches the alarm clock settings
based on the match criteria defined by RPT15–RPT11 and/or RPT25-RPT21, AF1 (Alarm 1
Flag) or AF2 (Alarm 2 Flag) is set. If A1IE (Alarm 1 Interrupt Enable), or A2IE (Alarm 2
Interrupt Enable) are also set, the alarm condition activates either the IRQ1/FT/OUT, or
IRQ2 output pins. To disable either of the alarms, write a '0' to the Alarm Date Registers and
to the RPTx5–RPTx1 bits.
Note:
If the address pointer is allowed to increment to the Flag Register address, or the last
address written is “Alarm Seconds,” the address pointer will increment to the Flag address,
and an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is
moved to a different address.
The IRQ output is cleared by a READ to the Flags Register (0Fh) as shown in Figure 21. A
subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag
has been reset to '0.'.
35/58
Clock operation
3.6
M41T82 M41T83
Optional second programmable alarm
When the Alarm 2 Enable (AL2E) bit (D1 of address 13h) is set to a logic ‘1’, registers 14h
through 18h provide control for a second programmable alarm which operates in the same
manner as the alarm function described above. The A2IE (Alarm 2 Interrupt Enable) bit
allows the second alarm to trigger a separate interrupt output (IRQ2).
The AL2E bit defaults on initial power-up to a logic ‘0’ (Alarm 2 disabled). In this mode, the
five address bytes (14h-18h) function as additional user SRAM, for a total of 12 bytes of
user SRAM.
The IRQ1/FT/OUT pin can also be activated in the battery back-up mode (see Figure 22 on
page 36).
Figure 21. Alarm interrupt reset waveform
0Eh
0Fh
00h
ALARM FLAG BITS (AFx)
HIGH-Z
IRQ1/FT/OUT or
IRQ2
AI08898
Figure 22. Back-up mode alarm waveform
VCC
VPFD
VSO
trec
AF Bit in Flags
Register
IRQ1/FT/OUT or
IRQ2
HIGH-Z
AI09164c
1. ABE and A1IE bits = 1.
36/58
M41T82 M41T83
Table 8.
3.7
Clock operation
Alarm repeat modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm setting
1
1
1
1
1
Once per second
1
1
1
1
0
Once per minute
1
1
1
0
0
Once per hour
1
1
0
0
0
Once per day
1
0
0
0
0
Once per month
0
0
0
0
0
Once per year
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1
second, and 11 = 4 seconds. The amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the resolution. (For example: writing
00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset
the timer within the specified period, the M41T8x sets the WDF (Watchdog Flag) and
generates a watchdog interrupt.
The watchdog timer can be reset by having the microprocessor perform a WRITE of the
Watchdog Register. The time-out period then starts over.
Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog
Register in order to clear the IRQ1/FT/OUT pin. This will also disable the watchdog function
until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog
Flag (bit D7; Register 0Fh).
The watchdog function is automatically disabled upon power-up and the Watchdog Register
is cleared. If the watchdog function is set, the frequency test function is activated, and the
SQWE bit is '0,' the watchdog function prevails and the frequency test function is denied.
37/58
Clock operation
3.8
M41T82 M41T83
8-bit (countdown) timer
The Timer Value Register is an 8-bit binary countdown timer. It is enabled and disabled via
the Timer Control Register (11h) TE bit. Other timer properties such as the source clock, or
interrupt generation are also selected in the Timer Control Register (see Table 9). For
accurate read back of the countdown value, the I2C-bus clock (SCL) must be operating at a
frequency of at least twice the selected timer clock.
The Timer Control register selects one of four source clock frequencies for the timer (4096,
64, 1, or 1/60Hz), and enables/disables the timer. The timer counts down from a softwareloaded 8-bit binary value. At the end of every countdown, the timer sets the Timer Flag (TF)
bit. The TF bit can only be cleared by software. When asserted, the timer flag (TF) can also
be used to generate an interrupt (IRQ1/FT/OUT) on the M41T83. The interrupt may be
generated as a pulsed signal every countdown period or as a permanently active signal
which follows the condition of TF. The Timer Interrupt/Timer Pulse (TI/TP) bit is used to
control this mode selection. When reading the timer, the current countdown value is
returned.
Table 9.
Timer control register map(1)
Addr
D7
D6
D5
D4
D3
D2
D1
D0
Function
0Fh
WDF
AF1
AF2
BL
TF
OF
0
0
Flags
10h
11h
Timer countdown value
TE
TI/TP
TIE
0
0
Timer value
0
TD1
TD0
Timer control
1. Bit positions labeled with ‘0’ should always be written with logic '0.'
3.8.1
Timer Interrupt/Timer Pulse (TI/TP, M41T83 only)
●
TI/TP = 0
IRQ1/FT/OUT is active when TF is logic '1' (subject to the status of the Timer Interrupt
Enable bit (TIE).
●
TI/TP = 1
IRQ1/FT/OUT pulses are active when TF is logic '1' according to Table 10 (subject to
the status of the TIE bit).
Note:
38/58
If an Alarm condition, Watchdog time-out, Oscillator Failure, or OUT = 0 causes
IRQ1/FT/OUT to be asserted low, then IRQ1/FT/OUT will remain asserted even if TI/TP is
set to '1'. When in pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on
IRQ1/FT/OUT. The output pulses will only stop if TE, TIE, or TI/TP are reset to '0'.
M41T82 M41T83
Clock operation
Table 10.
Interrupt operation (bit TI/TP = 1)
IRQ(1) periods
Source clock (Hz)
n(2) = 1
n>1
4096
1/8192
1/4096
64
1/128
1/64
1
1/64
1/64
1/60
1/64
1/64
1. TF and IRQ1/FT/OUT become active simultaneously.
2. n = loaded countdown timer value. The timer is stopped when n = 0.
3.8.2
Timer Flag (TF)
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are
required in the application, the source of the interrupt can be determined by reading the flag
bits. The timer will auto-reload and continue to count down regardless of the state of TF bit
(or TI/TP bit). The TF bit is cleared by reading the Flags Register.
3.8.3
Timer Interrupt Enable (TIE, M41T83 only)
In Level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To
clear the interrupt, the TF bit or the TIE bit must be reset.
3.8.4
Timer Enable (TE)
●
TE = 0
When the Timer Register (10h) is set to ‘0’, the timer is disabled.
●
TE = 1
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin from the same value as when it was disabled.
3.8.5
TD1/0
These are the timer source clock frequency selection bits (see Table 11). These bits
determine the source clock for the countdown timer (see Table 12). When not in use, the
TD1 and TD0 bits should be set to ‘11’ (1/60Hz) for power saving.
Table 11.
Timer source clock frequency selection (244.1µs to 4.25 hrs)
TD1
TD0
Timer source clock frequency (Hz)
0
0
4096 (244.1µs)
0
1
64 (15.6ms)
1
0
1 (1s)
1
1
1/60 (60s)
39/58
Clock operation
M41T82 M41T83
Table 12.
Timer countdown value register bits (addr 11h)(1)
Bit
Symbol
7-0
<timer countdown value>
Description
This register holds the loaded countdown value ‘n’.
Countdown period = n / source clock frequency.
1. Writing to the timer register will not reset the TF bit or clear the interrupt.
40/58
M41T82 M41T83
3.9
Clock operation
Square wave output (M41T83 only)
The M41T83 offers the user a programmable square wave function which is output on the
SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These
frequencies are listed in Table 13. Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the Square
Wave Enable bit (SQWE) located in Register 0Ah.
Note:
If the SQWE bit is set to '1' and VCC falls below the switchover (VSO) voltage, the square
wave output will be disabled.
Table 13.
Square wave output frequency
Square wave bits
Square wave
RS3
RS2
RS1
RS0
Frequency
Units
0
0
0
0
None
–
0
0
0
1
32.768
kHz
0
0
1
0
8.192
kHz
0
0
1
1
4.096
kHz
0
1
0
0
2.048
kHz
0
1
0
1
1.024
kHz
0
1
1
0
512
Hz
0
1
1
1
256
Hz
1
0
0
0
128
Hz
1
0
0
1
64
Hz
1
0
1
0
32
Hz
1
0
1
1
16
Hz
1
1
0
0
8
Hz
1
1
0
1
4
Hz
1
1
1
0
2
Hz
1
1
1
1
1
Hz
41/58
Clock operation
3.10
M41T82 M41T83
Battery low warning
The M41T8x automatically performs battery voltage monitoring upon power-up and at
factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) bit, bit
D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than
approximately 2.5V. The BL bit will remain asserted until completion of battery replacement
and subsequent battery low monitoring tests, either during the next power-up sequence or
the next scheduled 24-hour interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity. Clock data
should be considered suspect and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal VCC is supplied. In order to insure data integrity during subsequent periods of
battery back-up mode, the battery should be replaced.
The M41T8x only monitors the battery when a nominal VCC is applied to the device. Thus
applications which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.11
Century bits
These two bits will increment in a binary fashion at the turn of the century, and handle all
leap years correctly. See Table 14 for additional explanation.
Table 14.
Century bits examples
CB0
CB1
Leap Year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by
100. The only exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year
2100 is not).
3.12
Output driver pin
When the OFIE bit, A1IE bit, and Watchdog Register are not set to generate an interrupt,
the IRQ1/FT/OUT pin becomes an output driver that reflects the contents of D7 of register
08h. In other words, when D7 (OUT bit) is a '0,' then the IRQ1/FT/OUT pin will be driven low.
Note:
42/58
The IRQ1/FT/OUT pin is an open drain which requires an external pull-up resistor.
M41T82 M41T83
3.13
Clock operation
Oscillator fail detection
If the Oscillator Fail (OF) bit is internally set to a '1,' this indicates that the oscillator has
either stopped, or was stopped for some period of time. This bit can be used to judge the
validity of the clock and date data. This bit will be set to '1' any time the oscillator stops.
In the event the OF bit is found to be set to '1' at any time other than the initial power-up, the
STOP bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the
oscillator. The following conditions can cause the OF bit to be set:
●
Note:
The first time power is applied (defaults to a '1' on power-up).
If the OF bit cannot be written to '1' 4 seconds after the initial power-up, the STOP bit (ST)
should be written to a '1,' then immediately reset to '0.'
●
The voltage present on VCC or battery is insufficient to support oscillation.
●
The ST bit is set to '1.'
●
External interference of the crystal
For the M41T83, if the Oscillator Fail Interrupt Enable bit (OFIE) is set to a '1,' the
IRQ1/FT/OUT pin will also be activated. The IRQ1/FT/OUT output is cleared by resetting
the OFIE or OF bit to '0' (NOT by reading the Flag Register).
The OF bit will remain set to '1' until written to logic '0.' The oscillator must start and have
run for at least 4 seconds before attempting to reset the OF bit to '0.' If the trigger event
occurs during a power down condition, this bit will be set correctly.
3.14
Oscillator Fail Interrupt Enable (M41T83 only)
If the Oscillator Fail Interrupt Enable bit (OFIE) is set to a '1,' the IRQ1/FT/OUT pin will also
be activated. The IRQ1/FT/OUT output is cleared by resetting the OFIE or OF bit to '0' (not
by reading the Flags Register).
43/58
Clock operation
3.15
M41T82 M41T83
Initial power-on defaults
Upon initial application of power to the device, the register bits will initially power-on in the state indicated
in Table 15 and Table 16.
Table 15.
Initial power-on default values (part 1)
Condition(1)
Initial
Power-up
Subsequent
Power-up(4) (5)
ST
CB1 CB0 OUT
DCS Digital Analog OFIE Watchdog A1IE SQWE
ABE
(2)
(3)
(2)
(2)
ACS calib. calib.
FT
0
0
0
1
0
0
0
0
0
0
0
1
0
UC
UC
UC
UC
0
UC
UC
UC
UC
0
UC
UC
UC
1. All other control bits power-up in an undetermined state.
2. M41T83 only.
3. BMB0-BMB4, RB0, RB1.
4. With battery back-up.
5. UC = Unchanged.
Table 16.
Initial power-up default values (part 2)
Condition(1)
RPT11-15 HT
Initial
Power-up
Subsequent
Power-up(3) (4)
OF
TE
TI/TP TIE
(2)
(2)
TD1 TD0 RS0 RS1-3
OTP A2IE
(2)
(2)
RPT2125
AL2E
0
1
1
0
0
0
1
1
1
0
0
0
0
0
UC
1
UC
0
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1. All other control bits power-up in an undetermined state.
2. M41T83 only.
3. With battery back-up.
4. UC = Unchanged.
3.16
OTP bit operation (M41T83 only)
When the OTP (One Time Programmable) bit is set to a '1,' the value in the internal OTP registers will be
transferred to the analog calibration register (12h) and are “Read only.” The OTP value is programmed
by the manufacturer, and will contain the calibration value necessary to achieve ±5 ppm at room
temperature.
If the OTP bit is set to '0,' the analog calibration register will become a WRITE/READ register and
function like standard SRAM memory cells, allowing the user to implement any desired value of analog
calibration.
When the user sets the OTP bit, they need to wait for approximately 3 to 4ms before the analog registers
transfer the value from the OTP to the analog registers due to the OTP Read operation.
44/58
M41T82 M41T83
4
Maximum rating
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 17.
Absolute maximum ratings
Sym
Parameter
Value(1)
Unit
TSTG
Storage temperature (VCC off, Oscillator off)
–55 to 125
°C
VCC
Supply voltage
–0.3 to 7.0
V
260
°C
–0.2 to Vcc+0.3
V
TSLD(2)
VIO
Lead solder temperature for 10 seconds
Input or Output voltages
IO
Output current
20
mA
PD
Power dissipation
1
W
1. Data based on characterization results, not tested in production.
2. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30
seconds).
45/58
DC and ac parameters
5
M41T82 M41T83
DC and ac parameters
This section summarizes the operating and measurement conditions, as well as the dc and
ac characteristics of the device. The parameters in the following dc and ac Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 18.
Operating and ac measurement conditions(1)
Parameter
M41T8x
Supply voltage (VCC)
2.38V to 5.5V
Ambient operating temperature (TA)
–40 to 85°C
Load capacitance (CL)
50pF
Input Rise and Fall times
≤ 5ns
Input Pulse voltages
0.2VCC to 0.8 VCC
Input and Output timing ref. voltages
0.3VCC to 0.7 VCC
1. Output Hi-Z is defined as the point where data is no longer driven.
Figure 23. Measurement ac I/O waveform
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Table 19.
Capacitance
Parameter(1,2)
Symbol
CIN
COUT
tLP
(3)
Min
Max
Unit
Input capacitance
7
pF
Output capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
46/58
M41T82 M41T83
Table 20.
Sym
DC and ac parameters
DC characteristics
Test condition(1)
Min
Operating voltage (S)
–40 to 85°C
Operating voltage (R)
Max
Unit
3.00
5.50
V
–40 to 85°C
2.70
5.50
V
Operating voltage (Z)
–40 to 85°C
2.38
5.50
V
ILI
Input leakage current
0V ≤ VIN ≤ VCC
±1
μA
ILO
Output leakage current
0V ≤ VOUT ≤ VCC
±1
μA
150
µA
VCC
ICC1
ICC2
Parameter
Supply current
SCL = 400kHz
(No load)
SCL = 0Hz;
Supply current (standby) All inputs ≥ VCC – 0.2V or ≤
VSS + 0.2V (SQWE bit = 0)
Typ
5.5V
125
3.0V
55
µA
2.5 (Z only)
45
µA
5.5V
8
3.0V
7
µA
2.5 (Z only)
6
µA
10
µA
VIL
Input Low voltage
–0.3
0.3VCC
V
VIH
Input High voltage
0.7VCC
VCC+0.3
V
VOL
VOH
Output Low voltage
Output High voltage
Pull-up supply voltage
(open drain)
RST, FT/RST
VCC/VBAT = 3.0V,
IOL = 1.0mA
0.4
V
SQW, IRQ1/FT/OUT
VCC = 3.0V,
IOL = 1.0mA
0.4
V
SCL, SDA
VCC = 3.0V,
IOL = 3.0mA
0.4
V
VCC = 3.0V, IOH = –1.0mA (push-pull)
2.4
V
IRQ1/FT/OUT
5.5
V
VBAT
Battery back-up supply
voltage(2)
2.5
5.5
V
VCAP
Capacitor back-up
supply voltage
2.0
5.5
V
IBAT
Battery supply current
450
nA
25°C; VCC = 0V; OSC On;
VBAT = 3V; 32KHz Off
365
1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.38V to 5.5V (except where noted).
2. For non-rechargeable Lithium battery.
47/58
DC and ac parameters
Table 21.
M41T82 M41T83
Crystal electrical characteristics
Parameter(1) (2)
Symbol
fO
Min
Resonant frequency
RS
Series resistance
CL
Load capacitance
Typ
Max
32.768
Units
kHz
65
(3)
kΩ
12.5
pF
1. Externally supplied if using the QFN16 or SO8 package. STMicroelectronics recommends the Citizen CFS145 (1.5x5mm) and the KDS DT-38 (3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surfacemount, tuning fork-type quartz crystals.
KDS can be contacted at [email protected] or http://www.kdsj.co.jp.
Citizen can be contacted at [email protected] or http://www.citizencrystal.com.
2. Load capacitors are integrated within the M41T8x. Circuit board layout considerations for the 32.768kHz
crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
Table 22.
Oscillator characteristics
Parameter(1) (2)
Symbol
VSTA
Oscillator start voltage
tSTA
Oscillator start time
CXI, CXO(1)
Min
≤ 4s
2.0
1. With default analog calibration value ( = 0).
2. Reference value.
3. TA = 25°C, VCC = 5.0V.
Typ
(2) (3)
Max
1
25
–10
Units
V
VCC = VSO
Capacitor Input, Capacitor Output
IC-to-IC frequency variation
48/58
Conditions
s
pF
+10
ppm
M41T82 M41T83
DC and ac parameters
Figure 24. Power down/up mode ac waveforms
VCC
VSO
tPD
trec
SDA
SCL
DON'T CARE
AI00596
Table 23.
Power down/up trip points dc characteristics
Parameter(1) (2) (1,2)
Sym
VRST
Reset threshold voltage
Min
Typ
Max
Unit
S
2.85
2.93
3.0
V
R
2.55
2.63
2.7
V
Z
2.25
2.32
2.38
V
Battery back-up switchover
VSO
Hysteresis
Reset Pulse width (VCC Rising)
trec
VCC to Reset Delay, VCC = (VRST + 100mV), falling to
(VRST – 100mV; for VCC slew rate of 10mV/µs
VRST
V
25
mV
140
280
2.5
ms
µs
1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.38 to 5.5V (except where noted).
49/58
DC and ac parameters
M41T82 M41T83
Figure 25. Bus timing requirement sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
tSU:ST
SR
P
AI00589
Table 24.
AC characteristics
Parameter(1)
Sym
Min
Typ
Max
Units
400
kHz
fSCL
SCL clock frequency
tLOW
Clock low period
1.3
µs
tHIGH
Clock high period
600
ns
0
tR
SDA and SCL Rise time
300
ns
tF
SDA and SCL Fall time
300
ns
tHD:STA
START condition Hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition Setup time
(only relevant for a repeated start condition)
600
ns
100
ns
0
µs
tSU:DAT(2) Data Setup time
tHD:DAT
Data Hold time
tSU:STO
STOP condition Setup time
600
ns
Time the bus must be free before a new transmission
can start
1.3
µs
tBUF
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.38 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling
edge of SCL.
50/58
M41T82 M41T83
6
Package mechanical information
Package mechanical information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
51/58
Package mechanical information
M41T82 M41T83
Figure 26. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm body size outline
D
E
A3
A1
A
ddd C
e
b
L
1
2
E2
3
D2
QFN16-A
1. Drawing is not to scale.
Table 25.
QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm mech. data
mm
inches
Sym
52/58
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.031
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.30
0.25
0.35
0.012
0.010
0.014
D
4.00
3.90
4.10
0.157
0.154
0.161
D2
–
2.50
2.80
–
0.098
0.110
E
4.00
3.90
4.10
0.157
0.154
0.161
E2
–
2.50
2.80
–
0.098
0.110
e
0.65
–
–
0.026
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
M41T82 M41T83
Package mechanical information
Figure 27. QFN16 – 16-lead, quad, flat package, no lead, 4 x 4 mm, recommended
footprint
2.70
0.70
0.20
4.50
2.70
0.35
0.325
0.65
AI11815
1. Dimensions are shown in millimeters (mm).
Figure 28. 32KHz crystal + QFN16 vs. VSOJ20 mechanical data
6.0 ± 0.2
3.2
VSOJ20
SMT
CRYSTAL
1.5
7.0 ± 0.3
13
XO
XI
14
16
3.9
15
1
2
3
ST QFN16
4
3.9
AI11816
1. Dimensions shown are in millimeters (mm).
53/58
Package mechanical information
M41T82 M41T83
Figure 29. SOX18 – 18-lead plastic small outline, 300mils, embedded crystal, outline
D
9
h x 45°
1
C
E
10
H
18
A2
A
B
ddd
A1
e
A1
α
L
SO-J
1. Drawing is not to scale.
Table 26.
SOX18 – 18-lead plastic small outline, 300mils, embedded crystal,
package mech.
millimeters
inches
Symbol
54/58
Typ
Min
Max
Typ
Min
Max
A
2.57
2.44
2.69
0.101
0.096
0.106
A1
0.23
0.15
0.31
0.009
0.006
0.012
A2
2.34
2.29
2.39
0.092
0.090
0.094
B
0.46
0.41
0.51
0.018
0.016
0.020
c
0.25
0.20
0.31
0.010
0.008
0.012
D
11.61
11.56
11.66
0.457
0.455
0.459
E
7.62
7.57
7.67
0.300
0.298
0.302
E1
10.34
10.16
10.52
0.407
0.400
0.414
e
1.27
–
–
0.050
–
–
L
0.66
0.51
0.81
0.026
0.020
0.032
M41T82 M41T83
Package mechanical information
Figure 30. SO8 – 8-lead plastic small package outline
h x 45˚ h x 45˚
A2
A
A2
A
c
ccc
b
B
e
ddd
e
0.25 mm
GAUGE PLANE
D
D
C
k
8
8
1
1
E1
E E
H
L
A1
A1
α
L
L1
SO-A
SO-A
1. Drawing is not to scale.
Table 27.
SO8 – 8-lead plastic small outline (150 mils body width), package mech.
data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
1.75
Max
0.069
A1
0.10
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.009
ccc
0.25
0.004
0.010
0.049
0.10
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
-
-
0.050
-
-
h
0.25
0.50
0.010
0.020
k
0°
8°
0°
8°
L
0.40
0.127
0.016
0.050
L1
1.04
0.041
55/58
Part numbering
7
M41T82 M41T83
Part numbering
Table 28.
Ordering information
Example:
M41T
83
R
QA
6
E
Device family
M41T
Device type
82 (SO8 package only)
83
Operating voltage
S = VCC = 3.00 to 5.5V
R = VCC = 2.70 to 5.5V
Z = VCC = 2.38 to 5.5V
Package
QA = QFN16 (4mm x 4mm)
M(1) = SO8
MY(2) (3)= SOX18
Temperature range
6 = –40°C to 85°C
Shipping method
E = ECOPACK package, Tubes
F = ECOPACK package, Tape & Reel
1. M41T82.
2. Contact local ST sales office for availability.
3. The SOX18 package includes an embedded 32,768Hz crystal.
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
56/58
M41T82 M41T83
8
Revision history
Revision history
Date
Revision
27-Jul-2006
1
First edition
2
Updated package mechanical data in Figure 30: SO8 – 8-lead plastic
small package outline and Table 27: SO8 – 8-lead plastic small outline
(150 mils body width), package mech. data; small text changes for
entire document, amended footnotes in Table 1, Table 14 and
Figure 5.
19-Dec-2006
3
Document status upgraded to full datasheet; added footnote to diagram
in Features; amended footnotes in Figure 2 and updated footnotes in
Table 28; updated ‘typical data’ for ICC1 and ICC2 in Table 20; Updated
package mechanical data for the QFN16 and SOX18 in Section 6;
changed kHz to KHz through document; made small text changes
throughout document.
08-Mar-2007
4
Updated cover page (features and amended footnote concerning
availability), Figure 18: Clock accuracy vs. on-chip load capacitance,
and ordering information (Table 28).
17-Oct-2006
Changes
57/58
M41T82 M41T83
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