STMICROELECTRONICS M48T12

M48T02
M48T12
5.0V, 16 Kbit (2Kb x 8) TIMEKEEPER® SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, and POWER-FAIL
CONTROL CIRCUIT
■
BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, and SECONDS
■
TYPICAL CLOCK ACCURACY OF ±1 MINUTE
A MONTH, AT 25°C
■
SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
■
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T02: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V
– M48T12: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
SELF-CONTAINED BATTERY and CRYSTAL
IN THE CAPHAT™ DIP PACKAGE
■
■
Figure 1. 24-pin PCDIP, CAPHAT™ Package
24
1
PCDIP24 (PC)
Battery/Crystal
CAPHAT
PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 2K x 8 SRAMs
March 2003
Rev. 3.0
1/19
M48T02, M48T12
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. WRITE Enable Controlled, WRITE AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 8. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Checking the BOK Flag Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 11. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/19
M48T02, M48T12
SUMMARY DESCRIPTION
The M48T02/12 TIMEKEEPER ® RAM is a 2Kb x 8
non-volatile static RAM and real time clock which
is pin and functional compatible with the DS1642.
A special 24-pin, 600mil DIP CAPHAT™ package
houses the M48T02/12 silicon with a quartz crystal
and a long life lithium button cell to form a highly
integrated battery backed-up memory and real
time clock solution.
The M48T02/12 button cell has sufficient capacity
and storage life to maintain data and clock func-
tionality for an accumulated time period of at least
10 years in the absence of power over the operating temperature range.
The M48T02/12 is a non-volatile pin and function
equivalent to any JEDEC standard 2Kb x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
11
8
A0-A10
W
DQ0-DQ7
M48T02
M48T12
E
G
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
WRITE Enable
VCC
Supply Voltage
VSS
Ground
VSS
AI01027
Figure 3. DIP Connections
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
24
1
23
2
22
3
21
4
20
5
6
M48T02 19
M48T12 18
7
17
8
16
9
15
10
11
14
12
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01028
3/19
M48T02, M48T12
Figure 4. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A10
POWER
DQ0-DQ7
2040 x 8
SRAM ARRAY
LITHIUM
CELL
E
VPFD
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
W
BOK
VCC
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
G
VSS
AI01329
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 2. Absolute Maximum Ratings
Symbol
TA
TSTG
TSLD(2)
Parameter
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
VIO
Input or Output Voltages
–0.3 to 7
V
VCC
Supply Voltage
–0.3 to 7
V
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
4/19
M48T02, M48T12
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 3. Operating and AC Measurement Conditions
Parameter
M48T02
M48T12
Unit
4.75 to 5.5
4.5 to 5.5
V
0 to 70
0 to 70
°C
Load Capacitance (CL)
100
100
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 5. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL = 100pF
CL includes JIG capacitance
AI01019
Table 4. Capacitance
Parameter(1,2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input Capacitance
10
pF
Input / Output Capacitance
10
pF
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
5/19
M48T02, M48T12
Table 5. DC Characteristics
Symbol
Test Condition(1)
Parameter
Input Leakage Current
ILI
ILO(2)
ICC
Output Leakage Current
Supply Current
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
Outputs open
80
mA
E = VIH
3
mA
E = VCC – 0.2V
3
mA
ICC1(3)
Supply Current (Standby) TTL
ICC2(3)
Supply Current (Standby) CMOS
VIL(4)
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
Note: 1.
2.
3.
4.
2.4
V
Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
Outputs deselected.
Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.'
Negative spikes of –1V allowed for up to 10ns once per Cycle.
OPERATION MODES
As Figure 4, page 4 shows, the static memory array and the quartz controlled clock oscillator of the
M48T02/12 are integrated on one silicon chip. The
two circuits are interconnected at the upper eight
memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with
addresses 7F8h-7FFh. The clock locations contain the year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year - valid until 2100), 30, and 31 day
months are made automatically.
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ READ/WRITE memory
cells. The M48T02/12 includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T02/12 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of
data security in the midst of unpredictable system
operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
Table 6. Operating Modes
Mode
VCC
Deselect
WRITE
READ
4.75 to 5.5V
or
4.5 to 5.5V
READ
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD(min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 10, page 11 for details.
6/19
M48T02, M48T12
READ Mode
The M48T02/12 is in the READ Mode whenever W
(WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (tELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
Figure 6. READ Mode AC Waveforms
tAVAV
VALID
A0-A10
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01330
Note: WRITE Enable (W) = High.
Table 7. READ Mode AC Characteristics
M48T02/M48T12
Symbol
Parameter(1)
–70
Min
–150
Max
Min
–200
Max
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
70
150
200
ns
tELQV
Chip Enable Low to Output Valid
70
150
200
ns
tGLQV
Output Enable Low to Output Valid
35
75
80
ns
tELQX
Chip Enable Low to Output Transition
5
10
10
ns
tGLQX
Output Enable Low to Output Transition
5
5
5
ns
tEHQZ
Chip Enable High to Output Hi-Z
25
35
40
ns
tGHQZ
Output Enable High to Output Hi-Z
25
35
40
ns
tAXQX
Address Transition to Output Transition
70
10
150
5
200
ns
5
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
7/19
M48T02, M48T12
WRITE Mode
The M48T02/12 is in the WRITE Mode whenever
W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or
E. A WRITE is terminated by the earlier rising
edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from WRITE Enable prior to the initiation of anoth-
er READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for
tWHDX afterward. G should be kept high during
WRITE cycles to avoid bus contention; although, if
the output bus has been activated by a low on E
and G, a low on W will disable the outputs tWLQZ
after W falls.
Figure 7. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
VALID
A0-A10
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01331
Figure 8. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A10
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01332B
8/19
M48T02, M48T12
Table 8. WRITE Mode AC Characteristics
M48T02/M48T12
Symbol
(1)
–70
Parameter
Min
–150
Max
Min
Max
–200
Min
Unit
Max
tAVAV
WRITE Cycle Time
70
150
200
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
0
ns
tWLWH
WRITE Enable Pulse Width
50
90
120
ns
tELEH
Chip Enable Low to Chip Enable High
55
90
120
ns
tWHAX
WRITE Enable High to Address Transition
0
10
10
ns
tEHAX
Chip Enable High to Address Transition
0
10
10
ns
tDVWH
Input Valid to WRITE Enable High
30
40
60
ns
tDVEH
Input Valid to Chip Enable High
30
40
60
ns
tWHDX
WRITE Enable High to Input Transition
5
5
5
ns
tEHDX
Chip Enable High to Input Transition
5
5
5
ns
tWLQZ
WRITE Enable Low to Output Hi-Z
tAVWH
Address Valid to WRITE Enable High
60
120
140
ns
tAVEH
Address Valid to Chip Enable High
60
120
140
ns
tWHQX
WRITE Enable High to Output Transition
5
10
10
ns
25
50
60
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
9/19
M48T02, M48T12
Data Retention Mode
With valid VCC applied, the M48T02/12 operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high impedance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T02/12 may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
The power switching circuit connects external VCC
to the RAM and disconnects the battery when VCC
rises above VSO. As VCC rises, the battery voltage
is checked. If the voltage is too low, an internal
Battery Not OK (BOK) flag will be set. The BOK
flag can be checked after power up. If the BOK flag
is set, the first WRITE attempted will be blocked.
The flag is automatically cleared after the first
WRITE, and normal RAM operation resumes. Figure 9 illustrates how a BOK check routine could be
structured.
For more information on a Battery Storage Life refer to the Application Note AN1012.
Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK)
YES
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
AI00607
10/19
M48T02, M48T12
Figure 10. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tDR
tPD
INPUTS
tR
tFB
tRB
tREC
DON'T CARE
RECOGNIZED
NOTE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI00606
Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E high as VCC rises past VPFD (min). Some systems
may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a
power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running.
Table 9. Power Down/Up AC Characteristics
Symbol
Parameter(1)
tPD
E or W at VIH before Power Down
tF(2)
tFB(3)
Min
Max
Unit
0
µs
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
0
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
E or W at VIH before Power Up
2
ms
tREC
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Expected Data Retention Time
Min
Typ
Max
Unit
M48T02
4.5
4.6
4.75
V
M48T12
4.2
4.3
4.5
V
3.0
10
V
YEARS
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted).
3. At 25°C; VCC = 0V.
11/19
M48T02, M48T12
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, the seventh bit in the control register.
As long as a '1' remains in that position, updating
is halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and the time that
were current at the moment the halt command was
issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a '0.'
Setting the Clock
The eighth bit of the control register is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (on Table 11). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (7F9-7FF) to
the actual TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits
marked as '0' in Table 11 must be written to '0' to
allow for normal TIMEKEEPER and RAM operation.
See the Application Note AN923, “TIMEKEEPER ®
Rolling Into the 21st Century” for information on
Century Rollover.
Table 11. Register Map
Data
Address
D7
7FF
D6
D5
D4
D3
D2
10 Years
10 M
D0
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Day
01-07
Hours
Hours
00-23
7FE
0
0
7FD
0
0
7FC
0
FT
7FB
0
0
7FA
0
10 Minutes
Minutes
Minutes
00-59
7F9
ST
10 Seconds
Seconds
Seconds
00-59
7F8
W
R
0
D1
Function/Range
BCD Format
10 Date
0
0
0
Day
10 Hours
S
Calibration
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
12/19
Control
M48T02, M48T12
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T02/12 is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T02/12
oscillator starts within one second.
Calibrating the Clock
The M48T02/12 is driven by a quartz-controlled
oscillator with a nominal frequency of 32,768 Hz.
A typical M48T02/12 is accurate within 1 minute
per month at 25°C without calibration. The devices
are tested not to exceed ± 35 PPM (parts per million) oscillator frequency error at 25°C, which
equates to about ±1.53 minutes per month.
The oscillation rate of any crystal changes with
temperature. Figure 11, page 14 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for
crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T02/12
design, however, employs periodic counter correction. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12, page 14.
The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five-bit Calibration Byte found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order
bits in the Control register. This byte can be set to
represent any value between 0 and 31 in binary
form. The sixth bit is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The
first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles; that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration Byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T02/12 may require.
The first involves simply setting the clock, letting it
run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that
may seem crude, it allows the designer to give the
end user the ability to calibrate his clock as his environment may require, even after the final product
is packaged in a non-user serviceable enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) Bit, the seventh-most significant bit in the Day
Register, is set to a '1,' and the oscillator is running
at 32,768 Hz, the LSB (DQ0) of the Seconds Register will toggle at 512 Hz. Any deviation from 512
Hz indicates the degree and direction of oscillator
frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a
+20 PPM oscillator frequency error, requiring a –
10 (WR001010) to be loaded into the Calibration
Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output frequency. The device must be selected and addresses must be stable at Address 7F9 when
reading the 512 Hz on DQ0.
The FT Bit must be set using the same method
used to set the clock: using the WRITE Bit. The
LSB of the Seconds Register is monitored by holding the M48T02/12 in an extended READ of the
Seconds Register, but without having the READ
Bit set. The FT Bit MUST be reset to '0' for normal
clock operations to resume.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the Frequency Test Bit
(FT) or the Stop Bit (ST).
For more information on calibration, see the Application Note AN924, “TIMEKEEPER ® Calibration.”
13/19
M48T02, M48T12
Figure 11. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
-60
T0 = 25 °C
-80
-100
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
°C
AI02124
Figure 12. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
14/19
M48T02, M48T12
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 13. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
15/19
M48T02, M48T12
PACKAGE MECHANICAL INFORMATION
Figure 14. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Outline
A2
A1
B1
B
A
L
C
e1
eA
e3
D
N
E
1
PCDIP
Note: Drawing is not to scale.
Table 12. PCDIP24 – 24-pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
16/19
Min
Max
A
8.89
A1
Typ
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
34.29
34.80
1.350
1.370
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
25.15
30.73
0.990
1.210
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
24
24
M48T02, M48T12
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M48T
02
–70
PC
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
02 = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V
12 = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed
–70 = 100ns (M48T02/12)
–150 = 150ns (M48T02/12)
–200 = 200ns (M48T02/12)
Package
PC = PCDIP24
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest you.
17/19
M48T02, M48T12
REVISION HISTORY
Table 14. Document Revision History
Date
Rev. #
July 2000
1.0
First issue
13-Jul-00
1.1
tREC change (Table 9)
07-May-01
2.0
Reformatted; temp. / voltage info. added to tables (Tables 4, 5, 7, 8, 9, 10)
14-May-01
2.1
Note added to Clock Calibration section; table footnote correction (Table 6)
16-Jul-01
2.2
Basic formatting / content changes (Figure 1, Tables 4, 5, 10)
20-May-02
2.3
Add countries to disclaimer
26-Jun-02
2.4
Add footnote to table (Table 10)
28-Mar-03
3.0
v2.2 template applied; test conditions updated (Table 9)
18/19
Revision Details
M48T02, M48T12
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
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19/19