STMICROELECTRONICS M54HC374

M54HC374
RAD-HARD OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUT NON INVERTING
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HIGH SPEED:
fMAX = 90MHz (TYP.) at VCC = 6V
LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
HIGH NOISE IMMUNITY:
VNIH = VNIL = 28% VCC (MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 6mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 374
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9203-060
DESCRIPTION
The M54HC374 is an high speed CMOS OCTAL
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate C2MOS technology.
This 8 bit D-TYPE FLIP FLOP is controlled by a
clock input (CK) and an output enable input (OE).
DILC-20
FPC-20
ORDER CODES
PACKAGE
FM
EM
DILC
FPC
M54HC374D
M54HC374K
M54HC374D1
M54HC374K1
On the positive transition of the clock, the Q
outputs will be set to the logic state that were
setup at the D inputs.
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while OE is high the outputs will be in a
high impedance state.
The output control does not affect the internal
operation of flip-flops; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
May 2004
Rev. 1
1/11
M54HC374
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
SYMBOL
1
OE
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
11
Q0 to Q7
3 State Output Enable
Input (Active LOW)
3 State Outputs
D0 to D7
Data Inputs
10
20
GND
VCC
CK
NAME AND FUNCTION
Clock Input (LOW to
HIGH, edge triggered)
Ground (0V)
Positive Supply Voltage
Table 2: Truth Table
INPUTS
OE
CK
D
Q
H
X
X
Z
L
X
NO CHANGE
L
L
L
L
H
H
X: Don’t Care
Z: High Impedance
2/11
OUTPUT
M54HC374
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
Table 3: Absolute Maximum Ratings
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
-0.5 to +7
V
VI
DC Input Voltage
-0.5 to VCC + 0.5
V
VO
DC Output Voltage
IIK
DC Input Diode Current
-0.5 to VCC + 0.5
± 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
± 35
mA
ICC or IGND DC VCC or Ground Current
PD
Power Dissipation
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
V
± 70
mA
420
mW
-65 to +150
°C
265
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 4: Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
2 to 6
V
VI
Input Voltage
0 to VCC
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
Input Rise and Fall Time
tr, tf
-55 to 125
°C
VCC = 2.0V
0 to 1000
ns
VCC = 4.5V
0 to 500
ns
VCC = 6.0V
0 to 400
ns
3/11
M54HC374
Table 5: DC Specifications
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
IOZ
ICC
4/11
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
Value
TA = 25°C
VCC
(V)
Min.
2.0
4.5
6.0
2.0
4.5
6.0
Typ.
Max.
1.5
3.15
4.2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
3.15
4.2
0.5
1.35
1.8
Max.
1.5
3.15
4.2
0.5
1.35
1.8
Unit
V
0.5
1.35
1.8
2.0
IO=-20 µA
1.9
2.0
1.9
1.9
4.5
IO=-20 µA
4.4
4.5
4.4
4.4
6.0
IO=-20 µA
5.9
6.0
5.9
5.9
4.5
IO=-6.0 mA
4.18
4.31
4.13
4.10
6.0
IO=-7.8 mA
5.68
5.8
5.63
5.60
2.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=20 µA
0.0
0.1
0.1
0.1
V
V
6.0
IO=20 µA
0.0
0.1
0.1
0.1
4.5
IO=6.0 mA
0.17
0.26
0.33
0.40
6.0
IO=7.8 mA
0.18
0.26
0.33
0.40
6.0
VI = VCC or GND
± 0.1
±1
±1
µA
6.0
VI = VIH or VIL
VO = VCC or GND
± 0.5
±5
± 10
µA
6.0
VI = VCC or GND
4
40
80
µA
V
M54HC374
Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Symbol
Parameter
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
Time
(CLOCK - Q)
tPZL tPZH High Impedance
Output Enable
Time
tPLZ tPHZ High Impedance
Output Disable
Time
fMAX
Maximum Clock
Frequency
tW(L)
tW(H)
Minimum Pulse
Width (CLOCK)
ts
Minimum Set-up
Time
th
Minimum Hold
Time
VCC
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Value
TA = 25°C
CL
(pF)
Min.
50
50
150
50
RL = 1 KΩ
150
RL = 1 KΩ
50
RL = 1 KΩ
50
6.2
31
37
50
50
Typ.
Max.
25
7
6
45
15
13
60
20
17
39
13
11
54
18
15
30
14
13
18
75
90
15
6
6
25
6
4
60
12
10
140
28
24
190
38
32
135
27
23
185
37
31
125
25
21
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
75
15
13
175
35
30
240
48
41
170
34
29
230
46
39
155
31
26
5
25
30
75
15
13
75
15
13
0
0
0
50
Max.
90
18
15
210
42
36
285
57
48
205
41
35
280
56
48
190
38
32
4.2
21
25
95
19
16
95
19
16
0
0
0
Unit
ns
ns
ns
ns
ns
ns
MHz
110
22
19
110
22
19
0
0
0
ns
ns
ns
Table 7: Capacitive Characteristics
Test Condition
Symbol
Parameter
CIN
Input Capacitance
COUT
Output
Capacitance
Power Dissipation
Capacitance (note
1)
CPD
VCC
(V)
Value
TA = 25°C
Min.
Typ.
Max.
5
10
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
10
Unit
Max.
10
pF
10
pF
47
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip
Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 30 + 17 x n (pF)
5/11
M54HC374
Figure 4: Test Circuit
TEST
tPLH, tPHL
SWITCH
Open
tPZL, tPLZ
VCC
tPZH, tPHZ
GND
CL = 50pF/150pF or equivalent (includes jig and probe capacitance)
R1 = 1KΩ or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 5: Waveform - CK To Qn Propagation Delays, CK Fmax, Dn To CK Setup And Hold Times
(f=1MHz; 50% duty cycle)
6/11
M54HC374
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Minimum Pulse Width (CK) (f=1MHz; 50% duty cycle)
7/11
M54HC374
DILC-20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
2.1
2.71
0.083
0.107
a1
3.00
3.70
0.118
0.146
a2
0.63
0.88
1.14
0.025
0.035
0.045
B
1.93
2.03
2.23
0.076
0.080
0.088
b
0.40
0.45
0.50
0.016
0.018
0.020
b1
0.20
0.254
0.30
0.008
0.010
0.012
D
25.14
25.40
25.65
0.990
1.000
1.010
e
7.36
7.62
7.87
0.290
0.300
0.310
e1
2.54
0.100
e2
22.73
22.86
22.99
0.895
0.900
0.905
e3
7.62
7.87
8.12
0.300
0.310
0.320
F
7.29
7.49
7.70
0.287
0.295
0.303
I
3.86
K
11.30
L
1.14
1.27
0.152
11.56
0.445
1.40
0.045
0.455
0.050
0.055
0016178J
8/11
M54HC374
FPC-20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
A
9.98
10.16
10.34
0.393
0.400
0.407
B
9.98
10.16
10.34
0.393
0.400
0.407
C
1.45
1.61
1.78
0.57
0.63
0.070
D
0.10
0.127
0.18
0.004
0.005
0.007
E
11.30
11.43
11.56
0.445
0.450
0.455
F
1.27
G
0.38
H
0.48
0.015
7.24
8.16
0.285
0.320
L
24.46
26.67
0.960
1.050
M
0.45
0.55
0.018
N
0.43
0.050
0.50
7.87
0.017
0.020
0.019
0.022
0.310
O
1.14
1.27
1.40
0.045
0.050
0.055
P
0.10
0.18
0.25
0.004
0.007
0.010
016032F
9/11
M54HC374
Table 8: Revision History
Date
Revision
10-May-2004
1
10/11
Description of Changes
First Release
M54HC374
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11/11