ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 QUAD DIGITAL ISOLATORS FEATURES 1 • • • • • • 1, 25, and 150-Mbps Signaling Rate Options – Low Channel-to-Channel Output Skew; 1 ns Max – Low Pulse-Width Distortion (PWD); 2 ns Max – Low Jitter Content; 1 ns Typ at 150 Mbps Typical 25-Year Life at Rated Working Voltage (see application note SLLA197 and Figure 14) 4000-Vpeak Isolation, 560-Vpeak Working Voltage UL 1577 Certified 4 kV ESD Protection Operate With 3.3-V or 5-V Supplies • • High Electromagnetic Immunity (see application report SLLA181) –40°C to 125°C Operating Range APPLICATIONS • • • • Industrial Fieldbus Computer Peripheral Interface Servo Control Interface Data Acquisition DESCRIPTION The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations with output enable function. These devices have logic input and output buffers separated by TI’s silicon dioxide (SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same direction and one channel in opposition. The ISO7242 has two channels in each direction. The A and C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter or the additional propagation delay. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option). These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V / 3.3-V, 5-V / 5-V, 5-V / 3.3-V, or 3.3-V / 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used. These devices are characterized for operation over the ambient temperature range of –40°C to 125°C. ISO7240 VCC1 GND1 INA INB INC IND NC GND1 1 2 3 4 5 6 7 8 ISO7241 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB OUTC OUTD EN GND2 VCC1 GND1 INA INB INC OUTD EN1 GND1 1 2 3 4 5 6 7 8 ISO7242 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB OUTC IND EN2 GND2 VCC1 GND1 INA INB OUTC OUTD EN1 GND1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 GND2 OUTA OUTB INC IND EN2 GND2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel Filter OSC + PWM Pulse Width Demodulation Vref Carrier Detect EN IN Input + Filter Data MUX AC Detect Vref OUT Output Buffer AC Channel Table 1. Device Function Table ISO724x VCC1 PU (1) 2 VCC2 PU (1) INPUT (IN) OUTPUT ENABLE (EN) OUTPUT (OUT) H H or Open H L H or Open L X L Z Open H or Open H PD PU X H or Open H PD PU X L Z PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 AVAILABLE OPTIONS PRODUCT SIGNALING RATE INPUT THRESHOLD ISO7240ADW 1 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7240CDW 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7240MDW 150 Mbps Vcc/2 (CMOS) ISO7240M ISO7241ADW (1) 1 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7241A ISO7241CDW (1) 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7241MDW (1) 150 Mbps Vcc/2 (CMOS) ISO7241M ISO7242ADW (1) 1 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7242A ISO7242CDW (1) 25 Mbps ~1.5 V (TTL) (CMOS compatible) ISO7242MDW (1) 150 Mbps Vcc/2 (CMOS) (1) CHANNEL CONFIGURATION MARKED AS ISO7240A 4/0 3/1 2/2 ISO7240C ISO7241C ISO7242C ISO7242M ORDERING NUMBER ISO7240ADW (rail) ISO7240ADWR (reel) ISO7240CDW (rail) ISO7240CDWR (reel) ISO7240MDW (rail) ISO7240MDWR (reel) ISO7241ADW (rail) ISO7241ADWR (reel) ISO7241CDW (rail) ISO7241CDWR (reel) ISO7241MDW (rail) ISO7241MDWR (reel) ISO7242ADW (rail) ISO7242ADWR (reel) ISO7242CDW (rail) ISO7242CDWR (reel) ISO7242MDW (rail) ISO7242MDWR (reel) Product Preview Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 3 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 ABSOLUTE MAXIMUM RATINGS (1) (2) VCC Supply voltage VI Voltage at IN, OUT, EN , VCC1, VCC2 IO Output current ESD Electrostatic Field-Induced-Charged Device discharge Model TJ Maximum junction temperature Human Body Model JEDEC Standard 22, Test Method A114-C.01 Machine Model (1) (2) JEDEC Standard 22, Test Method C101 VALUE UNIT –0.5 to 6 V –0.5 to 6 V ±15 mA ±4 All pins kV ±1 ANSI/ESDS5.2-1996 ±200 V 170 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage, VCC1, VCC2 IOH High-level output current IOL Low-level output current tui 1/tui 4.5 5.5 3 3.6 Input pulse width Signaling rate UNIT V mA –4 mA ISO724xA 1 μs ISO724xC 40 ISO724xM 6.67 ISO724xA 0 250 1000 ISO724xC 0 30 (1) 25 ISO724xM 0 200 (1) 150 High-level input voltage (IN) VIL Low-level input voltage (IN) VIH High-level input voltage (IN) (EN on all devices) VIL Low-level input voltage (IN) (EN on all devices) TJ Junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 & IEC 61000-4-9 certification 4 MAX 4 VIH (1) TYP ISO724xM ISO724xA, ISO724xC ns 5 kbps Mbps 0.7 VCC VCC V 0 0.3 VCC V 2 VCC V 0 0.8 V 150 °C 1000 A/m Typical value at room temperature and well-regulated power supply. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1 3 UNIT SUPPLY CURRENT ISO7240A/C/M ICC1 ICC2 Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 3 7 10.5 mA TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD VI = VCC or 0 V, All channels, no load, EN2 at 3 V 15 22 16 22 17 mA 25 TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at VCC, Single channel VCC – 0.4 IOH = –20 μA, See Figure 1 VCC – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 μA 0 IOH = –4 mA, See Figure 1 V IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 150 IN from 0 V to VCC mV 10 –10 25 Product Folder Link(s): ISO7240 ISO7241 ISO7242 μA 1 pF 50 kV/μs Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated V 5 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 SWITCHING CHARACTERISTICS VCC1 and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay (1) MAX 10 18 See Figure 1 42 ISO724xM 22 tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 Peak-to-peak eye-pattern jitter 150 Mbps NRZ data input, Same polarity input on all channels, See Figure 5 (1) (2) (3) 6 1 ISO724xA/C ISO724xM (3) 2 ns 9 ns 2 ns 0 ISO724xA/C ISO724xM 0 1 2 See Figure 1 ISO724xM ns 2.5 10 Pulse-width distortion (2) UNIT 80 PWD tjit(pp) |tPHL – tPLH| TYP 40 ISO724xA ISO724xC MIN ns 2 See Figure 2 ns 12 μs 1 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1 3 UNIT SUPPLY CURRENT ICC1 ICC2 ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps VI = VCC or 0 V, All channels, no load, EN2 at 3 V 1 3 7 10.5 mA TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD VI = VCC or 0 V, All channels, no load, EN2 at 3 V 9.5 15 10 15 10.5 mA 17 TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD ELECTRICAL CHARACTERISTICS IOFF VOH Sleep mode output current High-level output voltage EN at VCC, Single channel IOH = –4 mA, See Figure 1 μA 0 ISO7240 VCC – 0.4 ISO724x (5-V side) VCC – 0.8 IOH = –20 μA, See Figure 1 V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 150 IN from 0 V to VCC mV 10 –10 IN at VCC, VI = 0.4 sin (4E6πt) 25 Product Folder Link(s): ISO7240 ISO7241 ISO7242 μA 1 pF 50 kV/μs Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated V 7 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 SWITCHING CHARACTERISTICS VCC1 at 5-V, VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 40 80 tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion(1) |tPHL – tPLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data input, Same polarity input on all channels, See Figure 5 tjit(pp) (1) (2) (3) 8 ISO724xA ISO724xC 11 See Figure 1 20 46 12 28 1 ISO724xA/C ISO724xM (3) 2 ns 7.5 ns 2.5 ns 0 ISO724xA/C ISO724xM 0 1 2 See Figure 1 ISO724xM ns 3 ISO724xM (2) UNIT ns 2 See Figure 2 ns 18 μs 1 ns Also known as pulse skew tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS VCC1 at 3.3-V, VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.5 1 1 2 3 5 UNIT SUPPLY CURRENT ICC1 ICC2 ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps VI = VCC or 0 V, All channels, no load, EN2 at 3 V mA TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD VI = VCC or 0 V, All channels, no load, EN2 at 3 V 15 22 16 22 17 mA 25 TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD TBD VI = VCC or 0 V, All channels, no load, EN1 at 3 V, EN2 at 3 V TBD mA TBD ELECTRICAL CHARACTERISTICS IOFF VOH Sleep mode output current High-level output voltage EN at VCC, Single channel IOH = –4 mA, See Figure 1 μA 0 ISO7240 VCC – 0.4 ISO724x (5-V side) VCC – 0.8 IOH = –20 μA, See Figure 1 V VCC – 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 150 IN from 0 V to VCC mV 10 –10 25 Product Folder Link(s): ISO7240 ISO7241 ISO7242 μA 1 pF 50 kV/μs Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated V 9 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 SWITCHING CHARACTERISTICS VCC1 at 3.3-V and VCC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion (1) |tPHL – tPLH| tPLH, tPHL Propagation delay PWD Pulse-width distortion(1) |tPHL – tPLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output tPZH Propagation delay, high-impedance-to-high-level output tPLZ Propagation delay, low-level-to-high-impedance output tPZL Propagation delay, high-impedance-to-low-level output tfs Failsafe output delay time from input power loss See Figure 3 Peak-to-peak eye-pattern jitter 150 Mbps NRZ data input, Same polarity input on all channels, See Figure 5 tjit(pp) (1) (2) (3) 10 TYP 40 ISO724xA ISO724xC MIN 11 22 51 12 26 See Figure 1 ISO724xM 1 2 10 0 ISO724xA/C 2.5 ISO724xM 0 1 2 See Figure 1 ISO724xM ns 3 ISO724xM (3) UNIT 80 ISO724xA/C (2) MAX ns ns ns 2 See Figure 2 ns 15 20 15 20 15 20 15 20 ns 12 μs 1 ns Also known as pulse skew tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.5 1 1 2 3 5 UNIT SUPPLY CURRENT ICC1 ICC2 ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps TBD ISO7242A/C/M Quiescent TBD ISO7242A 1 Mbps ISO7242C/M 25 Mbps ISO7240A/C/M Quiescent ISO7240A 1 Mbps ISO7240C/M 25 Mbps ISO7241A/C/M Quiescent ISO7241A 1 Mbps ISO7241C/M 25 Mbps ISO7242A/C/M Quiescent ISO7242A 1 Mbps ISO7242C/M 25 Mbps VI = VCC or 0 V, all channels, no load, EN2 at 3 V mA TBD VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V TBD VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V mA TBD TBD VI = VCC or 0 V, all channels, no load, EN2 at 3 V 9.5 15 10 15 10.5 17 mA TBD VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V TBD TBD TBD VI = VCC or 0 V, all channels, no load, EN1 at 3 V, EN2 at 3 V mA TBD TBD ELECTRICAL CHARACTERISTICS IOFF Sleep mode output current EN at VCC, single channel VCC – 0.4 IOH = –20 μA, See Figure 1 VCC – 0.1 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 4 μA 0 IOH = –4 mA, See Figure 1 V IOL = 4 mA, See Figure 1 0.4 IOL = 20 μA, See Figure 1 0.1 150 IN from 0 V or VCC mV 10 –10 25 Product Folder Link(s): ISO7240 ISO7241 ISO7242 μA 1 pF 50 kV/μs Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated V 11 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tPLH, tPHL Propagation delay PWD Pulse-width distortion |tPHL – tPLH| (1) tsk(pp) Part-to-part skew (2) tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tPHZ Propagation delay, high-level-to-high-impedance output 15 20 tPZH Propagation delay, high-impedance-to-high-level output 15 20 tPLZ Propagation delay, low-level-to-high-impedance output 15 20 tPZL Propagation delay, high-impedance-to-low-level output 15 20 tfs Failsafe output delay time from input power loss See Figure 3 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data input, same polarity input on all channels, See Figure 5 tjit(pp) (1) (2) (3) 12 45 MAX tPLH, tPHL ISO724xA ISO724xC 12 See Figure 1 25 56 12 32 ISO724xM 1 2 9 ISO724xM 0 ISO724xA/C 3 ISO724xM 0 1 ns ns ns 2 See Figure 1 ISO724xM ns 4 ISO724xA/C (3) UNIT 85 2 See Figure 2 ns 18 μs 1 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms Vcc Vcc ISOLATION BARRIER 0V RL = 1 kW ±1% IN Input Generator VI OUT EN Vcc/2 VI t PZL VO VO CL Vcc/2 0V t PLZ Vcc 0.5 V 50% NOTE B 50 W VOL 3V ISOLATION BARRIER NOTE A IN Input Generator VI Vcc OUT VO Vcc/2 VI Vcc/2 0V EN 50 W t PZH CL NOTE B RL = 1 kW ±1% VO VOH 50% 0.5 V t PHZ 0V NOTE A A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 13 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) VI 0V or VCC1 ISOLATION BARRIER VCC1 IN VCC1 VI OUT 2.7 V VO 0V VOH tfs CL NOTE B VO 50% VOL A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 ISOLATION BARRIER C = 0.1 mF± 1% IN S1 GND1 C = 0.1 mF± 1% OUT NOTE B Pass-fail criteria: Output must remain stable VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform VCC1 DUT Tektronix HFS9009 IN OUT 0V Tektronix 784D PATTERN GENERATOR VCC/2 Jitter NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s or 0s. Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 DEVICE INFORMATION PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 7.7 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface 8.1 mm 0.008 mm Minimum Internal Gap (Internal Clearance) Distance through the insulation RIO Isolation resistance Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device CIO Barrier capacitance Input to output CI Input capacitance to ground >1012 Ω VI = 0.4 sin (4E6πt) 1 pF VI = 0.4 sin (4E6πt) 1 pF DEVICE I/O SCHEMATICS Enable VCC Output Input VCC VCC VCC VCC VCC 1 MW 500 W EN IN 8W 500 W OUT 13 W 1 MW Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 15 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 REGULATORY INFORMATION UL Recognized under 1577 Component Recognition Program (1) File Number: E181974 (1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577. THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Low-K Thermal Resistance θJA Junction-to-air θJB Junction-to-Board Thermal Resistance θJC Junction-to-Case Thermal Resistance PD (1) MIN TYP MAX (1) 168 High-K Thermal Resistance °C/W 96.1 61 °C/W 48 °C/W VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 50% duty cycle square wave Device Power Dissipation UNIT 220 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. TYPICAL CHARACTERISTIC CURVES 3.3-V RMS SUPPLY CURRENT vs SIGNALING RATE 5-V RMS SUPPLY CURRENT vs SIGNALING RATE 45 35 VCC1 = 3.3 V, VCC2 = 3.3 V, TA = 25°C, Load = 15 pF, All Channels 25 ICC - Supply Current - mA/RMS ICC - Supply Current - mA/RMS 30 40 ICC2 20 15 10 ICC1 5 35 VCC1 = 5 V, VCC2 = 5 V, TA = 25°C, Load = 15 pF, All Channels 30 ICC2 25 20 ICC1 15 10 5 0 0 25 50 75 100 Signaling Rate - Mbps 125 150 0 0 25 Figure 6. 16 50 75 100 125 150 Signaling Rate - Mbps Figure 7. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 TYPICAL CHARACTERISTIC CURVES (continued) PROPAGATION DELAY vs FREE-AIR TEMPERATURE INPUT VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE 1.4 45 tPLH 40 3.3 V tPHL Input Voltage Threshold - V Propagation Delay - ns 35 5V 30 tPLH 25 tPHL 20 15 10 Load = 15 pF, Air Flow at 7 cf/m, Low-K Board 5 -25 -10 5 80 65 35 20 50 TA - Free-Air Temperature - °C 95 110 125 1.2 Air Flow at 7 cf/m, Low_K Board 1.15 5 V Vth1.1 3.3 V Vth-25 -10 5 20 35 50 65 80 TA - Free-Air Temperature - °C 95 Figure 8. Figure 9. VCC1 FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 110 125 50 VCC at 5 V or 3.3 V, Load = 15 pF, Air Flow at 7/cf/m, Low-K Board VCC = 5 V Load = 15 pF, TA = 25°C 40 2.7 IO - Output Current - mA VCC1 - Failsafe Threshold - V 2.8 3.3 V Vth+ 1.25 1 -40 3 2.9 1.3 1.05 0 -40 5 V Vth+ 1.35 Vfs+ 2.6 2.5 Vfs- 2.4 2.3 2.2 VCC = 3.3 V 30 20 10 2.1 2 -40 -25 -10 5 20 35 50 65 80 95 110 125 0 0 TA - Free-Air Temperature - °C Figure 10. 2 4 VO - Output Voltage - V 6 Figure 11. Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 17 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 TYPICAL CHARACTERISTIC CURVES (continued) LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 Load = 15 pF, TA = 25°C 45 IO - Output Current - mA 40 35 VCC = 3.3 V 30 25 VCC = 5 V 20 15 10 5 0 0 1 2 3 VO - Output Voltage - V 4 5 Figure 12. 18 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 ISO7240 ISO7241 ISO7242 www.ti.com SLLS868 – SEPTEMBER 2007 APPLICATION INFORMATION VCC1 20 mm Max From 20 mm Max From VCC1 VCC2 VCC2 0.1 mF 0.1 mF 1 16 2 15 IN A 3 14 OUTA IN B 4 13 OUTB IN C 5 12 OUTC IN D 6 11 OUTD 7 10 8 9 GND1 NC GND1 ISO7240x GND2 EN GND2 Figure 13. Typical ISO724x Application Circuit LIFE EXPECTANCY vs. WORKING VOLTAGE WORKING LIFE -- YEARS 100 VIORM at 560-V 28 Years 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (VIORM) -- V Figure 14. Time-Dependant Dielectric Breakdown Testing Results Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242 19 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7240ADWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7240CDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7240MDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) Height (mm) ISO7240ADWR DW 16 SITE 35 406.0 348.0 63.0 ISO7240CDWR DW 16 SITE 35 406.0 348.0 63.0 ISO7240MDWR DW 16 SITE 35 406.0 348.0 63.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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