TI TPS78001DDCR

TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
150mA, Low-Dropout Regulator, Ultralow-Power, IQ 500nA
with Pin-Selectable, Dual-Level Output Voltage
FEATURES
1
• Low IQ: 500nA
• 150mA, Low-Dropout Regulator with
Pin-Selectable Dual Voltage Level Output
• Low Dropout: 200mV at 150mA
• 3% Accuracy Over Load/Line/Temperature
• Available in Dual-Level, Fixed Output Voltages
from 1.5V to 4.2V Using Innovative Factory
EPROM Programming
• Available in an Adjustable Version from 1.22V
to 5.25V or a Dual-Level Output Version
• VSET Pin Toggles Output Voltage Between Two
Factory-Programmed Voltage Levels
• Stable with a 1.0µF Ceramic Capacitor
• Thermal Shutdown and Overcurrent Protection
• CMOS Logic Level-Compatible Enable Pin
• Available in DDC (TSOT23-5) or DRV (2mm ×
2mm SON-6) Package Options
2
APPLICATIONS
•
•
•
•
TI MSP430 Attach Applications
Power Rails with Programming Mode
Dual Voltage Levels for Power-Saving Mode
Wireless Handsets, Smartphones, PDAs, MP3
Players, and Other Battery-Operated Handheld
Products
DESCRIPTION
The TPS780 family of low-dropout (LDO) regulators
offer the benefits of ultralow power (IQ = 500nA),
miniaturized packaging (2×2 SON-6), and selectable
dual-level output voltage levels. An adjustable version
is also available, but does not have the capability to
shift voltage levels.
TPS780DDC
TSOT23-5
(TOP VIEW)
IN
GND
EN
1
5
The VSET pin allows the end user to switch between
two
voltage
levels
on-the-fly
through
a
microprocessor-compatible input. This LDO is
designed specifically for battery-powered applications
where dual-level voltages are needed. With ultralow
IQ (500nA), microprocessors, memory cards, and
smoke detectors are ideal applications for this device.
The ultralow-power and selectable dual-level output
voltages allow designers to customize power
consumption for specific applications. Designers can
now shift to a lower voltage level in a battery-powered
design when the microprocessor is in sleep mode,
further reducing overall system power consumption.
The two voltage levels are preset at the factory
through a unique architecture using an EPROM. The
EPROM technique allows for numerous output
voltage options between VSET low (1.5V to 4.2V) and
VSET high (2.0V to 3.0V) in the fixed output version
only. Consult with your local factory representative for
exact voltage options and ordering information;
minimum order quantities may apply.
The TPS780 series are designed to be compatible
with the TI MSP430 and other similar products. The
enable pin is compatible with standard CMOS logic.
This LDO is stable with any output capacitor greater
than 1.0µF. Therefore, implementations of this device
require minimal board space because of miniaturized
packaging and a potentially small output capacitor.
The TPS780 series IQ (500nA) also come with
thermal shutdown and current limit to protect the
device during fault conditions. All packages have an
operating temperature range of TJ = –40°C to
+125°C. For more cost-sensitive applications
requiring a dual-level voltage option and only on par
IQ, consider the TPS781 series, with an IQ of 1.0µA
and dynamic voltage scaling.
TPS780DRV
2mm x 2mm SON-6
(TOP VIEW)
OUT
OUT
1
2
N/C
2
3
VSET/FB
3
4
VSET/FB
Thermal
Pad
6
IN
5
GND
4
EN
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
SBVS083C – JANUARY 2007 – REVISED MAY 2008 ....................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1) (2)
PRODUCT
VOUT
TPS780vvvxxxyyyz
(1)
(2)
(3)
(4)
VVV is the nominal output voltage for VOUT(HIGH) and corresponds to VSET pin low.
XXX is the nominal output voltage for VOUT(LOW) and corresponds to VSET pin high.
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
Adjustable version (3) (4)
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Additional output voltage combinations are available on a quick-turn basis using innovative, factory EPROM programming.
Minimum-order quantities apply; contact your sales representative for details and availability.
To order the adjustable version, use TPS78001YYYZ.
The device is either fixed voltage, dual-level VOUT, or adjustable voltage only. Device design does not permit a fixed and adjustable
output simultaneously.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
PARAMETER
TPS780 Series
UNIT
–0.3 to +6.0
V
Enable and VSET voltage range, VEN and VVSET
–0.3 to VIN + 0.3 (2)
V
Output voltage range, VOUT
–0.3 to VIN + 0.3V
V
Input voltage range, VIN
Maximum output current, IOUT
Internally limited
Output short-circuit duration
Indefinite
Total continuous power dissipation, PDISS
ESD rating
See the Dissipation Ratings table
Human body model (HBM)
2
kV
500
V
Operating junction temperature range, TJ
–40 to +125
°C
Storage temperature range, TSTG
–55 to +150
°C
(1)
(2)
Charged device model (CDM)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
VEN and VVSET absolute maximum rating are VIN + 0.3V or +6.0V, whichever is less.
DISSIPATION RATINGS
BOARD
DERATING FACTOR
ABOVE TA = +25°C
TA < +25°C
TA = +70°C
TA = +85°C
20°C/W
65°C/W
15.4mW/°C
1540mW
845mW
615mW
90°C/W
200°C/W
5.0mW/°C
500mW
275mW
200mW
RθJC
(1)
DRV
High-K (1)
DDC
High-K
(1)
2
RθJA
PACKAGE
The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
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TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5V or 2.2V, whichever is greater; IOUT =
100µA, VVSET = VEN = VIN, COUT = 1.0µF, fixed or adjustable, unless otherwise noted. Typical values at TJ = +25°C.
TPS780 Series
PARAMETER
VIN
TEST CONDITIONS
Input voltage range
DC output accuracy
TYP
2.2
Nominal
VOUT (1)
MIN
TJ = +25°C, VSET = high/low
Over VIN, IOUT, VOUT + 0.5V ≤ VIN ≤ 5.5V,
temperature
0mA ≤ IOUT ≤ 150mA, VSET = high/low
MAX
UNIT
5.5
V
–2
±1
+2
%
–3.0
±2.0
+3.0
%
VFB
Internal reference (2)
(adjustable version only)
TJ = +25°C, VIN = 4.0V, IOUT = 75mA
VOUT_RANGE
Output voltage range (3) (4)
(adjustable version only)
VIN = 5.5V, IOUT = 100µA (2)
ΔVOUT/ΔVIN
Line regulation
VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V, IOUT = 5mA
–1
ΔVOUT/ΔIOUT
–2
VFB
1.216
V
5.25
V
+1
%
Load regulation
0mA ≤ IOUT ≤ 150mA
VDO
Dropout voltage (5)
VIN = 95% VOUT(NOM), IOUT = 150mA
VN
Output noise voltage
BW = 100Hz to 100kHz, VIN = 2.2V,
VOUT = 1.2V, IOUT = 1mA
VHI
VSET high (output VOUT(LOW)
selected), or EN high (enabled)
1.2
VIN
V
VLO
VSET low (output VOUT(HIGH)
selected), or EN low (disabled)
0
0.4
V
ICL
Output current limit
IGND
Ground pin current
%
mV
µVRMS
86
VOUT = 0.90 × VOUT(NOM)
230
400
mA
IOUT = 0mA (6)
420
800
nA
IOUT = 150mA
5
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4V, 2.2V ≤ VIN < 5.5V,
TJ = –40°C to +100°C
IVSET
VSET pin current
IEN
IFB
PSRR
+2
250
150
18
µA
130
nA
VEN = VVSET = 5.5V
70
nA
EN pin current
VEN = VVSET = 5.5V
40
nA
FB pin current (7)
(adjustable version only)
VIN = 5.5V, VOUT = 1.2V, IOUT = 100µA
10
nA
Power-supply rejection ratio
VIN = 4.3V,
VOUT = 3.3V,
IOUT = 150mA
f = 10Hz
40
dB
f = 100Hz
20
dB
f = 1kHz
15
dB
tTR(H→L)
VOUT transition time (high-to-low)
VOUT = 97% × VOUT(HIGH)
VOUT_LOW = 2.2V, VOUT(HIGH) = 3.3V,
IOUT = 10mA
800
µs
tTR(L→H)
VOUT transition time (low-to-high)
VOUT = 97% × VOUT(LOW)
VOUT_HIGH = 3.3V, VOUT(LOW) = 2.2V,
IOUT = 10mA
800
µs
Startup time (8)
COUT = 1.0µF, VOUT = 10% VOUT(NOM) to
VOUT = 90% VOUT(NOM)
500
µs
Shutdown time (9)
IOUT = 150mA, COUT = 1.0µF, VOUT = 2.8V,
VOUT = 90% VOUT(NOM) to VOUT = 10%
VOUT(NOM)
500 (10)
µs
Shutdown, temperature increasing
+160
°C
Reset, temperature decreasing
+140
°C
tSTR
tSHDN
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
TSD
Thermal shutdown temperature
TJ
Operating junction temperature
–40
+125
°C
The output voltage for VSET = low/high is programmed at the factory.
Adjustable version only.
No VSET pin on the adjustable version.
No dynamic voltage scaling on the adjustable version.
VDO is not measured for devices with VOUT(NOM) < 2.3V because minimum VIN = 2.2V.
IGND = 800nA (max) up to +100°C.
The TPS78001 FB pin is tied to VOUT. Adjustable version only.
Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)).
Time from VEN = 0.4V to VOUT = 10% (VOUT(NOM)).
See Shutdown in the Application Information section for more details.
Copyright © 2007–2008, Texas Instruments Incorporated
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TPS780 Series
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FUNCTIONAL BLOCK DIAGRAM
IN
OUT
Current
Limit
EPROM
EN
Bandgap
MUX
Thermal
Shutdown
Active
PullDown
(1)
VSET/FB
10kW
LOGIC
GND
(1)
Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions.
PIN CONFIGURATIONS
TPS780DDC
TSOT23-5
(TOP VIEW)
TPS780DRV
2mm x 2mm SON-6
(TOP VIEW)
OUT
1
N/C
2
VSET/FB
3
6
IN
5
GND
4
EN
IN
1
GND
2
EN
3
5
OUT
4
VSET/FB
Thermal
Pad
(1)
(1) It is recommended that the SON package thermal pad be connected to ground.
Table 1. TERMINAL FUNCTIONS
TERMINAL
4
NAME
DRV
DDC
OUT
1
5
Regulated output voltage pin. A small (1µF) ceramic capacitor is needed from this pin to
ground to assure stability. See the Input and Output Capacitor Requirements in the
Application Information section for more details.
N/C
2
—
Not connected.
VSET/FB
3
4
Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions. Driving the select
pin (VSET) below 0.4V selects preset output voltage high. Driving the VSET pin over 1.2V
selects preset output voltage low.
EN
4
3
Driving the enable pin (EN) over 1.2V turns on the regulator. Driving this pin below 0.4V puts
the regulator into shutdown mode, reducing operating current to 18nA typical.
GND
5
2
Ground pin.
IN
6
1
Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input
capacitor = 1.0µF. Both input and output capacitor grounds should be tied back to the IC
ground with no significant impedance between them.
Thermal pad
Thermal pad
—
It is recommended that the SON package thermal pad be connected to ground.
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DESCRIPTION
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
TYPICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
LINE REGULATION
IOUT = 5mA, VOUT = 1.22V (typ)
TPS78001
LINE REGULATION
IOUT = 5mA, VVSET = 1.2V, VOUT = 2.2V (typ)
TPS780330220
0.3
1.0
0.8
0.2
0.6
VOUT (%)
VOUT (%)
TJ = +25°C
TJ = +125°C
0
-0.1
TJ = +25°C
TJ = +85°C
0.4
0.1
TJ = -40°C
0.2
0
-0.2
TJ = +125°C
-0.4
-0.6
-0.2
TJ = +85°C
TJ = -40°C
-0.8
-0.3
-1.0
2.2
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
Figure 1.
Figure 2.
LINE REGULATION
IOUT = 150mA, VVSET = 1.2V, VOUT = 2.2V (typ)
TPS780330220
LINE REGULATION
IOUT = 5mA, VVSET = 0.4V, VOUT = 3.3V (typ)
TPS780330220
3
1.0
0.8
2
TJ = +25°C
0.4
TJ = +25°C
VOUT (%)
1
VOUT (%)
TJ = -40°C
0.6
TJ = -40°C
0
-1
0.2
0
-0.2
TJ = +85°C
-0.4
TJ = +85°C
-2
-0.6
-0.8
-3
-1.0
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
Figure 3.
Figure 4.
LINE REGULATION
IOUT = 150mA, VVSET = 0.4V, VOUT = 3.3V (typ)
TPS780330220
LOAD REGULATION
VOUT = 3.3V
TPS78001
5.2
5.6
1.5
3
2
1.0
TJ = +125°C
1
TJ = -40°C
VOUT (%)
VOUT (%)
5.4
0
0.5
TJ = +25°C
0
-1
-0.5
-2
TJ = +85°C
TJ = +25°C
TJ = +85°C
TJ = -40°C
-1.0
-3
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
Figure 5.
Copyright © 2007–2008, Texas Instruments Incorporated
5.2
5.4
5.6
0
25
50
75
IOUT (mA)
100
125
150
Figure 6.
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TPS780 Series
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TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
LOAD REGULATION
VVSET = 1.2V, VIN = 2.7V, VOUT = 2.2V
TPS780330220
LOAD REGULATION
VVSET = 0.4V, VIN = 3.8V, VOUT = 3.3V
TPS780330220
3.0
3
2.5
2
2.0
TJ = -40°C
1
1.0
0.5
VOUT (%)
VOUT (%)
1.5
TJ = -40°C
0
-1
-0.5
TJ = +25°C
-1.0
TJ = +85°C
-2.0
0
25
50
-3
75
IOUT (mA)
100
125
150
0
25
50
75
IOUT (mA)
100
125
Figure 8.
DROPOUT VOLTAGE vs OUTPUT CURRENT
VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS78001
DROPOUT VOLTAGE vs OUTPUT CURRENT
VVSET = 0.4V, VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS780330220
250
180
TJ = +125°C
TJ = +85°C
140
200
VDO (VIN - VOUT) (mV)
160
TJ = +125°C
120
100
80
60
40
TJ = +85°C
150
100
50
TJ = -40°C
TJ = +25°C
20
TJ = -40°C
TJ = +25°C
0
0
0
25
50
75
IOUT (mA)
100
125
150
0
25
50
75
IOUT (mA)
100
125
150
Figure 9.
Figure 10.
DROPOUT VOLTAGE vs TEMPERATURE
VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS78001
DROPOUT VOLTAGE vs TEMPERATURE
VVSET = 0.4V, VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS780330220
250
250
200
150mA
150
100mA
100
50mA
50
VDO (VIN - VOUT) (mV)
200
150mA
150
100mA
100
50mA
50
10mA
10mA
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
Figure 11.
6
150
Figure 7.
200
VDO (VIN - VOUT) (mV)
TJ = +85°C
-2
TJ = +25°C
-1.5
VDO (VIN - VOUT) (mV)
0
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80
95
110 125
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 12.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 50mA, VOUT = 1.22V
TPS78001
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 150mA, VOUT = 1.22V
TPS78001
6
8
5
TJ = +85°C
TJ = +125°C
IGND (mA)
IGND (mA)
TJ = +125°C
6
4
3
2
5
4
3
TJ = +25°C
TJ = +25°C
TJ = -40°C
2
1
1
TJ = -40°C
0
0
2.2
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
2.2
3.7
4.2
VIN (V)
4.7
5.2
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 0mA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 1mA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220
800
700
IGND (nA)
600
500
400
TJ = +25°C
200
TJ = +125°C
900
TJ = +85°C
300
5.7
1000
TJ = +125°C
700
3.2
Figure 14.
900
800
2.7
Figure 13.
1000
IGND (nA)
TJ = +85°C
7
TJ = +85°C
600
500
400
300
TJ = -40°C
TJ = +25°C
200
100
TJ = -40°C
100
0
0
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
Figure 15.
Figure 16.
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 50mA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 150mA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220
6
5.7
12
11
5
10
TJ = +85°C
TJ = +125°C
9
TJ = +125°C
8
IGND (mA)
IGND (mA)
4
3
2
TJ = +85°C
7
6
5
4
TJ = +25°C
3
TJ = -40°C
1
TJ = +25°C
2
TJ = -40°C
1
0
0
2.7
3.2
3.7
4.2
VIN (V)
4.7
Figure 17.
Copyright © 2007–2008, Texas Instruments Incorporated
5.2
5.7
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 0mA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 1mA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220
1000
1000
900
900
TJ = +125°C
800
700
TJ = +85°C
600
TJ = +85°C
700
TJ = +25°C
IGND (nA)
IGND (nA)
TJ = +125°C
800
500
400
300
TJ = +25°C
600
500
400
300
200
100
TJ = -40°C
200
TJ = -40°C
100
0
0
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.4
Figure 19.
Figure 20.
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 50mA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220
GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 150mA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220
6
5.6
9
8
TJ = +85°C
TJ = +125°C
TJ = +85°C
5
TJ = +125°C
7
4
6
IGND (mA)
IGND (mA)
5.2
3
2
5
4
3
TJ = +25°C
TJ = +25°C
TJ = -40°C
2
TJ = -40°C
1
1
0
0
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
3.8
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
Figure 22.
GROUND PIN CURRENT vs OUTPUT CURRENT
VVSET = 1.2V, VIN = 5.5V, VOUT = 2.2V
TPS780330220
GROUND PIN CURRENT vs OUTPUT CURRENT
VVSET = 0.4V, VIN = 5.5V, VOUT = 3.3V
TPS780330220
10
8
8
TJ = +85°C
TJ = +125°C
TJ = +85°C
6
IGND (mA)
IGND (mA)
4.2
Figure 21.
10
4
2
TJ = +125°C
6
4
2
TJ = +25°C
TJ = -40°C
TJ = -40°C
TJ = +25°C
0
0
0
25
50
75
IOUT (mA)
Figure 23.
8
4.0
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100
125
150
0
25
50
75
IOUT (mA)
100
125
150
Figure 24.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
SHUTDOWN CURRENT vs INPUT VOLTAGE
IOUT = 0mA, VVSET = 0.4V
TPS78001
CURRENT LIMIT vs INPUT VOLTAGE
VOUT = 90% VOUT (typ), VOUT = 1.22V (typ)
TPS78001
60
280
270
50
TJ = -40°C
Current Limit (mA)
TJ = +85°C
IGND (nA)
40
30
TJ = +25°C
20
260
250
TJ = +25°C
240
230
220
10
0
200
2.2
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
2.2
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
Figure 26.
CURRENT LIMIT vs INPUT VOLTAGE
VVSET = 1.2V, VOUT = 95% VOUT (typ), VOUT = 2.2V (typ)
TPS780330220
CURRENT LIMIT vs INPUT VOLTAGE
VVSET = 0.4V, VOUT = 95% VOUT (typ), VOUT = 3.3V (typ)
TPS780330220
300
300
290
290
280
Current Limit (mA)
Current Limit (mA)
2.7
Figure 25.
280
TJ = -40°C
270
260
250
TJ = +25°C
240
TJ = +85°C
230
220
270
TJ = -40°C
260
250
TJ = +25°C
240
TJ = +85°C
230
220
TJ = +125°C
210
TJ = +125°C
210
200
200
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
Figure 27.
Figure 28.
FEEDBACK PIN CURRENT vs TEMPERATURE
IOUT = 0mA, VOUT = 1.22V
TPS78001
VSET PIN CURRENT vs INPUT VOLTAGE
IOUT = 100µA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220
5
1.0
4
0.8
3
0.6
IVSET (nA)
IFB (nA)
TJ = +85°C
210
TJ = -40°C
2
TJ = +25°C
TJ = -40°C
TJ = +85°C
5.6
0.4
VIN max
0.2
1
VIN min
0
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
Figure 29.
Copyright © 2007–2008, Texas Instruments Incorporated
95
110 125
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
VSET PIN CURRENT vs INPUT VOLTAGE
IOUT = 100µA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220
ENABLE PIN CURRENT vs INPUT VOLTAGE
IOUT = 1mA, VOUT = 1.22V
TPS78001
2.5
2.0
TJ = +125°C
1.8
2.0
1.6
1.4
IEN (nA)
IVSET (nA)
1.5
1.0
TJ = -40°C
TJ = +85°C
0.5
0
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
5.6
2.2
3.7
4.2
VIN (V)
4.7
5.2
ENABLE PIN CURRENT vs INPUT VOLTAGE
IOUT = 100µA, VVSET = 1.2V, VOUT = 2.2V
TPS780330220
ENABLE PIN CURRENT vs INPUT VOLTAGE
IOUT = 100µA, VVSET = 0.4V, VOUT = 3.3V
TPS780330220
2.0
1.8
1.8
1.6
1.6
1.4
1.4
1.2
1.2
TJ = +85°C
0.8
3.2
Figure 32.
2.0
1.0
2.7
Figure 31.
TJ = +25°C
IEN (nA)
IEN (nA)
0.8
0.2
-0.5
TJ = -40°C
1.0
TJ = +85°C
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
5.7
TJ = -40°C
TJ = +25°C
0
2.7
3.2
3.7
4.2
VIN (V)
4.7
5.2
5.7
3.8
4.0
4.2
4.4
4.6
4.8
VIN (V)
5.0
5.2
5.4
Figure 33.
Figure 34.
ENABLE PIN HYSTERESIS vs TEMPERATURE
IOUT = 1mA, TPS78001
ENABLE PIN HYSTERESIS vs TEMPERATURE
IOUT = 1mA, TPS780330220
1.2
1.2
1.1
1.1
1.0
5.6
1.0
VEN On
VEN (V)
0.9
0.8
0.7
VEN On
0.8
0.7
VEN Off
VEN Off
0.6
0.6
0.5
0.5
0.4
0.4
-40 -25 -10
5
20 35 50 65
Temperature (°C)
Figure 35.
10
TJ = -40°C
TJ = +25°C
0.4
TJ = +25°C
0.9
TJ = +85°C
1.0
0.6
0
VEN (V)
1.2
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80
95
110 125
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 36.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
%ΔVOUT vs TEMPERATURE
IOUT = 1mA, VIN = 3.8V, VOUT = 3.3V
TPS78001
%ΔVOUT vs TEMPERATURE
VVSET = 1.2V, VIN = 2.7V, VOUT = 2.2V (typ)
TPS780330220
0.4
1
0.3
0.1mA
0
%DVOUT (V)
%VOUT (V)
0.2
0.1
0
-0.1
5mA
-1
150mA
-0.2
-0.3
-0.4
-2
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
5
20 35 50 65
Temperature (°C)
95
110 125
Figure 38.
%ΔVOUT vs TEMPERATURE
VVSET = 0.4V, VIN = 3.8V, VOUT = 3.3V (typ)
TPS780330220
OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
CIN = 1µF, COUT = 2.2µF, VVSET = 1.2V, VIN = 2.7V
TPS780330220
Output Spectral Noise Density (mV/ÖHz)
2
1
0.1mA
0
5mA
-1
150mA
-2
-3
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
100
10
150mA
109mVRMS
1
0.1
50mA
109mVRMS
0.01
1mA
108mVRMS
0.001
10
110 125
100
1k
Frequency (Hz)
10k
100k
Figure 39.
Figure 40.
RIPPLE REJECTION vs FREQUENCY
VIN = 2.7V, VOUT = 1.2V, COUT = 2.2µF
TPS78001
INPUT VOLTAGE RAMP vs OUTPUT VOLTAGE
TPS780330220
80
VIN
1mA
60
50
40
50mA
Enable
VOUT
VIN = 0.0V to 5.0V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
Load Current
30
0V
20
Current (50mA/div)
Voltage (1V/div)
70
PSRR (dB)
80
Figure 37.
3
%DVOUT (V)
-40 -25 -10
150mA
10
0
10
100
1k
10k
100k
Frequency (Hz)
Figure 41.
Copyright © 2007–2008, Texas Instruments Incorporated
1M
10M
Time (20ms/div)
Figure 42.
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TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
OUTPUT VOLTAGE vs ENABLE (SLOW RAMP)
TPS780330220
VSET
Load Current
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
0A
0V
0V
VIN
Load Current
VIN = 0.0V to 5.5V
VOUT = 2.2V
IOUT = 100mA
COUT = 10mF
VOUT
Time (20ms/div)
Time (1ms/div)
Figure 43.
Figure 44.
LINE TRANSIENT RESPONSE
TPS780330220
LINE TRANSIENT RESPONSE
TPS780330220
VIN
VIN
1V/div
1V/div
VOUT
VIN = 4.0V to 4.5V
VOUT = 2.2V
IOUT = 150mA
Slew Rate = 1V/ms
Time (200ms/div)
Figure 45.
Figure 46.
LOAD TRANSIENT RESPONSE
TPS780330220
LOAD TRANSIENT RESPONSE
TPS780330220
Enable
Enable
Voltage
(100mV/div)
Voltage
(100mV/div)
VIN
VOUT
VIN = 4.0V to 4.5V
VOUT = 3.3V
IOUT = 150mA
Slew Rate = 1V/ms
Time (200ms/div)
VOUT
0A
Time (5ms/div)
Figure 47.
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VOUT
VIN
VIN = 5.5V
VOUT = 3.3V
IOUT = 0mA to 60mA
COUT = 10mF
Load
Current
Current
(20mA/div)
Load
Current
Current
(10mA/div)
VIN = 5.5V
VOUT = 3.3V
IOUT = 0mA to 10mA
COUT = 10mF
12
Current (50mA/div)
VOUT
Voltage (1V/div)
Enable
Current (50mA/div)
Voltage (1V/div)
VIN
INPUT VOLTAGE vs DELAY TO OUTPUT
TPS780330220
0A
Time (2ms/div)
Figure 48.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
ENABLE PIN vs OUTPUT VOLTAGE RESPONSE
AND OUTPUT CURRENT
TPS780330220
ENABLE PIN vs OUTPUT VOLTAGE DELAY
TPS780330220
VIN = 5.50V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
0V
Voltage (1V/div)
Load Current
VIN
Enable
VOUT
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF
Load
Current
0V
Time (1ms/div)
Current (50mA/div)
VOUT
VIN
Current (50mA/div)
Voltage (1V/div)
Enable
Time (1ms/div)
Figure 49.
Figure 50.
VSET PIN TOGGLE
TPS780330220
VSET PIN TOGGLE
TPS780330220
VOUT
VOUT
1V/div
VSET
VSET
1V/div
VIN = 5.0V
Enable = VIN
IOUT = 150mA
VOUT Transitioning from 2.2V to 3.3V
VIN = 5.0V
IOUT = 150mA
VOUT Transitioning from 3.3V to 2.2V
Time (500ms/div)
Time (500ms/div)
Figure 51.
Figure 52.
VSET PIN TOGGLE (SLOW RAMP)
TPS780330220
Current (50mA/div)
Voltage (1V/div)
VIN
VOUT
VSET
100mA
VIN = 5.5V
VOUT = 3.3V
50mA
IOUT = 150mA
to 100mA 0A
COUT = 10mF
Load Current
Time (50ms/div)
Figure 53.
Copyright © 2007–2008, Texas Instruments Incorporated
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APPLICATION INFORMATION
Programming the TPS78001 Adjustable LDO
Regulator
APPLICATION EXAMPLES
The TPS780 series of LDOs typically take less than
800µs to transition from a lower voltage of 2.2V to a
higher voltage of 3.3V under an output load of
150mA; see Figure 51. Additionally, the TPS780
series contain active pull-down circuitry that
automatically pulls charge out of the voltage capacitor
to transition the output voltage from the higher
voltage to the lower voltage, even with no load
connected.
Output
voltage
overshoots
and
undershoots are minimal under this load condition.
The TPS780 series typically take less than 800µs to
transition from VSET low (3.3V to 2.2V), or VSET high
(2.2V to 3.3V); see Figure 51 and Figure 52. Both
output states of the TPS780 series are
factory-programmable between 1.5V to 4.2V. Note
that during startup or steady-state conditions, it is
important that the EN pin and VSET pin voltages never
exceed VIN + 0.3V.
4.2V to 5.5V
VIN
2.2V to 3.3V
IN
VOUT
OUT
1mF
1m F
TPS780
On
Off
EN
(
)
Where:
VFB = 1.216V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for
approximately 1.2µA divider current. Lower value
resistors can be used for improved noise
performance, but the solution consumes more power.
Higher resistor values should be avoided because
leakage current into/out of FB across R1/R2 creates
an offset voltage that artificially increases/decreases
the feedback voltage and thus erroneously
decreases/increases VOUT. Table 2 lists several
common output voltages and resistor values. The
recommended design procedure is to choose R2 =
1MΩ to set the divider current at 1.2µA, and then
calculate R1 using Equation 2:
V
R1 = OUT - 1 ´ R2
VFB
(2)
(
VSET High = VOUT(LOW)
VSET Low = VOUT(HIGH)
The output voltage of the TPS78001 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 55. The output voltage
operating range is 1.2V to 5.1V, and is calculated
using Equation 1:
R
VOUT = VFB ´ 1 + 1
R2
(1)
)
VSET
GND
VIN
IN
VOUT
OUT
1mF
1m F
Figure 54. Typical Application Circuit
The TPS780 is also used effectively in dynamic
voltage scaling (DVS) applications. DVS applications
are required to dynamically switch between a high
operational voltage to a low standby voltage in order
to reduce power consumption. Modern multimillion
gate microprocessors fabricated with the latest
sub-micron processes save power by transitioning to
a lower voltage to reduce leakage currents while
maintaining content. This architecture enables the
microprocessor to transition quickly into an
operational state (wake up) without requiring a reload
of the states from external memory, or a reboot.
R1
TPS78001
FB
EN
R2
GND
VOUT = VFB ´ (1 +
R1
)
R2
Figure 55. TPS78001 Adjustable LDO Regulator
Programming
Table 2. Output Voltage Programming Guide
14
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OUTPUT VOLTAGE
R1
R2
1.8V
0.499MΩ
1MΩ
2.8V
1.33MΩ
1MΩ
5.0V
3.16MΩ
1MΩ
Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
Powering the MSP430 Microcontroller
Several versions of the TPS780 are ideal for
powering the MSP430 microcontroller. Table 3 shows
potential applications of some voltage versions.
3.0V
VIN
TPS780360200
VOUT(HIGH)
(TYP)
3.6V
VOUT(LOW)
(TYP)
2.0V
1m F
LDO
I/O
VSS
APPLICATION
3.6V
2.2V
VOUT, MIN > 2.200V
required by some
MSP430s FLASH
operation.
TPS780360300
3.6V
3.0V
VOUT, MIN > 2.700V
required by some
MSP430s FLASH
operation.
2.2V
VOUT, MIN < 3.600V
required by some
MSP430s. Allows
highest speed
operation.
3.6V
MSP430
GND
VOUT, MIN > 1.800V
required by many
MSP430s. Allows
lowest power
consumption
operation.
TPS780360220
TPS780360220
VCC
1m F
Table 3. Typical MSP430 Applications
DEVICE
VOUT
The TPS780 family offers many output voltage
versions to allow designers to optimize the supply
voltage for the processing speed required of the
MSP430. This flexible architecture minimizes the
supply current consumed by the particular MSP430
application. The MSP430 total system power can be
reduced by substituting the 500nA IQ TPS780 series
LDO in place of an existing ultra-low IQ LDO (typical
best case = 1µA). Additionally, DVS allows for
increasing the clock speed in active mode (MSP430
VCC = 3.6V). The 3.6V VCC reduces the MSP430 time
in active mode. In low-power mode, MSP430 system
power can be further reduced by lowering the
MSP430 VCC to 2.2V in sleep mode.
Key features of the TPS780 series are an ultralow
quiescent current (500nA), DVS, and miniaturized
packaging. The TPS780 family are available in
SON-6 and TSOT-23 packages. Figure 56 shows a
typical MSP430 circuit powered by an LDO without
DVS. Figure 57 is an MSP430 circuit using a TPS780
LDO that incorporates an integrated DVS, thus
simplifying the circuit design. In a circuit without DVS,
as Figure 56 illustrates, VCC is always at 3.0V. When
the MSP430 goes into sleep mode, VCC remains at
3.0V; if DVS is applied, VCC could be reduced in
sleep mode. In Figure 57, the TPS780 LDO with
integrated DVS maintains 3.6V VCC until a logic high
signal from the MSP430 forces VOUT to level shift
VOUT from 3.6V down to 2.2V, thus reducing power in
sleep mode.
Copyright © 2007–2008, Texas Instruments Incorporated
VCC = 3.0V
5mA
Active
Mode
1.6mA IQ
LPM3/Sleep Mode
Figure 56. Typical LDO without DVS
2.2V to 3.6V
VIN
VOUT
1m F
VCC
1m F
TPS780
VSET
MSP430
I/O
GND
VSS
VCC = 3.6V
VCC = 2.2V
5mA
Active
Mode
Current
700nA IQ
LPM3/Sleep Mode
Figure 57. TPS780 with Integrated DVS
The other benefit of DVS is that it allows a higher VCC
voltage on the MSP430, increasing the clock speed
and reducing the active mode dwell time.
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The total system power savings is outlined in Table 4,
Table 5, and Table 6. In Table 4, the MSP430 power
savings are calculated for various MSP430 devices
using a TPS780 series with integrated DVS versus a
standard ultralow IQ LDO without DVS. In Table 5, the
TPS780 series quiescent power is calculated for a VIN
of 4.2V, with the same VIN used for the ultralow IQ
LDO. Quiescent power dissipation in an LDO is the
VIN voltage times the ground current, because zero
load is applied. After the dissipation power is
calculated for the individual LDOs in Table 5, simple
subtraction outputs the LDO power savings using the
TPS780 series. Table 6 calculates the total system
power savings using a TPS780 series LDO in place
of an ultralow IQ 1.2µA LDO in an MSP430F1121
application. There are many different versions of the
MSP430. Actual power savings will vary depending
on the selected device.
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not
located near the power source. If source impedance
is not sufficiently low, a 0.1µF input capacitor may be
necessary to ensure stability.
The TPS780 is designed to be stable with standard
ceramic capacitors with values of 1.0µF or larger at
the output. X5R- and X7R-type capacitors are best
because they have minimal variation in value and
ESR over temperature. Maximum ESR should be less
than 1.0Ω. With tolerance and dc bias effects, the
minimum capacitance required to ensure stability is
1µF.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
output capacitor should connect directly to the GND
pin of the device. High ESR capacitors may degrade
PSRR.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1.0µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
Table 4. DVS MSP430 Power Savings with the TPS780 Series on selected MSP430 Devices
DEVICE
LPM3 AT VCC = 3V,
IQ
(µA)
LPM3 AT VCC = 3.0V
× IQ
(µW)
LPM3 AT VCC =
2.2V, IQ
(µA)
LPM3 AT VCC = 2.2V
× IQ
(µW)
µW SAVINGS
USING ONLY DVS
MSP430F1121
1.6
4.8
0.7
1.5
3.3
MSP430F149
1.6
4.8
0.9
2.0
2.8
MSP430F2131
0.9
2.7
0.7
1.5
1.2
MSP430F249
1.0
3.0
0.9
2.0
1.0
MSP430F413
0.9
2.7
0.7
1.5
1.2
MSP430F449
1.6
4.8
1.1
2.4
2.4
Table 5. Typical Ultralow IQ LDO Quiescent Power Dissipation Versus the TPS780 Series
TYPICAL ULTRALOW IQ
TYPICAL ULTRALOW IQ LDO AT +25°C AMBIENT
LDO AT +25°C AMBIENT
POWER DISSIPATION
TPS780 SERIES
TYPICAL IQ AT +25°C
AMBIENT
TPS780 SERIES AT
+25C AMBIENT, POWER
DISSIPATION
MSP430 SYSTEM
POWER SAVINGS
USING THE TPS780
SERIES
IQ
(µA)
IQ × VIN = 4.2V
(µW)
TPS780 IQ
(µA)
IQ × VIN = 4.2V
(µW)
QUIESCENT POWER
DISSIPATION SAVINGS
(µW)
1.20
5.04
0.42
1.76
3.28
Table 6. Total System Power Dissipation
LDO DISSIPATION
MSP430 DISSIPATION
TOTAL SYSTEM POWER IN
SLEEP MODE 3
5.04µW
4.8µW (1)
9.84µW
1.76µW
(1)
3.26µW
Typical 1.2µA LDO, no DVS
TPS780 Series with DVS
(1)
16
1.5µW
Value taken from Table 4 and relative to the MSP430F1121.
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Copyright © 2007–2008, Texas Instruments Incorporated
TPS780 Series
www.ti.com ....................................................................................................................................................... SBVS083C – JANUARY 2007 – REVISED MAY 2008
INTERNAL CURRENT LIMIT
4.2V to 5.5V
The TPS780 series are internally current-limited to
protect the regulator during fault conditions. During
current limit, the output sources a fixed amount of
current that is largely independent of output voltage.
For reliable operation, the device should not be
operated in a current limit state for extended periods
of time.
The PMOS pass element in the TPS780 series has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of
rated output current may be appropriate.
VIN
2.2V
IN
VOUT
OUT
1mF
1m F
TPS780
EN
VSET
GND
Figure 59. Circuit to Tie Both EN and VSET High
SHUTDOWN
DROPOUT VOLTAGE
The enable pin (EN) is active high and is compatible
with standard and low-voltage CMOS levels. When
shutdown capability is not required, EN should be
connected to the IN pin, as shown in Figure 58.
Figure 59 shows both EN and VSET connected to IN.
The TPS780 series, with internal active output
pull-down circuitry, discharges the output to within 5%
VOUT with a time (t) shown in Equation 3:
The TPS780 series use a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element.
VDO approximately scales with output current
because the PMOS device behaves like a resistor in
dropout. As with any linear regulator, PSRR and
transient response are degraded as (VIN – VOUT)
approaches dropout. This effect is shown in the
Typical Characteristics section. Refer to application
report SLVA207, Understanding LDO Dropout,
available for download from www.ti.com.
t=3
10kW ´ RL
´ COUT
10kW + RL
(3)
Where:
RL= output load resistance
COUT = output capacitance
TRANSIENT RESPONSE
4.2V to 5.5V
VIN
2.2V to 3.3V
IN
VOUT
OUT
1mF
1m F
TPS780
EN
VSET High = VOUT(LOW)
VSET Low = VOUT(HIGH)
VSET
GND
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. For
more information, see Figure 48.
ACTIVE VOUT PULL-DOWN
In the TPS780 series, the active pull-down discharges
VOUT when the device is off. However, the input
voltage must be greater than 2.2V for the active
pull-down to work.
MINIMUM LOAD
Figure 58. Circuit Showing EN Tied High when
Shutdown Capability is Not Required
Copyright © 2007–2008, Texas Instruments Incorporated
The TPS780 series are stable with no output load.
Traditional PMOS LDO regulators suffer from lower
loop gain at very light output loads. The TPS780
series employ an innovative, low-current circuit under
very light or no-load conditions, resulting in improved
output voltage regulation performance down to zero
output current. See Figure 47 for the load transient
response.
Submit Documentation Feedback
17
TPS780 Series
SBVS083C – JANUARY 2007 – REVISED MAY 2008 ....................................................................................................................................................... www.ti.com
THERMAL INFORMATION
THERMAL PROTECTION
POWER DISSIPATION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. Once the junction
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off again. This cycling limits the dissipation of
the regulator, protecting it from damage as a result of
overheating.
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are given in the Dissipation Ratings table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness. Power
dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 4:
PD = (VIN - VOUT) ´ IOUT
(4)
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces a worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS780 series are available from the Texas
Instruments web site at www.ti.com through the
TPS780 series product folders.
The internal protection circuitry of the TPS780 series
has been designed to protect against overload
conditions. However, it is not intended to replace
proper heatsinking. Continuously running the TPS780
series into thermal shutdown degrades device
reliability.
18
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS78001DDCR
ACTIVE
SOT
DDC
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS78001DDCRG4
ACTIVE
SOT
DDC
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS78001DDCT
ACTIVE
SOT
DDC
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS78001DDCTG4
ACTIVE
SOT
DDC
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS78001DRVR
ACTIVE
SON
DRV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS78001DRVRG4
ACTIVE
SON
DRV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS78001DRVT
ACTIVE
SON
DRV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS78001DRVTG4
ACTIVE
SON
DRV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS780270200DDCR
PREVIEW
SOT
DDC
5
3000
TBD
Call TI
Call TI
TPS780270200DDCT
PREVIEW
SOT
DDC
5
250
TBD
Call TI
Call TI
TPS780330220DDCR
ACTIVE
SOT
DDC
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS780330220DDCRG4
ACTIVE
SOT
DDC
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS780330220DDCT
ACTIVE
SOT
DDC
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS780330220DDCTG4
ACTIVE
SOT
DDC
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS780330220DRVR
ACTIVE
SON
DRV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS780330220DRVRG4
ACTIVE
SON
DRV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS780330220DRVT
ACTIVE
SON
DRV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS780330220DRVTG4
ACTIVE
SON
DRV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-Aug-2008
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS78001DDCR
Package Package Pins
Type Drawing
SOT
DDC
5
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS78001DDCT
SOT
DDC
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS78001DRVR
SON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS78001DRVT
SON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS780330220DDCR
SOT
DDC
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS780330220DDCT
SOT
DDC
5
250
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
TPS780330220DRVR
SON
DRV
6
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS780330220DRVT
SON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS78001DDCR
SOT
DDC
5
3000
195.0
200.0
45.0
TPS78001DDCT
SOT
DDC
5
250
195.0
200.0
45.0
TPS78001DRVR
SON
DRV
6
3000
195.0
200.0
45.0
TPS78001DRVT
SON
DRV
6
250
195.0
200.0
45.0
TPS780330220DDCR
SOT
DDC
5
3000
195.0
200.0
45.0
TPS780330220DDCT
SOT
DDC
5
250
195.0
200.0
45.0
TPS780330220DRVR
SON
DRV
6
3000
195.0
200.0
45.0
TPS780330220DRVT
SON
DRV
6
250
195.0
200.0
45.0
Pack Materials-Page 2
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