TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com 200-mA, Low IQ, Low-Noise, Low-Dropout Regulator in Ultra-Small 0.8-mm x 0.8-mm WCSP FEATURES DESCRIPTION • Very Low Dropout: – 105 mV at IOUT = 150 mA – 145 mV at IOUT = 200 mA • Accuracy: 0.5% Typical • Low IQ: 35 μA • Available in Fixed-Output Voltages from 0.7 V to 4.8 V • High PSRR: 70 dB at 1 kHz • Stable with Effective Capacitance of 0.1 μF • Thermal Shutdown and Overcurrent Protection • Available in 0.8-mm x 0.8-mm WCSP • Available in Two WCSP Height Options: – YFF: 0.625 mm Max Height – YFP: 0.5 mm Max Height The TLV705 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. Designed for power-sensitive applications, a precision bandgap and error amplifier provides typical accuracy of 0.5%. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of LDOs ideal for a wide selection of battery-operated hand-held equipment. All devices have a thermal shutdown and current limit for safety. 1 234 APPLICATIONS • • • • • • • Wireless Handsets Smart Phones, PDAs MP3 Players Zigbee™ Networks Bluetooth® Devices Other Li-Ion Operated Hand-Held Products WLAN and Other PC Add-On Cards YFF, YFP PACKAGES WCSP-4 (TOP VIEW) EN VIN GND VOUT A B Furthermore, the TLV705 is stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltage and temperature derating. The devices regulate to the specified accuracy with zero output load. The TLV705P series also provides an active pull-down circuit to quickly discharge output. The TLV705 and TLV705P series are both available in a 0.8-mm × 0.8-mm WCSP with two height options that are optimal for hand-held applications. VOUT VIN Input CIN COUT Output 1 mF Ceramic TLV705 On Off EN GND Typical Application Circuit (Fixed-Voltage Versions) 2 1 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Bluetooth is a registered trademark of Bluetooth SIG, Inc. Zigbee is a trademark of ZigBee Alliance. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AVAILABLE OPTIONS (1) PRODUCT VOUT XX(X) is nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example 28 = 2.8 V). P is optional; devices with P have an LDO regulator with an active output discharge. YYY is Package Designator Z is Package Quantity; R is for Reel (3000 pieces), T is for Tape (250 pieces) TLV705xx(x)Pyyyz (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Specified at TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND. VALUE Voltage (2) Maximum output current MIN MAX VIN –0.3 6 V VEN –0.3 6 V VOUT –0.3 6 V IOUT Internally limited Output short-circuit duration Indefinite Continuous total power dissipation PDISS Temperature Electrostatic Discharge Rating (3) (1) (2) (3) UNIT See Table 2 Operating junction, TJ –55 +150 °C Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM) QSS 009-105 (JESD22-A114A) Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TLV705 THERMAL METRIC (1) YFF, YFP UNITS 4 BALLS θJA Junction-to-ambient thermal resistance 160 θJCtop Junction-to-case (top) thermal resistance 80 θJB Junction-to-board thermal resistance 90 ψJT Junction-to-top characterization parameter 0.5 ψJB Junction-to-board characterization parameter 78 θJCbot Junction-to-case (bottom) thermal resistance N/A (1) 2 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS At TJ = –40°C to +125°C, VIN = VOUT (typ) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA, VEN = 0.9 V, and COUT = 1 μF, unless otherwise noted. Typical values are at TJ = +25°C. TLV705 PARAMETER VIN TEST CONDITIONS MIN Input voltage range VOUT VO Output voltage range DC output accuracy –40°C ≤ TJ ≤ +125°C ±5 20 mV 0.05 5 mV 1 Dropout voltage (1) VIN = 0.98 × VOUT(NOM), IOUT = 200 mA ICL Output current limit VOUT = 0.9 × VOUT(NOM), TJ = +25°C IOUT = 200 mA 250 mV 400 550 mA 35 55 μA μA 1 80 dB VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 MHz 55 dB VIN = 2.3 V, VOUT = 1.8 V 26.6 μVRMS VIN = 3.3 V, VOUT = 2.8 V 26.7 μVRMS VIN = 3.8 V, VOUT = 3.3 V 28.2 μVRMS VIN = 2.3 V, VOUT = 1.8 V 30.7 μVRMS VIN = 3.3 V, VOUT = 2.8 V 31.3 μVRMS VIN = 3.8 V, VOUT = 3.3 V 34.1 μVRMS COUT = 1 μF, IOUT = 200 mA μs 100 VHI Enable high (enabled) 0.9 VIN VLO Enable low (disabled) 0 0.4 IEN EN pin current UVLO Undervoltage lockout tSD Thermal shutdown temperature TJ Operating junction temperature (1) (2) μA 1.8 VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 10 kHz BW = 10 Hz to 100 kHz, IOUT = 10 mA Startup time mV 145 315 VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V Output noise voltage tSTR 260 IOUT = 0 mA BW = 100 Hz to 100 kHz, IOUT = 10 mA (2) V –20 VDO VN V 0 mA ≤ IOUT ≤ 200 mA, VOUT < 1 V 0 mA ≤ IOUT ≤ 200 mA Power-supply rejection ratio 4.8 % VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.5 V PSRR 5.5 2 Line regulation Shutdown ground pin current 2 0.7 ±0.5 Load regulation ISHUTDOWN UNIT –2 ΔVO/ΔIOUT Ground pin current MAX 0 mA ≤ IOUT ≤ 200 mA, VOUT ≥ 1 V ΔVO/ΔVIN IGND TYP EN = 5.5 V V μA 0.01 VIN rising V 1.9 V Shutdown, temperature increasing +160 °C Reset, temperature decreasing +140 °C –40 +125 °C VDO is measured for devices with VOUT(NOM) = 2.35 V so that VIN = 2.3 V. Startup time = time from EN assertion to 0.98 × VOUT(NOM). Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 3 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS VOUT VIN Current Limit Thermal Shutdown UVLO EN Bandgap LOGIC TLV705 Series GND Figure 1. TLV705 Diagram TLV705P Series VOUT VIN Current Limit Thermal Shutdown 120 W UVLO EN Bandgap LOGIC GND Figure 2. TLV705P Diagram 4 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com PIN CONFIGURATION YFF, YFP PACKAGES WCSP-4 (TOP VIEW) EN VIN GND VOUT A B 2 1 Table 1. Pin Descriptions TLV705 NAME PIN # DESCRIPTION GND A1 Ground pin EN A2 Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode, thus reducing operating current to 1 μA, nominal. VOUT B1 Regulated output voltage pin. A small 1-μF ceramic capacitor is required to be placed from this pin to ground to assure stability. See the Input and Output Capacitor Requirements section for more details. VIN B2 Input pin. A small 1-μF ceramic capacitor is recommended to be placed from this pin to ground for good transient performance. See the Input and Output Capacitor Requirements section for more details. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 5 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(TYP) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = +25°C. LINE REGULATION LINE REGULATION 1.90 1.90 VOUT = 1.8 V IOUT = 10 mA 1.88 1.86 1.84 1.84 1.82 1.82 VOUT (V) VOUT (V) 1.86 1.80 1.78 1.76 1.72 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 VOUT = 1.8 V IOUT = 200 mA 1.88 +125°C +85°C +25°C -40°C 1.74 1.72 1.70 1.70 2.1 2.6 3.1 3.6 4.1 VIN (V) 4.6 5.1 2.1 5.6 2.6 3.1 3.6 4.1 VIN (V) Figure 3. 5.6 DROPOUT VOLTAGE vs INPUT VOLTAGE 250 VOUT = 1.8 V 1.88 5.1 Figure 4. LOAD REGULATION ( 0 mA ≤ IOUT ≤ 200 mA) 1.90 4.6 IOUT = 200 mA 200 1.86 1.82 VDO (mV) VOUT (V) 1.84 1.80 1.78 1.76 +125°C +85°C +25°C -40°C 1.74 1.72 150 100 +125°C +85°C +25°C -40°C 50 0 1.70 0 50 100 150 2 200 2.25 2.5 2.75 IOUT (mA) 3 3.25 3.5 3.75 4 4.25 4.5 4.75 VIN (V) Figure 5. Figure 6. DROPOUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs TEMPERATURE 140 1.90 VOUT = 4.8 V VOUT = 1.8 V 1.88 120 1.84 80 1.82 VOUT (V) VDO (mV) 1.86 100 60 40 +125°C +85°C +25°C -40°C 20 0 1.78 1.76 10mA 150mA 200mA 1.74 1.72 1.70 0 50 100 IOUT (mA) Figure 7. 6 1.80 Submit Documentation Feedback 150 200 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 8. Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(TYP) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = +25°C. GROUND PIN CURRENT vs INPUT VOLTAGE 50 GROUND PIN CURRENT vs OUTPUT CURRENT 400 VOUT = 1.8 V IOUT = 0 mA 45 40 300 35 30 IGND (mA) IGND (mA) VOUT = 1.8 V 350 25 20 15 +125°C +85°C +25°C -40°C 10 5 250 200 150 +125°C +85°C +25°C -40°C 100 50 0 0 2.3 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 0 5.5 50 100 IOUT (mA) Figure 9. 150 200 Figure 10. GROUND PIN CURRENT vs TEMPERATURE SHUTDOWN PIN CURRENT vs INPUT VOLTAGE 2.5 50 VOUT = 1.8 V IOUT = 0 mA 45 VOUT = 1.8 V 2 40 ISHDN (mA) IGND (mA) 35 30 25 20 1.5 1 15 +125°C +85°C +25°C -40°C 0.5 10 5 0 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 2.3 110 125 2.7 3.1 3.5 3.9 VIN (V) 4.3 4.7 5.1 5.5 Figure 11. Figure 12. CURRENT LIMIT vs INPUT VOLTAGE POWER-SUPPLY REJECTION RATIO vs FREQUENCY 500 100 VOUT = 1.8 V VIN = 2.3 V VOUT = 1.8 V 90 470 80 PSRR (dB) ILIM (mA) 70 440 +25°C 410 60 50 40 30 380 20 IOUT = 10 mA IOUT = 150 mA 10 350 0 2.5 3 3.5 4 VIN (V) 4.5 Figure 13. Copyright © 2010–2011, Texas Instruments Incorporated 5 5.5 10 100 1k 10k 100k Frequency (Hz) 1M 10M Figure 14. Submit Documentation Feedback 7 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(TYP) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = +25°C. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY 100 10 Output Spectral Noise Density (mV/ÖHz) POWER-SUPPLY REJECTION RATIO vs INPUT VOLTAGE VOUT = 1.8 V 90 80 PSRR (dB) 70 60 50 40 30 1 kHz 10 kHz 100 kHz 20 10 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 VOUT = 1.8 V 1 0.1 0.01 0 10 100 Input Voltage (V) 1k 10 k 100 k Frequency (Hz) Figure 15. Figure 16. INTEGRATED NOISE vs OUTPUT VOLTAGE LOAD TRANSIENT 0 45 10 M tR = tF = 1 ms 40 Integrated Noise (mVRMS) 1M 35 VOUT 30 (20 mV/div) 25 20 200 mA 15 (100 mA/div) 10 IOUT Bandwidth: 100 Hz to 100 kHz Bandwidth: 10 Hz to 100 kHz 5 0 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 0 mA Time (200 ms/div) 4.8 VOUT (V) Figure 17. Figure 18. LOAD TRANSIENT 1 LOAD TRANSIENT 3 tR = tF = 1 ms tR = tF = 1 ms (20 mV/div) VOUT VOUT (20 mV/div) 200 mA (50 mA/div) (100 mA/div) IOUT 1 mA 1 mA Time (200 ms/div) Figure 19. 8 100 mA IOUT Submit Documentation Feedback Time (200 ms/div) Figure 20. Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(TYP) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = +25°C. SMALL-STEP LINE TRANSIENT (10mA) SMALL-STEP LINE TRANSIENT (200mA) Slew Rate = 1 V/ms 2.9 V 2.9 V VIN Slew Rate = 1 V/ms VIN (200 mV/div) (200 mV/div) 2.3 V (5 mV/div) VOUT 2.3 V (5 mV/div) VOUT Time (100 ms/div) Time (100 ms/div) Figure 21. Figure 22. VIN INRUSH CURRENT VIN INRUSH CURRENT IOUT = 0 mA IOUT = 200 mA C2 (1 V/div) C2 (1 V/div) C1 (1 V/div) C1 (1 V/div) C4 (100 mA/div) C4 (100 mA/div) Time (50 ms/div) Time (10 ms/div) Figure 23. Figure 24. LINE TRANSIENT (10mA) LINE TRANSIENT (200mA) Slew Rate = 1 V/ms 5.5 V 5.5 V (2 V/div) (5 mV/div) (2 V/div) VIN 2.3 V VOUT (5 mV/div) VIN 2.3 V VOUT Slew Rate = 1 V/ms Time (100 ms/div) Time (100 ms/div) Figure 25. Figure 26. Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 9 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over operating temperature range (TJ = –40°C to +125°C), IOUT = 10 mA, VEN = 0.9 V, COUT = 1 μF, and VIN = VOUT(TYP) + 0.5 V or 2 V, whichever is greater, unless otherwise noted. Typical values are at TJ = +25°C. POWER-UP/POWER-DOWN VIN (1 V/div) VOUT Time (100ms/div) Figure 27. 10 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com APPLICATION INFORMATION The TLV705 and TLV705P series of devices belong to a new family of next-generation value low-dropout (LDO) voltage regulators. They consume low quiescent current and deliver excellent line and load transient performance. This performance, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, makes these devices ideal for RF portable applications. This family of regulators offers sub-bandgap output voltages down to 0.7 V, current limit, and thermal protection, and are specified from –40°C to +125°C. The TLV705P provides an active pull-down circuit to quickly discharge the outputs. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE INPUT AND OUTPUT CAPACITOR REQUIREMENTS INTERNAL CURRENT LIMIT 1-μF X5R- and X7R-type ceramic capacitors are recommended because these components have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV705 series is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. Thus, the device would also be stable with capacitors of other dielectrics as long as the effective capacitance under the operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions (that is, the capacitance after taking the bias voltage and temperature derating into consideration). In addition to allowing the use of lower cost dielectrics, it also enables using smaller footprint capacitors that have higher derating in space-constrained applications. Note that using a 0.1-μF rating capacitor at the output of the LDO does not ensure stability because the effective capacitance under operating conditions would be less than 0.1 μF. Maximum ESR should be less than 200 mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1-μF low ESR capacitor across the VIN and GND pins of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability. Copyright © 2010–2011, Texas Instruments Incorporated Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance (such as PSRR, output noise, and transient response), it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR. The internal current limits of the TLV705 series help protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output voltage is not regulated, and can be measured as VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown; see the Thermal Information section for more details. The PMOS pass element in the TLV705 has a built-in body diode that conducts current when the voltage at VOUT exceeds the voltage at VIN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of rated output current is recommended. SOFT-START The startup current is given by Equation 1. This equation shows that soft-start current is directly proportional to COUT. ISOFT-START = COUT (μF) × 0.06 (V/μs) + ILOAD (mA) (1) The output voltage ramp rate is independent of COUT and the load current, and has a typical value of 0.06 V/μs. The TLV705 automatically adjusts the soft-start current to supply both the load current and the current to charge COUT. For example, if ILOAD = 0 mA upon enabling the LDO, then ISOFT-START = 1 μF × 0.06 V/μs + 0 mA = 60 mA, which is the current that charges the output capacitor. However if ILOAD = 200 mA, then ISOFT-START = 1 μF × 0.06 V/μs + 200 mA = 260 mA, which is the current required for charging the output capacitor and supplying the load current. Submit Documentation Feedback 11 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, it is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, then 10 μF × 0.06 V/μs + 200 mA = 800 mA is not supplied. Instead, it is clamped at 400 mA. SHUTDOWN The enable pin (EN) is active high. The device is enabled when the EN pin goes above 0.9 V. This relatively lower value of voltage required to turn the LDO on can be used to power the device with the GPIO of recent processors with a GPIO voltage lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the VIN pin. The TLV705P version has internal active pull-down circuitry that discharges the output with a time constant of: τ = (120 × RL)/(120 + RL) × COUT Where: RL = load resistance, COUT = output capacitor (2) DROPOUT VOLTAGE The TLV705 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with the output current because the PMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 15 in the Typical Characteristics. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude, but increases the duration of the transient response. UNDERVOLTAGE LOCK-OUT (UVLO) The TLV705 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry is operating properly. www.ti.com dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C, maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TLV705 is been designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TLV705 into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Refer to Table 2 for thermal performance on the TLV705 evaluation module (EVM). The EVM is a two-layer board with two ounces of copper per side. Dimensions and layout of the board are illustrated in Figure 28 and Figure 29, respectively. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 3: PD = (VIN – VOUT) × IOUT (3) THERMAL INFORMATION Thermal protection disables the output when the junction temperature rises to approximately +165°C, allowing the device to cool. When the junction temperature cools to approximately +145°C, the output circuitry is again enabled. Depending on power 12 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com Table 2. Power Dissipation Ratings (1) (1) BOARD PACKAGE RθJ TA ≤ 25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING High-K YFF, YFP 140 °C/W 714 mW 392 mW 285 mW Thermal resistance as measured on the evaluation module (EVM). Figure 28. Silkscreen, Top Layer Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 13 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com Figure 29. Silkscreen, Bottom Layer 14 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P www.ti.com SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 MECHANICAL PACKAGES Figure 30 and Figure 31 show the YFF and YFP mechanical packages, respectively, with maximum and minimum heights noted. X: Max = 0.826 mm. Min = 0.726 mm Y: Max = 0.826 mm, Min = 0.726 mm Figure 30. YFF Package Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 15 TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com X: Max = 0.826 mm. Min = 0.726 mm Y: Max = 0.826 mm. Min = 0.726 mm Figure 31. YFP Package 16 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated TLV705 TLV705P SBVS151B – DECEMBER 2010 – REVISED DECEMBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2011) to Revision B Page • Added last Features bullet .................................................................................................................................................... 1 • Changed front page pin out drawing .................................................................................................................................... 1 • Changed last sentence of Description section ..................................................................................................................... 1 • Added YFP package to Thermal Information table ............................................................................................................... 2 • Added YFP to title of pin out drawing ................................................................................................................................... 5 • Added YFP to Package column of Table 2 ........................................................................................................................ 13 • Added Mechanical Packages section ................................................................................................................................. 15 Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 17 PACKAGE OPTION ADDENDUM www.ti.com 25-Jun-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV705185YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70518YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70518YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70525YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70525YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70528YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70528YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70530YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70530YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70533YFFR ACTIVE DSBGA YFF 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70533YFFT ACTIVE DSBGA YFF 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70533YFPR ACTIVE DSBGA YFP 4 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM TLV70533YFPT ACTIVE DSBGA YFP 4 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples (Requires Login) TLV705185YFPR (1) (3) PACKAGE OPTION ADDENDUM www.ti.com 25-Jun-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jun-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TLV705185YFPR DSBGA YFP 4 3000 180.0 8.4 TLV705185YFPT DSBGA YFP 4 250 180.0 TLV70518YFPR DSBGA YFP 4 3000 180.0 TLV70518YFPT DSBGA YFP 4 250 TLV70525YFPR DSBGA YFP 4 W Pin1 (mm) Quadrant 0.86 0.86 0.59 4.0 8.0 Q1 8.4 0.86 0.86 0.59 4.0 8.0 Q1 8.4 0.86 0.86 0.59 4.0 8.0 Q1 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 3000 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70525YFPT DSBGA YFP 4 250 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70528YFPR DSBGA YFP 4 3000 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70528YFPT DSBGA YFP 4 250 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70530YFPR DSBGA YFP 4 3000 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70530YFPT DSBGA YFP 4 250 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70533YFFR DSBGA YFF 4 3000 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1 TLV70533YFFT DSBGA YFF 4 250 180.0 8.4 0.85 0.85 0.64 4.0 8.0 Q1 TLV70533YFPR DSBGA YFP 4 3000 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 TLV70533YFPT DSBGA YFP 4 250 180.0 8.4 0.86 0.86 0.59 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jun-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV705185YFPR DSBGA YFP 4 3000 210.0 185.0 35.0 TLV705185YFPT DSBGA YFP 4 250 210.0 185.0 35.0 TLV70518YFPR DSBGA YFP 4 3000 210.0 185.0 35.0 TLV70518YFPT DSBGA YFP 4 250 210.0 185.0 35.0 TLV70525YFPR DSBGA YFP 4 3000 210.0 185.0 35.0 TLV70525YFPT DSBGA YFP 4 250 210.0 185.0 35.0 TLV70528YFPR DSBGA YFP 4 3000 210.0 185.0 35.0 TLV70528YFPT DSBGA YFP 4 250 210.0 185.0 35.0 TLV70530YFPR DSBGA YFP 4 3000 210.0 185.0 35.0 TLV70530YFPT DSBGA YFP 4 250 210.0 185.0 35.0 TLV70533YFFR DSBGA YFF 4 3000 210.0 185.0 35.0 TLV70533YFFT DSBGA YFF 4 250 210.0 185.0 35.0 TLV70533YFPR DSBGA YFP 4 3000 210.0 185.0 35.0 TLV70533YFPT DSBGA YFP 4 250 210.0 185.0 35.0 Pack Materials-Page 2 X: Max = 0.826 mm, Min =0.726 mm Y: Max = 0.826 mm, Min =0.726 mm X: Max = 0.826 mm, Min =0.726 mm Y: Max = 0.826 mm, Min =0.726 mm X: Max = 0.826 mm, Min =0.726 mm Y: Max = 0.826 mm, Min =0.726 mm X: Max = 0.826 mm, Min =0.726 mm Y: Max = 0.826 mm, Min =0.726 mm IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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