TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable Devices FEATURES DESCRIPTION • • • • • The TLV707 series (TLV707xx and TLV707xxP) of low-dropout linear regulators (LDOs) are low quiescent current devices with excellent line and load transient performance, and are designed for power-sensitive applications. These devices provide a typical accuracy of 0.5%. All versions have thermal shutdown and overcurrent protection for safety. Furthermore, these devices are stable with an effective output capacitance of only 0.1 µF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. These devices also regulate to the specified accuracy with no output load. 1 2 • • • • Very Low Dropout: 250 mV at 150 mA 0.5% Typical Accuracy 1.5% Accuracy over Temperature Low IQ: 25 μA Fixed-Output Voltage Combinations Possible from 1.2 V to 5.0 V(1) High PSRR: – 70 dB at 100 Hz – 50 dB at 1 MHz Stable with Effective Capacitance of 0.1 μF(2) Thermal Shutdown and Overcurrent Protection Package: 1-mm × 1-mm DFN (SON) (1) See Package Option Addendum at end of this document for complete list of available voltage options. (2) See Input and Output Capacitor Requirements in the Application Information section for more details. The TLV707xxP also provides an active pull-down circuit to quickly discarge the outputs. The TLV707 series are available in a 1-mm x 1-mm DFN (SON) package that makes them ideal for handheld applications. APPLICATIONS • • • Wireless Handsets, Smart Phones, and PDAs MP3 Players and Other Handheld Devices WLAN and Other PC Add-On Cards Typical Application Circuit (Fixed Voltage Versions) VIN IN OUT CIN COUT VOUT 1 mF Ceramic TLV707 Series TLV707 Series DQN PACKAGE 1-mm ´ 1-mm DFN-4 (TOP VIEW) IN 4 On Off EN GND EN 3 Thermal Pad 1 2 OUT GND 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (2) PRODUCT VOUT TLV707xx(x)Pyyyz XX(X) is the nominal output voltage. For output voltages with a resolution of 100mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 18 = 1.8V, 285 = 2.85V). P is optional; devices with P have an LDO regulator with an active output discharge. YYY is the package designator. Z is package quantity. Use R for reel (3000 pieces), and T for tape (250 pieces). (1) (2) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. Output voltages from 1.2 V to 5.0 V in 50-mV increments are available. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE Voltage (2) Current (source) MIN MAX UNIT IN –0.3 +6.0 V EN –0.3 +6.0 V OUT –0.3 +6.0 V OUT Internally limited Output short-circuit duration Temperature Electrostatic Discharge Ratings (3) (1) (2) (3) Indefinite Operating junction, TJ –55 +150 Storage, Tstg –55 +150 °C 2 kV 500 V Human body model (HBM) QSS 009-105 (JESD22-A114A) Charged device model (CDM) QSS 009-147 (JESD22-C101B.01) °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TLV707xx, TLV707xxP THERMAL METRIC (1) DQN (DFN) UNITS 4 PINS θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance N/A θJB Junction-to-board thermal resistance N/A ψJT Junction-to-top characterization parameter 6.0 ψJB Junction-to-board characterization parameter N/A θJCbot Junction-to-case (bottom) thermal resistance N/A (1) 249.9 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A. DISSIPATION RATINGS 2 PACKAGE RθJA TA < +25°C DQN 249.9°C/W 400 mW 220 mW 160 mW DCK 354.4°C/W 282 mW 155.2 mW 112.9 mW Submit Documentation Feedback TA = +70°C TA = +85°C Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS At VIN = VOUT(TYP) + 0.5V or 2.0 V (whichever is greater); IOUT = 1 mA, VEN = VIN, COUT = 0.47 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. SPACE TLV707 Series PARAMETER VIN Input voltage range VO Output voltage range VOUT DC output accuracy ΔVO/ΔVIN Line regulation ΔVO/ΔIOUT Load regulation TEST CONDITIONS VOUT ≥ 1.2 V, TA = –40°C to +85°C VIN = 0.98 x VOUT(NOM) ICL Output current limit VOUT = 0.9 × VOUT(NOM) IGND Ground pin current IOUT = 0 mA ISHUTDOWN Shutdown current VEN ≤ 0.4 V, 2.0 V ≤ VIN ≤ 4.5 V V VIN = 3.3 V, VOUT = 2.8 V, IOUT = 30 mA % +1.5 % 1 5 mV 10 20 mV IOUT = 30 mA 65 IOUT = 150 mA 325 mV 360 mV IOUT = 30 mA 50 IOUT = 150 mA 250 IOUT = 30 mA 45 IOUT = 150 mA 220 IOUT = 30 mA 40 IOUT = 150 mA 200 250 mV 300 450 mA 25 50 µA 240 mV 300 mV mV 270 mV mV 1 µA f = 100 Hz 70 dB f = 10 kHz 55 dB f = 1 MHz 50 dB 45 µVRMS VN Output noise voltage BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA tSTR Startup time (1) COUT = 1.0 µF, IOUT = 150 mA µs 100 VEN(HI) EN pin high (enabled) 0.9 VIN V VEN(LO) EN pin low (disabled) 0 0.4 V IEN EN pin current VEN = 5.5 V UVLO Undervoltage lockout VIN rising RPULLDOWN Pull-down resistance (TLV707xxP only) TJ (1) V 5.0 –1.5 0 mA ≤ IOUT ≤ 150 mA 3.3 V < VOUT ≤ 5.0 V PSRR UNIT 5.5 0.5 2.8 V < VOUT ≤ 3.3 V Power-supply rejection ratio MAX 1.2 TA = +25°C 2.4 V < VOUT ≤ 2.8 V Dropout voltage TYP 2.0 2.0 V < VOUT ≤ 2.4 V VDO MIN Operating junction temperature –40 0.01 µA 1.9 V 120 Ω +125 °C Startup time = time from EN assertion to 0.98 × VOUT(NOM). Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 3 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAMS IN OUT Current Limit Thermal Shutdown EN Bandgap LOGIC TLV707xx GND Figure 1. TLV707xx Block Diagram IN OUT Current Limit Thermal Shutdown UVLO EN 120 W Bandgap LOGIC TLV707xxP GND Figure 2. TLV707xxP Block Diagram 4 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com PIN CONFIGURATIONS DQN PACKAGE DFN-4 (TOP VIEW) IN 4 EN 3 Thermal Pad 1 2 OUT GND PIN DESCRIPTIONS PIN NAME NO. DESCRIPTION OUT 1 Regulated output voltage pin. A small 1μF ceramic capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor Requirements in the Application Information section for more details. GND 2 Ground pin EN 3 Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode For TLV707xxP, output voltage is discharged through an internal 120-Ω resistor when device is shut down. IN 4 Input pin. A small 1µF ceramic capacitor is recommended from this pin to ground for good transient performance. See Input and Output Capacitor Requirements in the Application Information section for more details. NC — No connection. This pin can be tied to ground to improve thermal dissipation. Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. LOAD REGULATION 1.3 LOAD REGULATION 2.9 VOUT = 1.2 V 1.28 2.86 Output Voltage (V) 1.26 Output Voltage (V) VOUT = 2.8 V 2.88 1.24 1.22 1.2 1.18 1.16 +85°C +25°C -40°C 1.14 1.12 2.84 2.82 2.8 2.78 2.76 +85°C +25°C -40°C 2.74 2.72 1.1 2.7 0 20 40 60 80 100 120 140 160 180 Output Current (mA) 200 0 20 40 60 Figure 3. LINE REGULATION 1.3 VOUT = 5.0 V 5.08 1.26 Output Voltage (V) Output Voltage (V) VOUT = 1.2 V IOUT = 10 mA 1.28 5.06 5.04 5.02 5 4.98 4.96 +85°C +25°C -40°C 4.94 4.92 1.24 1.22 1.2 1.18 1.16 +85°C +25°C -40°C 1.14 1.12 1.1 4.9 0 20 40 60 80 100 120 140 160 180 Output Current (mA) 2 200 2.5 3 Figure 5. 5 5.5 VOUT = 5.0 V IOUT = 10 mA 5.08 2.86 5.06 Output Voltage (V) Output Voltage (V) 4.5 LINE REGULATION 5.1 VOUT = 2.8 V IOUT = 10 mA 2.88 3.5 4 Input Voltage (V) Figure 6. LINE REGULATION 2.9 2.84 2.82 2.8 2.78 2.76 +85°C +25°C -40°C 2.74 2.72 5.04 5.02 5 4.98 4.96 +85°C +25°C -40°C 4.94 4.92 2.7 4.9 3.1 3.7 4.3 Input Voltage (V) Figure 7. 6 200 Figure 4. LOAD REGULATION 5.1 80 100 120 140 160 180 Output Current (mA) Submit Documentation Feedback 4.9 5.5 5.3 5.35 5.4 Input Voltage (V) 5.45 5.5 Figure 8. Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. LINE REGULATION 1.3 LINE REGULATION 2.9 VOUT = 1.2 V IOUT = 150 mA 1.28 2.86 Output Voltage (V) 1.26 Output Voltage (V) VOUT = 2.8 V IOUT = 150 mA 2.88 1.24 1.22 1.2 1.18 1.16 +85°C +25°C -40°C 1.14 1.12 2.84 2.82 2.8 2.78 2.76 +85°C +25°C -40°C 2.74 2.72 1.1 2.7 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 3.1 3.7 Figure 9. 1.26 Output Voltage (V) Output Voltage (V) VOUT = 1.2 V 1.28 5.06 5.04 5.02 5 4.98 4.96 +85°C +25°C -40°C 4.94 4.92 1.24 1.22 1.2 1.18 1.16 1.14 IOUT = 10 mA IOUT = 150 mA 1.12 4.9 1.1 5.3 5.35 5.4 Input Voltage (V) 5.45 5.5 -40 -15 Figure 11. 60 85 OUTPUT VOLTAGE vs TEMPERATURE 5.1 VOUT = 2.8 V 2.88 10 35 Temperature (°C) Figure 12. OUTPUT VOLTAGE vs TEMPERATURE 2.9 VOUT = 5.0 V 5.08 5.06 Output Voltage (V) 2.86 Output Voltage (V) 5.5 OUTPUT VOLTAGE vs TEMPERATURE 1.3 VOUT = 5.0 V IOUT = 150 mA 5.08 4.9 Figure 10. LINE REGULATION 5.1 4.3 Input Voltage (V) 2.84 2.82 2.8 2.78 2.76 2.74 5.04 5.02 5 4.98 4.96 4.94 IOUT = 10 mA IOUT = 150 mA 2.72 2.7 -40 -15 10 35 Temperature (°C) Figure 13. Copyright © 2011, Texas Instruments Incorporated 60 85 IOUT = 10 mA IOUT = 150 mA 4.92 4.9 -40 -15 10 35 Temperature (°C) 60 85 Figure 14. Submit Documentation Feedback 7 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. DROPOUT VOLTAGE vs INPUT VOLTAGE DROPOUT VOLTAGE vs INPUT VOLTAGE 400 600 500 300 Dropout Voltage (mV) Dropout Voltage (mV) IOUT = 200 mA IOUT = 150 mA 350 250 200 150 100 +85°C +25°C -40°C 50 400 300 200 +85°C +25°C -40°C 100 0 0 2 2.5 3 3.5 4 Input Voltage (V) 4.5 2 5 2.5 3 Figure 15. DROPOUT VOLTAGE vs OUTPUT CURRENT VOUT = 2.8 V 300 250 250 Output Voltage (V) Output Voltage (V) 5 DROPOUT VOLTAGE vs OUTPUT CURRENT 350 300 200 150 100 +85°C +25°C -40°C 50 VOUT = 5.0 V 200 150 100 +85°C +25°C -40°C 50 0 0 0 20 40 60 80 100 120 140 160 180 Output Current (mA) 200 0 20 40 60 Figure 17. 200 GROUND PIN CURRENT vs INPUT VOLTAGE 35 VOUT = 1.2 V IOUT = 0 mA 30 Ground Pin Current (mA) 30 80 100 120 140 160 180 Output Current (mA) Figure 18. GROUND PIN CURRENT vs INPUT VOLTAGE 35 Ground Pin Current (mA) 4.5 Figure 16. 350 25 20 15 10 +85°C +25°C -40°C 5 VOUT = 2.8 V IOUT = 0 mA 25 20 15 10 +85°C +25°C -40°C 5 0 0 2 2.5 3 3.5 4 Input Voltage (V) Figure 19. 8 3.5 4 Input Voltage (V) Submit Documentation Feedback 4.5 5 5.5 3.1 3.7 4.3 Input Voltage (V) 4.9 5.5 Figure 20. Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. GROUND PIN CURRENT vs INPUT VOLTAGE 35 VOUT = 5.0 V IOUT = 0 mA 25 20 15 10 +85°C +25°C -40°C 5 VOUT = 1.2 V IOUT = 0 mA 35 Ground Pin Current (mA) 30 Ground Pin Current (mA) GROUND PIN CURRENT vs TEMPERATURE 40 30 25 20 15 10 5 0 0 5.3 5.35 5.4 Input Voltage (V) 5.45 5.5 -40 10 35 Temperature (°C) -15 Figure 21. VOUT = 2.8 V IOUT = 0 mA 30 25 20 15 10 VOUT = 5.0 V IOUT = 0 mA 35 Ground Pin Current (mA) Ground Pin Current (mA) GROUND PIN CURRENT vs TEMPERATURE 40 35 30 25 20 15 10 5 5 0 0 -40 10 35 Temperature (°C) -15 60 -40 85 10 35 Temperature (°C) -15 Figure 23. 60 85 Figure 24. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs OUTPUT CURRENT 1200 1200 1000 800 600 400 +85°C +25°C -40°C 200 0 VOUT = 2.8 V Ground Pin Current (mA) VOUT = 1.2 V Ground Pin Current (mA) 85 Figure 22. GROUND PIN CURRENT vs TEMPERATURE 40 60 1000 800 600 400 +85°C +25°C -40°C 200 0 0 20 40 60 80 100 120 140 160 180 Output Current (mA) Figure 25. Copyright © 2011, Texas Instruments Incorporated 200 0 20 40 60 80 100 120 140 160 180 Output Current (mA) 200 Figure 26. Submit Documentation Feedback 9 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. GROUND PIN CURRENT vs OUTPUT CURRENT SHUTDOWN CURRENT vs INPUT VOLTAGE 2 1200 1000 800 600 400 +85°C +25°C -40°C 200 VOUT = 1.2 V 1.8 Shutdown Current (mA) Ground Pin Current (mA) VOUT = 5 V 1.6 1.4 1.2 1 0.8 0.6 +85°C +25°C -40°C 0.4 0.2 0 0 0 20 40 60 80 100 120 140 160 180 Output Current (mA) 2 200 2.5 3 Figure 27. SHUTDOWN CURRENT vs INPUT VOLTAGE 5.5 1.4 1.2 1 0.8 0.6 +85°C +25°C -40°C 0.4 VOUT = 5.0 V 1.8 Shutdown Current (mA) 1.6 0.2 1.6 1.4 1.2 1 0.8 0.6 +85°C +25°C -40°C 0.4 0.2 0 0 2 2.5 3 3.5 4 Input Voltage (V) 4.5 5 5.5 2 2.5 3 Figure 29. 3.5 4 Input Voltage (V) 4.5 5 5.5 Figure 30. CURRENT LIMIT vs INPUT VOLTAGE CURRENT LIMIT vs INPUT VOLTAGE 450 450 VOUT = 1.2 V 425 425 400 400 Current Limit (mA) Current Limit (mA) 5 SHUTDOWN CURRENT vs INPUT VOLTAGE 2 VOUT = 2.8 V 1.8 375 350 325 VOUT = 2.8 V 375 350 325 300 300 +25°C -40°C 275 +25°C -40°C 275 250 250 2 2.5 3 3.5 4 Input Voltage (V) Figure 31. 10 4.5 Figure 28. 2 Shutdown Current (mA) 3.5 4 Input Voltage (V) Submit Documentation Feedback 4.5 5 5.5 3.1 3.7 4.3 Input Voltage (V) 4.9 5.5 Figure 32. Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. CURRENT LIMIT vs INPUT VOLTAGE POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 450 Current Limit (mA) 425 400 375 350 325 300 +25°C -40°C 275 Power-Supply Ripple Rejection (dB) 90 VOUT = 5.0 V 3.1 3.7 4.3 Input Voltage (V) 4.9 60 50 40 30 20 IOUT = 30 mA IOUT = 150 mA 10 5.5 10 100 1k 10k 100k Frequency (Hz) 10M 1M Figure 33. Figure 34. POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY 90 90 VOUT = 2.8 V 80 70 60 50 40 30 20 IOUT = 30 mA IOUT = 150 mA 10 0 10 100 1k 10k 100k Frequency (Hz) Power-Supply Ripple Rejection (dB) Power-Supply Ripple Rejection (dB) 70 0 250 VOUT = 5.0 V 80 70 60 50 40 30 20 IOUT = 30 mA IOUT = 150 mA 10 0 10M 1M 10 100 1k 10k 100k Frequency (Hz) 10M 1M Figure 35. Figure 36. POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE 70 60 50 40 30 20 10 VOUT = 2.8 V IOUT = 30 mA 1 kHz 1 MHz 0 Power-Supply Ripple Rejection (dB) 70 Power-Supply Ripple Rejection (dB) VOUT = 1.2 V 80 60 50 40 30 20 10 VOUT = 2.8 V IOUT = 150 mA 1 kHz 1 MHz 0 3.1 3.2 3.3 3.4 3.5 Input Voltage (V) Figure 37. Copyright © 2011, Texas Instruments Incorporated 3.6 3.7 3.8 3.1 3.2 3.3 3.4 3.5 Input Voltage (V) 3.6 3.7 3.8 Figure 38. Submit Documentation Feedback 11 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE POWER-SUPPLY RIPPLE REJECTION vs INPUT VOLTAGE 70 60 50 40 30 20 VOUT = 3.3 V IOUT = 30 mA 10 1 kHz 1 MHz Power-Supply Ripple Rejection (dB) Power-Supply Ripple Rejection (dB) 70 60 50 40 30 20 10 0 1 kHz 1 MHz 0 3.6 3.7 3.8 3.9 4.0 Input Voltage (V) 4.1 4.2 4.3 3.6 3.7 3.8 3.9 4.0 Input Voltage (V) Figure 40. OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY LOAD TRANSIENT RESPONSE 5V 2.8 V 1.2 V 10 100 mA/div 100 4.2 4.3 150 mA 50 mA IOUT 50 mV/div 1 0.1 VOUT 0.01 VOUT = 1.2 V 0.001 100 1k 10k 100k Frequency (Hz) 1M Time (100ms/div) 10M Figure 42. LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 150 mA 50 mV/div 1 mA IOUT VOUT 50 mA/div Figure 41. 200 mA/div 10 100 mA 50 mA Time (100 ms/div) Figure 43. Submit Documentation Feedback IOUT VOUT VOUT = 1.2 V 12 4.1 Figure 39. 50 mV/div Output Spectral Noise Density (mV/ÖHz) VOUT = 3.3 V IOUT = 150 mA VOUT = 2.8 V Time (100 ms/div) Figure 44. Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. IOUT VOUT 100 mA 50 mA 50 mV/div 1 mA 50 mA/div LOAD TRANSIENT RESPONSE 150 mA 50 mV/div 100 mA/div LOAD TRANSIENT RESPONSE VOUT VOUT = 2.8 V VOUT = 5 V Time (100ms/div) Time (100 ms/div) Figure 45. Figure 46. LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE VOUT = 1.2 V IOUT = 150 mA 1 mA IOUT 1 V/div 150 mA 100 mV/div 100 mA/div IOUT VIN 10 mV/div VOUT VOUT VOUT = 5 V Time (100 ms/div) Time (100 ms/div) Figure 47. Figure 48. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE 20 mV/div VOUT Time (100 ms/div) Figure 49. Copyright © 2011, Texas Instruments Incorporated 2 V/div VIN VOUT = 1.2 V IOUT = 150 mA VIN VOUT 20 mV/div 1 V/div VOUT = 1.2 V IOUT = 200 mA Time (100 ms/div) Figure 50. Submit Documentation Feedback 13 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE 20 mV/div VOUT 1 V/div VIN VOUT = 2.8 V IOUT = 150 mA VIN 10 mV/div 2 V/div VOUT = 1.2 V IOUT = 200 mA VOUT Time (100 ms/div) Time (100 ms/div) Figure 52. LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE 10 mV/div VIN VOUT 20 mV/div 1 V/div VOUT = 2.8 V IOUT = 200 mA 1 V/div Figure 51. VIN VOUT VOUT = 2.8 V IOUT = 150 mA Time (100 ms/div) Time (100 ms/div) Figure 53. Figure 54. LINE TRANSIENT RESPONSE VIN RAMP UP, RAMP DOWN RESPONSE 1 V/div VOUT = 1.2 V IOUT = 30 mA VIN 20 mV/div 2 V/div VIN VOUT VOUT = 2.8 V IOUT = 200 mA Time (100 ms/div) Figure 55. 14 VOUT Submit Documentation Feedback Time (100 ms/div) Figure 56. Copyright © 2011, Texas Instruments Incorporated TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At VIN = VOUT(TYP) + 0.5 V or 2.0 V (whichever is greater); IOUT = 10 mA, VEN = VIN, COUT = 1 μF, and TA = –40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. VIN RAMP UP, RAMP DOWN RESPONSE VOUT = 2.8 V IOUT = 30 mA VIN VOUT = 5 V IOUT = 30 mA 1 V/div 1 V/div VIN VIN RAMP UP, RAMP DOWN RESPONSE VOUT Time (100 ms/div) Figure 57. Copyright © 2011, Texas Instruments Incorporated VOUT Time (100 ms/div) Figure 58. Submit Documentation Feedback 15 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com APPLICATION INFORMATION GENERAL DESCRIPTION The TLV707 series (TLV707xx and TLV707xxP) belongs to a new family of next-generation value low-dropout regulators (LDOs). These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise and very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for portable RF applications. This family of regulators offers current limit and themal protection. The operating junction temperature of these devices is –40°C to +125°C. INPUT AND OUTPUT CAPACITOR REQUIREMENTS Generally, 1.0-µF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. However, the TLV707 is designed to be stable with an effective capacitance of 0.1 µF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-µF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications. NOTE: Using a 0.1-µF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions would be less than 0.1 µF. Maximum ESR should be less than 200 mΩ. Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1.0-μF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2-Ω, a 0.1-μF input capacitor may be necessary to ensure stability. 16 Submit Documentation Feedback BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE Input and output capacitors should be placed as close to the device pins as possible. To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR performance. INTERNAL CURRENT LIMIT The TLV707 internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT until thermal shutdown is triggered and the device turns off. As the device cools, it is turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information section for more details. The PMOS pass element in the TLV707 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. SHUTDOWN The enable pin (EN) is active high. The device is enabled when voltage at the EN pin goes above 0.9 V. This relatively lower voltage value required to turn on the LDO can also be used to power the device when it is connected to a GPIO of a newer processor, where the GPIO Logic 1 voltage level is lower than that of traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the IN pin. The TLV707xxP version has internal active pull-down circuitry that discharges the output with a time constant of: (120 · RL) t= · COUT (120 + RL) where: • • RL = Load resistance COUT = Output capacitor (1) Copyright © 2011, Texas Instruments Incorporated TLV707 Series www.ti.com DROPOUT VOLTAGE The TLV707 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout. This effect is shown in Figure 14 in the Typical Characteristics section. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over-/undershoot magnitude but increases the duration of the transient response. UNDERVOLTAGE LOCKOUT (UVLO) The TLV707 uses an undervoltage lockout circuit to keep the output shut off until internal circuitry is operating properly. THERMAL INFORMATION Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. Copyright © 2011, Texas Instruments Incorporated SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TLV707 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TLV707 into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Dissipation Ratings. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 2. PD = (VIN - VOUT) ´ IOUT (2) PACKAGE MOUNTING Solder pad footprint recommendations for the TLV707 are available from the Texas Instruments web site at www.ti.com. The recommended land pattern for the DQN (DFN-4) package is shown towards the end of this data sheet. Submit Documentation Feedback 17 TLV707 Series SBVS153B – FEBRUARY 2011 – REVISED OCTOBER 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2011) to Revision B Page • Deleted reference to DCK package from Features .............................................................................................................. 1 • Deleted DCK package pinout drawing .................................................................................................................................. 1 • Deleted DCK package from Thermal Information table ........................................................................................................ 2 • Deleted DCK package pinout drawing .................................................................................................................................. 5 • Deleted column for DCK package from Pin Descriptions table ............................................................................................ 5 • Deleted reference to DCK package from Package Mounting section. ............................................................................... 17 Changes from Original (February 2011) to Revision A Page • Added footnote to Features to show available voltage options ............................................................................................ 1 • Added preview banner over DCK pinout drawing ................................................................................................................. 1 • Added preview banner over DCK pinout drawing ................................................................................................................. 5 • Deleted two manually-inserted land pattern drawings ........................................................................................................ 17 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 31-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV70712PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70712PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70715PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70715PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV707185DQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV707185DQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70718DQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70718DQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70718PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70718PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70719PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70719PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70725PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70725PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV707285DQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV707285DQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV707285PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 31-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV707285PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70728PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70728PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70730DQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70730DQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70730PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70730PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70733PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70733PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70736PDQNR PREVIEW X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV70736PDQNT PREVIEW X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 31-Aug-2012 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV70712PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70712PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70712PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70712PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV707185DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV707185DQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV707185DQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70718DQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70718DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70718DQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70718DQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70718PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70718PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70719PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70719PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70719PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70719PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV707285DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2012 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TLV707285DQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV707285DQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV707285PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV707285PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV707285PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV707285PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70728PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70728PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70730DQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70730DQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70730PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70730PDQNR X2SON DQN 4 3000 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70730PDQNT X2SON DQN 4 250 180.0 8.4 1.16 1.16 0.63 4.0 8.0 Q2 TLV70730PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70733PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 TLV70733PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.63 4.0 8.0 Q2 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70712PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2012 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV70712PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70712PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV70712PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV707185DQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV707185DQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV707185DQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV70718DQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV70718DQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70718DQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV70718DQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70718PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70718PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70719PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70719PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV70719PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70719PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV707285DQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV707285DQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV707285DQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV707285PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV707285PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV707285PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV707285PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70728PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70728PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70730DQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70730DQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70730PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70730PDQNR X2SON DQN 4 3000 202.0 201.0 28.0 TLV70730PDQNT X2SON DQN 4 250 202.0 201.0 28.0 TLV70730PDQNT X2SON DQN 4 250 180.0 180.0 30.0 TLV70733PDQNR X2SON DQN 4 3000 180.0 180.0 30.0 TLV70733PDQNT X2SON DQN 4 250 180.0 180.0 30.0 Pack Materials-Page 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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