www.ti.com
SLLS553 – NOVEMBER 2002
D High Speed (>1000 Mbps) Upgrade for
DS90CP22 2x2 LVDS Crosspoint Switch
D LVPECL Crosspoint Switch Available in
SN65LVCP23
D Low-Jitter 1000-Mbps Fully Differential Data
Path
D 20 ps (Typ), 50 ps (Max), of Peak-to-Peak
Jitter With PRBS = 223–1 Pattern at 1000 Mbps
D Less Than 200 mW (Typ), 280 mW (Max) Total
Power Dissipation
D Balanced Output Impedance
D Output (Channel-to-Channel) Skew Is 10 ps
(Typ), 20 ps (Max)
D Configurable as 2:1 Mux, 1:2 Demux,
Repeater or 1:2 Signal Splitter
D Inputs Accept LVDS, LVPECL, and CML
Signals
D Fast Switch Time of 1.2 ns (Typ), 1.5 ns (Max)
D Fast Propagation Delay of 0.65 ns (Typ),
0.8 ns (Max)
D Receiver Input Threshold < ±50 mV
D 16 Lead SOIC and TSSOP Packages
D Inter-Operates With TIA/EIA–644–A LVDS
DESCRIPTION
The SN65LVCP22 is a 2x2 crosspoint switch providing
greater than 1000 Mbps operation for each path. The dual
channels incorporate wide common-mode (0 V to 4 V)
receivers, allowing for the receipt of LVDS, LVPECL, and
CML signals. The dual outputs are LVDS drivers to provide
low-power, low-EMI, high-speed operation. The
SN65LVCP22 provides a single device supporting 2:2
buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2
switching, and LVPECL/CML to LVDS level translation on
each channel. The flexible operation of the SN65LVCP22
provides a single device to support the redundant serial
bus transmission needs (working and protection switching
cards) of fault–tolerant switch systems found in optical
networking,
wireless
infrastructure,
and
data
communications systems. TI offers additional gigibit
repeater/translator and crosspoint products in the
SN65LVDS100 and SN65LVDS122.
The SN65LVCP22 uses a fully differential data path to
ensure low-noise generation, fast switching times, low
pulse width distortion, and low jitter. Output jitter is less
than 20 ps (typ), and 50 ps (max), to provide an eye that
is at least 95 % open at 1000 Mbps. Output channel-tochannel skew is less than 10 ps (typ) and 20 ps (max) to
ensure accurate alignment of outputs in all applications.
Both SOIC and TSSOP package options are available to
allow easy upgrade for existing solutions, and board area
savings where space is critical.
D or PW PACKAGE
(TOP VIEW)
Standard
D Operating Temperature: –40°C to 85°C
APPLICATIONS
D
D
D
D
D
D
Base stations
Add/Drop Muxes
Protection Switching for Serial Backplanes
Network Switches/Routers
Optical Networking Line Cards/Switches
SEL1
SEL0
IN0+
IN0–
VCC
IN1+
IN1–
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN0
EN1
OUT0+
OUT0–
GND
OUT1+
OUT1–
NC
NC – No internal connection
Clock Distribution
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!" ##$ %&#" "'$ !"($ %$)
'!$ %$($* $"+ '!!#"$"# %!"! !% "'$ $##!" !$ %$)
)!*+ $
! "& $" $$($ "'$ )'" " #'!)$ %#"&$ "'$$
%&#" ,"'&" "#$+
Copyright 2002, Texas Instruments Incorporated
PRODUCT PREVIEW
FEATURES
www.ti.com
SLLS553 – NOVEMBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE DESIGNATOR
PART NUMBER(1)
SYMBOLIZATION
SOIC
SN65LVCP22D
TBD
TSSOP
SN65LVCP22PW
TBD
(1) Add the syffix R for taped and reeled carrier
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
SOIC (D)
950 mW
DERATING FACTOR
ABOVE TA = 25°C
7.5 mW/°C
TA = 85°C
POWER RATING
494 mW
TSSOP (PW)
774 mW
6.2 mW/°C
402 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
PRODUCT PREVIEW
FUNCTION TABLE
SEL0
SEL1
OUT0
OUT1
FUNCTION
0
0
IN0
IN0
1:2 Splitter
0
1
IN0
IN1
Repeater
1
0
IN1
IN0
Switch
1
1
IN1
IN1
1:2 Splitter
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
INPUT AND OUTPUT SCHEMATICS TO BE INCLUDED AFTER DESIGN IS FINALIZED
2
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SLLS553 – NOVEMBER 2002
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNITS
Supply voltage(2) range, VCC
–0.5 V to 4 V
CMOS/TTL input voltage (ENO, EN1, SEL0, SEL1)
–0.5 V to 4 V
LVDS receiver input voltage (IN+, IN–)
–0.7 V to 4.3 V
LVDS driver output voltage (OUT+, OUT–)
–0.5 V to 4 V
LVDS output short circuit current
Continuous
Junction temperature
150°C
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Electrostatic discharge
Human body model(3)
Charged-device mode(4)
260°C
See Dissipation Rating Table
±8 kV
IN+, IN–, OUT+, OUT–,and GND
All pins
±2 kV
All pins
±500 V
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminals.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(4) Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
Supply voltage, VCC
3
3.3
MAX UNIT
3.6
V
Receiver input voltage
0
4
V
Operating free-air temperature, TA
–40
85
°C
Magnitude of differential input voltage |VID|
0.05
3
V
3
PRODUCT PREVIEW
Continuous power dissipation
www.ti.com
SLLS553 – NOVEMBER 2002
INPUT ELECTRICAL CHARACTERISTICS
over recommended operatingconditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN0, EN1, SEL0, SEL1)
VIH
VIL
High-level input voltage
2
Low-level input voltage
GND
IIH
IIL
High-level input current
Low-level input current
PRODUCT PREVIEW
VCL
Input clamp voltage
LVDS OUTPUT SPECIFICATIONS (OUT0, OUT1)
VIN = 3.6 V or 2.0 V, Vcc= 3.6 V
VIN = 0.0 V or 0.8 V, Vcc= 3.6 V
ICL = –18 mA
VCC
0.8
V
±7
±20
µA
±1
±10
µA
–0.8
–1.5
V
365
475
Differential output voltage
RL =75 Ω, See Figure 2
RL =75 Ω, VCC = 3.3V, TA = 25°C,
See Figure 2
270
VOD
285
365
440
VOD
Change in differential output voltage magnitude
between logic states
VID= ±100 mV, See Figure 2
–25
VOS
Steady-state offset voltage
Figure 3
1
∆VOS
Change in steady-state offset voltage between
logic states
Figure 3
–25
VOC(PP) Peak-to-peak common-mode output voltage
IOZ
High-impedance output current
Figure 3
1.2
50
VOUT = GND or VCC
VCC = 0 V, 1.5 V; VOUT = 3.6 V or GND
IOFF
IOS
Power-off leakage current
IOSB
CO
Both outputs short-circuit current
VOUT+ or VOUT– = 0 V
VOUT+ and VOUT– = 0 V
Differential output capacitance
VI = 0.4 sin(4E6πt) + 0.5 V
Output short-circuit current
25
–12
1.45
V
mV
mV
V
25
mV
150
mV
±1
µA
±1
µA
–24
mA
12
mA
pF
LVDS RECEIVER DC SPECIFICATIONS (IN0, IN1)
VTH
VTL
Positive-going differential input voltage threshold
See Figure 1 and Table 1
Negative-going differential input voltage threshold
See Figure 1 and Table 1
–50
50
VID = 100 mV, VCC = 3.0 V to 3.6 V
VIN = 4 V, VCC = 3.6 V or 0.0
0.05
mV
VID(HYS) Differential input voltage hysteresis
VCMR
Common-mode voltage range
IIN
Input current
CIN
Differential input capacitance
SUPPLY CURRENT
ICCD
Total supply current
ICCZ
3-state supply current
(1) All typical values are at 25°C and with a 3.3 V supply.
4
mV
mV
VIN = 0V, VCC = 3.6V or 0.0
VI = 0.4 sin (4E6πt) + 0.5 V
3.95
±1
±10
±1
±10
3
V
mA
pF
RL= 75 Ω, CL = 5 pF, 500 MHz
(1000 Mbps), EN0=EN1=High
60
85
mA
EN0 = EN1 = Low
25
40
mA
www.ti.com
SLLS553 – NOVEMBER 2002
SWITCHING CHARACTERISTICS
over recommended operatingconditions unless otherwise noted
TSET
THOLD
TEST CONDITIONS
MIN
TYP
Input to Sel setup time
Figure 7
0.7
0.5
Input to Sel hold time
Figure 7
1.0
0.5
MAX
UNIT
ns
ns
TSWITCH SEL to switched output
tPHZ
Disable time, high-level-to-high-impedance
Figure 7
1.2
1.5
ns
Figure 6
2
4.0
ns
tPLZ
tPZH
Disable time, low-level-to-high-impedance
Figure 6
2
4.0
ns
Enable time, high-impedance -to-high-level output
Figure 6
2
6.0
ns
tPZL
tLHT
Enable time, high-impedance-to-low-level output
Figure 6
2
6.0
ns
Differential output signal rise time (20%–80%)
200
450
ps
tHLT
Differential output signal fall time (20%–80%)
CL = 5 pF, Figure 5
CL = 5 pF, Figure 5
200
450
ps
10
30
ps
20
50
ps
VID = 300 mV, 50% duty cycle, VCM = 1.2 V
at 1000 Mbps, CL = 5 pF
0.5
1
psRMS
VCC = 3.3 V, TA = 25°C, CL = 5 pF,
See Figure 5
650
800
tJIT
LVDS data path peak
peak–to-peak
to peak jitter
TJrms
Added random jitter (rms)
tPLHD
Propagation
Pro
agation delay time, low
low-to-high-level
to high level out
output
ut
tPHLD
Propagation delay time, high-to-low-level output
tskew
Pulse skew (|tPLHD – tPHLD|)(1)
Output channel-to-channel skew {want this to
cover splitter mode, repeater, and switch
modes.}
tCCS
tsk(pp)
Part to part skew(2)
Part–to–part
VID = 300 mV, 50% duty cycle, VCM = 1.2 V
at 1000 Mbps (500 MHz), CL = 5 pF
VID = 300 mV, PRBS = 223–1 data pattern,
VCM = 1.2 V at 1000 Mbps, CL = 5 pF
ps
s
CL = 5 pF, Figure 5
VCC = 3.3 V, TA = 25°C, CL = 5 pF,
See Figure 5
550
650
800
550
650
800
ps
CL = 5 pF, Figure 5
CL = 5 pF, Figure 5
550
650
800
ps
550
0
20
ps
10
20
ps
CL = 5 pF, Figure 5
VCMR: 0.05 to 3.95 V
VCMR: 0.50 to 3.95 V
250
100
ps
(1) tskew is the magnitude of the time difference between the tPLHD and tPHLD of any output of a single device.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
PRODUCT PREVIEW
PARAMETER
www.ti.com
SLLS553 – NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
IIN+
OUT +
IN+
IN+ + IN–
VID
VIN+
VIC
IN–
VIN–
2
VOD
VOY
OUT –
VOUT++VOUT–
2
VOZ
IIN–
Figure 1. Voltage and Current Definitions
3.74 kΩ
Y
+
_
75 Ω
VOD
Z
0 V ≤ V(test) ≤ 2.4 V
3.74 kΩ
PRODUCT PREVIEW
Figure 2. Differential Output Voltage (VOD) Test Circuit
OUT+
IN+
IN+
≈1.4 V
IN–
≈1 V
37.4 Ω ±1%
VID
VOC(PP)
IN–
OUT–
1 pF VOS
37.4 Ω ±1%
VOS
VOC
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ±10 ns; RL = 100 Ω; CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.;the measurement of
VOC(PP) is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
OUT+
IN+
1 pF
VID
VIN+
IN–
VOUT+ VOD
OUT–
5 pF
VIN–
VOUT–
VIN+
1.4 V
VIN–
1V
0.4 V
0V
–0.4 V
VID
tPHLD
+VOD
–VOD
75 Ω
tPLHD
80%
20%
0V
Vdiff = (OUT+) – (OUT–)
tHLT
tLHT
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ .25 ns, pulse-repetition rate (PRR) = 0.5 Mpps, pulse
width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Timing Test Circuit and Waveforms
6
www.ti.com
SLLS553 – NOVEMBER 2002
37.4 Ω ±1%
OUT+
1 V or 1.4 V
VOUT+
1.2 V
37.4 Ω ±1%
OUT–
5 pF
1.2 V
VOUT–
EN
3V
1.5 V
0V
OUT
VOH
50%
1.2 V
tPHZ
tPZH
1.2 V
50%
VOL
OUT
tPLZ
tPZL
NOTE: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse-repetition rate (PRR) = 0.5 Mpps,
Pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
7
PRODUCT PREVIEW
EN
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SLLS553 – NOVEMBER 2002
IN0
IN1
SEL
tSET
tHOLD
OUT
IN0
IN1
tSWITCH
PRODUCT PREVIEW
EN
IN0
IN1
SEL
tSET
OUT
tHOLD
IN1
IN0
tSWITCH
EN
NOTE: tSET and tHOLD times specify that data must be in a stable state before and after mux control switches.
Figure 6. Input to Select for Both Rising and Falling Edge Setup and Hold Times
8
MECHANICAL DATA
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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Copyright 2002, Texas Instruments Incorporated