ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com DUAL DIGITAL ISOLATOR Check for Samples: ISO7221C-HT FEATURES 1 • • • • • • • • • • • APPLICATIONS • • Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Extreme (–55°C/175°C) Temperature Range (1) (2) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Texas Instruments high temperature products utilize highly optimized silicon (die) solutions with design and process enhancements to maximize performance over extended temperatures. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 • 1-, 5- and 25-Mbps Signaling Rate Options – Low Channel-to-Channel Output Skew; 1 ns max – Low Pulse-Width Distortion (PWD); 1 ns max – Low Jitter Content; 1 ns Typ at 150 Mbps 4000-Vpeak Isolation, 560 Vpeak VIORM – UL 1577 Approved – 50-kV/μs Typical Transient Immunity Operates with 3.3-V or 5-V Supplies 4-kV ESD Protection High Electromagnetic Immunity Down-Hole Drilling High Temperature Environments ISO7221C (1) (2) VCC1 1 OUTA INB 2 GND1 4 3 Isolation • SUPPORTS EXTREME TEMPERATURE APPLICATIONS 8 VCC2 7 INA OUTB GND2 6 5 Custom temperature ranges available. Device is qualified to ensure reliable operation for 1000 hours at maximum rated temperature. This includes, but is not limited to temperature bake, temperature cycle, electro migration, bond inter metallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. DESCRIPTION The ISO7221 is a dual-channel digital isolator. To facilitate PCB layout, the channels are oriented in the opposite directions. This device has a logic input and output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 V. Used in conjunction with isolated power supplies, this device blocks high voltage, isolates grounds, and prevents noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 μs, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. The small capacitance and resulting time constant provide fast operation with signaling rates available from 0 Mbps (dc) to 150 Mbps. (3) The A-, B- and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS VCC/2 input thresholds and do not have the input noise-filter and the additional propagation delay. (3) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com This device requires two supply voltages of 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3.3-V supply and all outputs are 4-mA CMOS. The ISO7221 is characterized for operation over the ambient temperature range of –55°C to 175°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SINGLE-CHANNEL FUNCTION DIAGRAM 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Galvanic Isolation Barrier DC Channel IN Filter OSC + PWM Vref Input + Filter Vref Pulse Width Demodulation Carrier Detect Data MUX AC Detect OUT Output Buffer AC Channel AVAILABLE OPTIONS (1) (1) (2) PRODUCT MAX SIGNALING RATE PACKAGE (2) INPUT THRESHOLD MARKED AS ORDERING NUMBER ISO7221C 25 Mbps SOIC-8 ≉ 1.5 V (TTL) (CMOS compatible) I7221H ISO7221CHD For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. REGULATORY INFORMATION UL Recognized under 1577 Component Recognition Program (1) File Number: E181974 (1) Production tested ≥3000 VRMS for 1 second in accordance with UL 1577. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT VCC Supply voltage (2), VCC1, VCC2 –0.5 to 6 V VI Voltage at IN, OUT –0.5 to 6 V IO Output current ±15 mA Human Body Model Electrostatic discharge JEDEC Standard 22, Test Method A114-C.01 Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 Machine Model ANSI/ESDS5.2-1996 ESD Electrostatic discharge TJ Maximum junction temperature (1) (2) 2 ±4 All pins kV ±1 ±200 V 180 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage (1), VCC1, VCC2 IOH High-level output current IOL Low-level output current TYP MAX 3 UNIT 5.5 V 4 mA –4 (2) mA tui Input pulse width 40 33 1/tui Signaling rate (2) 0 30 VIH High-level input voltage 2 VIL Low-level input voltage 0 0.8 V TA Operating temperature –55 175 °C (2) Mbps VCC 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 (1) ns 25 V For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. Typical signaling rate and Input pulse width are measured at ideal conditions at 25°C. ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 25 Mbps VI = VCC or 0 V, no load 12 22 ICC2 25 Mbps VI = VCC or 0 V, no load 12 22 VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IN from 0 V to VCC IIL Low-level input current IN from 0 V to VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) IOH = –4 mA, See Figure 1 VCC – 0.8 4.6 IOH = –20 μA, See Figure 1 VCC – 0.1 5 mA V IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 μA, See Figure 1 0 0.1 V 150 mV μA 11 –11 25 μA 1 pF 50 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 21 32 43 UNIT 1 2 ns 10 ns tpLH, tpHL Propagation delay See Figure 1 PWD Pulse-width distortion |tpHL – tpLH| (1) See Figure 1 tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 tf Output signal fall time See Figure 1 1 ns tfs Failsafe output delay time from input power loss See Figure 2 3 μs (1) (2) (3) (2) (3) 0.2 5 1 ns ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT 3 ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 25 Mbps VI = VCC or 0 V, no load 12 22 mA ICC2 25 Mbps VI = VCC or 0 V, no load 6 12 mA VOH High-level output voltage VOL Low-level output voltage (5-V side) IOH = –4 mA, See Figure 1 VCC – 0.8 IOH = –20 μA, See Figure 1 VCC – 0.1 0.4 IOL = 20 μA, See Figure 1 0.1 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 IOL = 4 mA, See Figure 1 VI(HYS) Input voltage hysteresis IIH High-level input current IN from 0 V to VCC IIL Low-level input current IN from 0 V to VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) V 150 mV 11 –11 15 V μA μA 1 pF 40 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL TEST CONDITIONS Propagation delay MIN TYP MAX 24 36 49 (1) UNIT ns PWD Pulse-width distortion |tpHL – tpLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 tf Output signal fall time See Figure 1 2 ns tfs Failsafe output delay time from input power loss See Figure 2 3 μs (1) (2) (3) 1 (2) (3) 0.2 2 ns 10 ns 10 2 ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 25 Mbps VI = VCC or 0 V, no load 6 12 mA ICC2 25 Mbps VI = VCC or 0 V, no load 12 22 mA VOH High-level output voltage VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IN from 0 V or VCC IIL Low-level input current IN from 0 V or VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 4 (3.3-V side) IOH = –4 mA, See Figure 1 VCC – 0.4 IOH = –20 μA, See Figure 1 VCC – 0.1 IOL = 4 mA, See Figure 1 IOL = 20 μA, See Figure 1 0 V 0.4 0.1 150 mV 11 –11 15 μA μA 1 pF 40 kV/μs For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL TEST CONDITIONS Propagation delay Pulse-width distortion |tpHL – tpLH| tsk(pp) Part-to-part skew tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss MAX 24 36 49 1 (2) (3) 0.2 UNIT ns 3 ns 10 ns 10 ns 1 See Figure 1 1 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 (3) TYP (1) PWD (1) (2) MIN See Figure 2 μs 3 Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ICC1 25 Mbps VI = VCC or 0 V, no load 6 12 mA ICC2 25 Mbps VI = VCC or 0 V, no load 6 12 mA VOH High-level output voltage VOL Low-level output voltage IOH = –4 mA, See Figure 1 VCC – 0.4 3 IOH = –20 μA, See Figure 1 VCC – 0.1 3.3 IOL = 4 mA, See Figure 1 0.2 0.4 IOL = 20 μA, See Figure 1 0 0.1 VI(HYS) Input voltage hysteresis IIH High-level input current IN from 0 V or VCC IIL Low-level input current IN from 0 V or VCC CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) V 150 V mV 11 μA –11 1 pF 15 40 kV/μs MIN TYP MAX 256 40 53 ns 3 ns 10 ns For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3 V over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL TEST CONDITIONS Propagation delay (1) UNIT PWD Pulse-width distortion |tpHL – tpLH| tsk(pp) Part-to-part skew (2) tsk(o) Channel-to-channel output skew tr Output signal rise time See Figure 1 2 tf Output signal fall time See Figure 1 2 ns tfs Failsafe output delay time from input power loss See Figure 2 3 μs (1) (2) (3) (3) 1 0.2 5 ns ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT 5 ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC1 VI VCC1/2 VCC1/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50Ω. B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 A. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI 0V or VCC1 A. ISOLATION BARRIER VCC1 IN VCC1 OUT VI 2.7 V VO 0V VOH tfs CL NOTE A VO 50% FAILSAFE HIGH VOL CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 S1 ISOLATION BARRIER C = 0.1 mF± 1% IN GND1 C = 0.1 mF± 1% Pass-fail criteria: Output must remain stable OUT NOTE A VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit DUT Tektronix HFS9009 VCC1 IN OUT Tektronix 784D PATTERN GENERATOR 0V VCC/2 Jitter NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com DEVICE INFORMATION DEVICE I/O SCHEMATICS Input VCC1 VCC1 Output VCC2 VCC1 750 kW 8W 500 W 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 IN OUT 13 W SOIC-8 PACKAGE THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Low-K Thermal Resistance θJA Junction-to-air θJB Junction-to-Board Thermal Resistance θJC Junction-to-Case Thermal Resistance (1) MIN (1) TYP MAX UNIT 212 High-K Thermal Resistance 122 37 °C/W 69.1 Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. DEVICE FUNCTION TABLE Table 1. Function Table (1) INPUT SIDE VCC (1) OUTPUT SIDE VCC PU PU PD PU INPUT IN OUTPUT OUT H H L L Open H X H PU = Powered Up(Vcc ≥ 3.0V); PD = Powered Down (Vcc ≤ 2.5V); X = Irrelevant; H = High Level; L = Low Level Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT 7 ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTIC CURVES 3.3-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 5-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 20 30 TA = 25°C, 15 pF Load 18 26 ISO7220x ICC2 24 14 ICC - Supply Current - mA 16 ISO7220x ICC2 12 10 ISO7221x ICC1&2 8 6 4 22 20 18 16 14 12 10 4 2 0 0 0 25 50 75 ISO7220x ICC1 8 6 ISO7220x ICC1 2 ISO7221x ICC1&2 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 ICC - Supply Current - mA TA = 25°C, 15 pF Load 28 100 0 25 Signaling Rate - Mbps 50 50 75 Signaling Rate - Mbps 100 Figure 5. Figure 6. PROPAGATION DELAY vs FREE-AIR TEMPERATURE INPUT VOLTAGE LOW-TO-HIGH SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE 1.45 5-V Vth+ VCC = 3.3 V 1.4 45 tpLH & tpHL 40 35 30 VCC = 5 V tpLH & tpHL 25 Input Voltage Threshold - V Propagation Delay - ns 1.35 3.3-V Vth+ 1.3 1.25 1.2 15 pF Load 5-V Vth- 1.15 1.1 3.3-V Vth- 1.05 20 -55 -40 25 125 175 1 -60 Temperature - °C 40 90 140 190 Temperature - °C Figure 7. 8 -10 Figure 8. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com TYPICAL CHARACTERISTIC CURVES (continued) VCC FAILSAFE THRESHOLD vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 2.75 -80 15 pF Load VCC = 3.3 V or 5 V 2.7 VFS -60 VCC = 5 V 2.65 -50 IOUT - mA 2.6 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Failsafe Threshold - V 15 pF Load TA = 25°C -70 VFS- -40 -30 2.55 VCC = 3.3 V -20 2.5 -10 2.45 -60 0 -10 40 90 140 0 190 2 4 6 VOUT - V Temperature - °C Figure 9. Figure 10. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 70 15 pF Load TA = 25°C 60 VCC = 5 V IOUT - mA 50 40 VCC = 3.3 V 30 20 10 0 0 1 2 3 4 5 VOUT - V Figure 11. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT 9 ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com APPLICATION INFORMATION V CC 1 V CC 2 0.1mF OUTPUT 2 mm max . from Vcc 1 1 OUTA 2 INB INPUT 0.1mF INPUT OUTPUT 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 3 4 8 INA 7 OUTB 6 5 2 mm max . from Vcc 2 ISO 7221 GND 1 GND 2 Figure 12. Typical ISO7221 Application Circuit 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com ISOLATION GLOSSARY Creepage Distance — The shortest path between two conductive input to output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Clearance — The shortest distance between two conductive input to output leads measured through air (line of sight). Input-to Output Barrier Capacitance — The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to Output Barrier Resistance — The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit — An internal circuit directly connected to an external supply mains or other equivalent source which supplies the primary circuit electric power. Secondary Circuit — A circuit with no direct connection to primary power, and derives its power from a separate isolated source. Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials which is defined as the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT 11 ISO7221C-HT SLLSE78 – APRIL 2011 www.ti.com Insulation: Operational insulation — Insulation needed for the correct operation of the equipment. Basic insulation — Insulation to provide basic protection against electric shock. Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Double insulation — Insulation comprising both basic and supplementary insulation. Reinforced insulation — A single insulation system which provides a degree of protection against electric shock equivalent to double insulation. 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 Pollution Degree: Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence. Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation must be expected. Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs which becomes conductive due to condensation which is to be expected. Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions. Installation Category: Overvoltage Category — This section is directed at insulation co-ordination by identifying the transient overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664. I: Signal Level — Special equipment or parts of equipment. II: Local Level — Portable equipment etc. III: Distribution Level — Fixed installation IV: Primary Supply Level — Overhead lines, cable systems Each category should be subject to smaller transients than the category above. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :ISO7221C-HT PACKAGE OPTION ADDENDUM www.ti.com 20-Feb-2012 司 公 限 有 2 件 技 83 器 科 16 元 子 29 子 电 -8 电 创 55 温 德 07 高 鸿 话 油 圳 电 石 深 系 理 联 代 业 专 PACKAGING INFORMATION Orderable Device ISO7221CHD Status (1) ACTIVE (1) Package Type Package Drawing SOIC D Pins Package Qty 8 75 Eco Plan TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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