STMICROELECTRONICS ST72682R21

ST72682
USB 2.0 high-speed Flash drive controller
Features
■
■
USB 2.0 interface compatible with mass
storage device class
– Integrated USB 2.0 PHY
– Supports USB high speed and full speed
– Suspend and Resume operations
Mass storage controller interface (MSCI)
– Supports all types of NAND Flash devices
including ST, Hynix, Samsung, Toshiba,
Renesas, and Micron
– Reed-Solomon encoder/decoder: on-thefly correction (4 bytes of a 512-byte block)
– Flash identification support
– Up to 21 Mbyte/s for read and 11 Mbyte/s
for write operations in dual channel
■
Embedded ST7 8-bit MCU
■
Supply management
– 3.3V operation
– Integrated 3.3 -1.8 V voltage regulator
■
USB 2.0 low-power device compliant
– Less than 100 mA during write operation
with two NAND Flash devices
– Less than 500 µA in suspend mode
■
LQFP64 10x10
Clock management
– Integrated PLL for generating core and
USB 2.0 clock sources using external
12 MHz crystal
Table 1.
■
AutoRun CDROM partition support
■
Data protection
– Write protect switch control
– Public/Private partitions support
■
Bootability support (HDD mode)
■
Production tool device configurability:
– USB vendor ID/product ID (VID/PID), serial
number and USB strings with foreign
language support
– SCSI strings
– One or two LED outputs
– Adjustable NAND Flash bus frequency to
reach highest performance
■
Code update in the NAND Flash
■
LQFP64 10x10 lead-free package
■
Development support
– Complete reference design including
schematics, BOM and gerber files
■
Supports Windows (Vista, XP, 2000, ME),
Linux and MacOS. Drivers available for
Windows 98 SE
Device summary
Orderable part numbers
Features
ST72682/R20
USB interface
ST72682/R21
USB 2.0 high speed
Number of NAND devices supported
up to 8
Read/write speed
21MBps/11MBps
Operating supply
3.0 to 3.6 V
Operating Temperature
0°C to +70°C
Package
LQFP64 10x10 / die form
August 2007
Rev 2
1/36
www.st.com
1
Contents
ST72682
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
NAND Flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
5
Hardware error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1.2
Firmware error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.1
Bad Block identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.2
Bad block replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2.3
Late Fail block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Wear levelling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4
NAND Flash interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mass storage implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1
USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2
BOT/SCSI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
2/36
4.1.1
4.3
5.3
6
NAND Flash error correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1
BOT specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.2
SCSI specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.3
Bootability specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multi-LUN device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1
Public drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.2
Private drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.3
Additional drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.4
CD-ROM considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mass storage interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Human interface implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
LED behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Read-only switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ST72682
7
Contents
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5.1
7.6
7.7
7.8
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.6.1
Functional EMS (Electromagnetic Susceptibility) . . . . . . . . . . . . . . . . . 23
7.6.2
Electromagnetic Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.6.3
Absolute Maximum Ratings (Electrical Sensitivity) . . . . . . . . . . . . . . . . 24
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7.1
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7.2
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.8.1
7.9
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Other communication interface characteristics . . . . . . . . . . . . . . . . . . . . 30
7.9.1
MSCI parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.9.2
USB (Universal Bus Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3/36
List of tables
ST72682
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/36
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Control and system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
USB 2.0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
USB 2.0 and core clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
General Purpose I/O ports / Mass Storage I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Known NAND Flash memory compatibility guide for ST72682/R20 and ST72682/R21. . . 12
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RUN and SUSPEND modes current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply and Clock managers current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical CL and RS values by crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MSCI parallel interface DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
USB Interface DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB Interface AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB high speed transmit waveform requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
64-pin Thin Quad Flat Package (10 x10) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . 33
Feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ST72682
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
64-pin LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock frequency versus supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Typical application with a crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical VIL and VIH standard I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical RPU vs. VDD33 with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical VOL at VDD33=3.3 V (I/O D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Typical VOL at VDD33=3.3 V (I/O D4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Typical VOL at VDD33=3.3 V (I/O D8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical VDD33-VOH vs. VDD33 (I/O D2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical VDD33-VOH vs. VDD33 (I/O D4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical VDD33-VOH vs. VDD33 (I/O D8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical RON on RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timing diagrams for input mode (with max load on CTRL signal = 50 pf) . . . . . . . . . . . . . 30
Timing diagrams for output mode (with max CTRL signal = 50 pf, DATA) . . . . . . . . . . . . . 30
USB signal eye diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
64-pin Thin Quad Flat Package (10 x10) package outline . . . . . . . . . . . . . . . . . . . . . . . . . 33
5/36
Introduction
1
ST72682
Introduction
The ST72682 is a USB 2.0 high-speed Flash drive controller. The USB 2.0 high-speed
interface includes PHY and function and supports USB 2.0 mass storage device class.
The Mass storage controller interface (MSCI), combined with the Reed-Solomon
encoder/decoder on-the-fly correction (4 bytes on 512-byte data blocks), provides a flexible
high transfer rate solution for interfacing a wide of range NAND Flash memory devices.
The internal 60 MHz PLL driven by the 12 MHz oscillator is used to generate the 480 MHz
frequency required for the USB 2.0 PHY.
The ST7 8-bit CPU runs the application program from the internal ROM and RAM. USB data
and patch code are stored in internal RAM.
The I/O ports provide allow to connect EEPROM, LEDs and a write protect switch control.
The internal 3.3 to 1.8 V voltage regulator provides the 1.8 V supply voltage to the digital
part of the circuit.
Figure 1.
Device block diagram
12 MHz
OSC
8-bit
CPU
USB 2.0 USB 2.0
Function
PHY
3.3 V to 1.8 V
voltage
regulator
6/36
ROM
RAM
Mass
ReedStorage Solomon
Controller
Error
Interface Correction
GPIO
NAND
I/F
ST72682
Pin description
Figure 2 shows the LQPF64 package pinout, while Table 2, Table 3, Table 4, Table 5, and
Table 6 give the pin description.
The legend and abbreviations used in these tables are the following:
●
Type
–
I = input
–
O = output
–
S = supply
●
Input level: A = Dedicated analog input
●
In/Output level
●
–
CT = CMOS 0.3VDD/0.7VDD with input trigger
–
TT= TTL 0.8V / 2V with Schmitt trigger
Output level
–
D8 = 8mA drive
–
D4 = 4mA drive
–
D2 = 2mA drive
64-pin LQFP package pinout
VSS_1
VDD33_1
NC*
NAND D[14]
NAND D[15]
NAND D[0]
NAND D[1]
NAND D[2]
NAND D[3]
NAND D[4]
VSS_5
VDD33_5
NAND D[5]
NAND D[6]
NAND D[7]
NAND RnB
Figure 2.
NAND D[13]
NAND D[12]
NAND D[11]
NAND D[10]
VDDA
OSCIN
OSCOUT
VSSA
RREF
VSSC
VDDC
VDD3
USBDP
USBDM
VSSBL
VDDBL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ST72682
NAND WP
READ ONLY
NC(1)
VSS_2
VDD33_2
NC(1)
NC(1)
RESET
NC(1)
NC(1)
NC(1)
LED2
LED1
PE4
NAND ALE
VSS_3
VDDOUSB
VSS_4
VDD33_4
NAND D[9]
NAND D[8]
NAND CE4
NAND CE3
NAND CE2
NAND CE1
NAND RE
NAND WE
NAND CLE
NC(1)
NC(1)
NC(1)
VDD33_3
2
Pin description
1. Must remain NOT connected in the application.
7/36
Pin description
ST72682
Power supply pins
Pin
Pin name
LQFP64
64
VSS_1
63
VDD33_1
45
VSS_2
44
VDD33_2
33
VSS_3
32
VDD33_3
18
VSS_4
19
VDD33_4
54
VSS_5
53
VDD33_5
17
VDDOUSB
Description
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
S Ground
S I/Os and regulator supply voltage
O USB2 PHY, OSC and PLL power supply output (1.8V)
Control and system
41
Table 4.
RESET
I/O 3.3 CT
Description
Reset input with filter with internal pull-up
USB 2.0 Interface
Pin name
Type
Pin
16
VDDBL
S
Supply voltage for buffers and deserialisation flip flops (1.8 V)
15
VSSBL
S
Ground for buffers and deserialisation flip flops (1.8 V)
14
USBDM
I/O USB2 DATA -
13
USBDP
I/O USB2 DATA +
12
VDD3
S
Supply voltage for the FS compliance (3.3 V)
11
VDDC
S
Supply voltage for DLL & XOR tree (1.8 V)
10
VSSC
S
Ground for DLL & XOR tree (1.8 V)
9
RREF
I/O
LQFP64
8/36
Output
Pin name
LQFP64
Power
Level
Type
Pin
Input
Table 3.
Type
Table 2.
Description
Ref. resistor for integrated impedance process adaptation
(11.3 kOhms 1% Pull Down)
ST72682
Pin description
USB 2.0 and core clock system
Pin
Pin name
LQFP64
Type
Table 5.
Description
8
VSSA
7
OSCOUT
6
OSCIN
I
5
VDDA
S Supply voltage for oscillator & PLL (1.8 V)
Table 6.
S Ground for oscillator & PLL (1.8 V)
O 12MHz oscillator output
12MHz oscillator input
General Purpose I/O ports / Mass Storage I/Os
Level
Input
Outputs
Main
function
(after reset)
Pin name
Type
Pin
59
NAND D[0]
I/O
TT
D4 NAND data [0]
58
NAND D[1]
I/O
TT
D4 NAND data [1]
57
NAND D[2]
I/O
TT
D4 NAND data [2]
56
NAND D[3]
I/O
TT
D4 NAND data [3]
55
NAND D[4]
I/O
TT
D4 NAND data [4]
52
NAND D[5]
I/O
TT
D4 NAND data [5]
51
NAND D[6]
I/O
TT
D4 NAND data [6]
50
NAND D[7]
I/O
TT
D4 NAND data [7]
21
NAND D[8]
I/O
TT
D4 NAND data [8]
20
NAND D[9]
I/O
TT
D4 NAND data [9]
10
NAND D[10]
I/O
TT
D4 NAND data [10]
11
NAND D[11]
I/O
TT
D4 NAND data [11]
12
NAND D[12]
I/O
TT
D4 NAND data [12]
13
NAND D[13]
I/O
TT
D4 NAND data [13]
14
NAND D[14]
I/O
TT
D4 NAND data [14]
15
NAND D[14]
I/O
TT
D4 NAND data [15]
34
NAND ALE
I/O
TT
D8 NAND address latch enable
35
PE4
I/O
TT
D2
28
NAND CLE
O
TT
D8 NAND command latch enable
27
NAND WE
O
TT
D8 NAND write enable
26
NAND RE
O
TT
D8 NAND read enable
25
NAND CE1
O
TT
D4 NAND enable 1
24
NAND CE2
O
TT
D4 NAND enable 2
23
NAND CE3
O
TT
D4 NAND enable 3
LQFP64
9/36
Pin description
ST72682
Table 6.
General Purpose I/O ports / Mass Storage I/Os (continued)
Level
Input
Outputs
22
NAND CE4
O
TT
D4 NAND enable 4
49
NAND RnB
I
TT
D2 NAND Ready/Busy
48
NAND WP
O
TT
D2 NAND Write Protect
47
READ ONLY
I
TT
D2 Read-only switch (“0”: Read/Write; “1”: Read only)
EEPROM SCL
O
TT
D2 EEPROM serial clock
37
LED2
O
TT
D8 Green LED (USB access)
36
LED1
O
TT
D8 Red LED (NAND access)
LQFP64
10/36
Main
function
(after reset)
Pin name
Type
Pin
C12
18pF
510
R6
USB CON
GND
D+
DVBUS
J1
XT1
1
2
4
3
2
1
USB_V5
V33
DP
DM
C13
18pF
C3
10nF
V18_USB
100nF
1uF
V18_USB
12MHz_NX4025DA
3
4
V18_USB
C10
C4
USB_V5
D[15..8]
2
NAND D[13]
NAND D[12]
NAND D[11]
NAND D[10]
VDDA
OSCI N
OSCOUT
VSSA
RREF
VSSC
VDDC
VDD3
USBDP
USBDM
VSSBL
VDDBL
C5
470nF
4
5
V33
LD3985M33R_SOT235L
R5
11.3K 1%
D9
D8
Vout
Vout
AME8800_SOT23
INHI BI T BYPASS
GND
Vin
1
2
3
4
5
OSCIN 6
OCSOUT 7
8
9
RREF
10
11
12
13
14
15
16
D13
D12
D11
D10
3
2
1
U1a
1
GND
C1
10nF
+ C6
4.7uF
V33
V33
C7
220nF
ST72682_QF
P64
NAND WP
READ ONL Y
NC
VSS_2
VDD33_2
NC
NC
RESET
NC
NC
NC
LED2
LED1
NC
NAND AL E
VSS_3
V33
V33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
U4
C9
100nF
D[7..0]
C8
100nF
C2
10nF
NAND_AL E
LED2
LED1
RESET
V33
C11
100nF
Read Only
S1
NAND_WP
RO
R1
330
LED1
RED L ED
V33
R2
330
NAND_RnB
NAND_WP
R4
10K
NAND_RnB
NAND_WP
NAND_WP
LED2
GREENL ED
R_T
0
R_Toshiba_config
GND/NAND_RnB2
R_SW
0
R_Samsung W_config
NAND_RnB
R3
4.7K
V33
LED1
Vin
NAND_WP
NAND_CE3
NAND_CE4
NAND_CL E
NAND_AL E
NAND_WE
NAND_WP
V33
NAND_CE3
NAND_CE4
NAND_CL E
NAND_AL E
NAND_WE
NAND_WP
NAND_RnB
NAND_RnB
GND/NAND_RnB2
NAND_RnB
NAND_RE
NAND_CE1
NAND_CE2
V33
NAND_RnB
NAND_RnB
GND/NAND_RnB2
NAND_RnB
NAND_RE
NAND_CE1
NAND_CE2
NAND_WP
NAND_FLASH_TSOP 48
NC/#RES
NC
NC
NC
NC
NC
NC/#RB4
NC
NC/#RB3
I/O 7
GND/#RB2/NC I/O 6
#RB/#RB1
I/O 5
#RE
I/O 4
#CE/#CE1
NC
NC/#CE2
NC
NC
NC/PRE
VCC
VCC
VSS
VSS
NC/#CE3
NC
NC/#CE4
NC
CL E
NC
AL E
I/O 3
#WE
I/O 2
#WP
I/O 1
NC
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
U2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D3
D2
D1
D0
D7
D6
D5
D4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NAND_FLASH_TSOP 48
NC/#RES
NC
NC
NC
NC
NC
NC/#RB4
NC
NC/#RB3
I/O 7
GND/#RB2/NC I/O 6
#RB/#RB1
I/O 5
#RE
I/O 4
#CE/#CE1
NC
NC/#CE2
NC
NC
NC/PRE
VCC
VCC
VSS
VSS
NC/#CE3
NC
NC/#CE4
NC
CL E
NC
AL E
I/O 3
#WE
I/O 2
#WP
I/O 1
NC
I/O 0
NC
NC
NC
NC
NC
NC
NC
NC
U3
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D11
D10
D9
D8
D15
D14
D13
D12
On Board Flash2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
On Board Flash1
V33
V33
D[7..0]
D[15..8]
U1b
D14
D15
D0
D1
D2
D3
D4
3
D5
D6
D7
NAND_RnB
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NAND_CE4
NAND_CE3
NAND_CE2
NAND_CE1
NAND_RE
NAND_WE
NAND_CLE
Application schematic
VSS_1
VDD33_1
NC
NAND D[14]
NAND D[15]
NAND D[0]
NAND D[1]
NAND D[2]
NAND D[3]
NAND D[4]
VSS_5
VDD33_5
NAND D[5]
NAND D[6]
NAND D[7]
NAND RnB
Figure 3.
VDDOUSB
VSS_4
VDD33_4
NAND D[9]
NAND D[8]
NAND CE4
NAND CE3
NAND CE2
NAND CE1
NAND RE
NAND WE
NAND CLE
NC
NC
NC
VDD33_3
Application schematics
LED2
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
ST72682
Application schematics
11/36
NAND Flash memory interface
4
ST72682
NAND Flash memory interface
Table 7 gives the list of NAND Flash memory devices compatible with ST72682/R20 and
ST72682/R21 devices. This list is only provided as a guide as it is not possible to
automatically guarantee support for all the additions and updates across the listed ranges of
manufacturers’ devices.
Table 7.
Known NAND Flash memory compatibility guide for ST72682/R20 and ST72682/R21
NAND Flash part number
NAND Flash size (Mbytes or
Gbytes) and type
Number of NAND Flash devices supported
ST72682/R20 device
ST72682/R21 device
Samsung K9F1G08U
128 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9F2G08U
256 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9F4G08U
512 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9K4G08U
512 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9W4G08U
512 MB; SLC2K; Dual CE
2 or 4
1, 2 or 4
Samsung K9K8G08U
1 GB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9W8G08U
1 GB; SLC2K; Dual CE
2 or 4
1, 2 or 4
Samsung K9WAG08U
2 GB; SLC2K; Dual CE
2 or 4
1, 2 or 4
Samsung K9NBG08U
4 GB; SLC2K; Quad CE
2
1 or 2
Samsung K9G4G08U
512 MB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9L8G08U
1 GB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Samsung K9HAG08U
2 GB; MLC2K; Dual CE
2 or 4
1, 2 or 4
Samsung K9MBG08U
4 GB; MLC2K; Quad CE
2
1 or 2
Toshiba TH58NVG0S3
128 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Toshiba TH58NVG1S3
256 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Toshiba TH58NVG2S3
512 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Toshiba TH58NVG1D4
256 MB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Toshiba TH58NVG2D4
512 MB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Toshiba TH58NVG3D4
1 GB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
ST NAND01GW3B
128 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
ST NAND02GW3B
256 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
ST NAND04GW3B
512 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
ST NAND08GW3B
1 GB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
ST NAND04GW3C
512 MB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Hynix HY27UF081G2M
128 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Hynix HY27UG082G2M
256 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Hynix HY27UG084G2M
512 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Hynix HY27UH084G5M
512 MB; SLC2K; Dual CE
2 or 4
1, 2 or 4
12/36
ST72682
Table 7.
NAND Flash memory interface
Known NAND Flash memory compatibility guide for ST72682/R20 and ST72682/R21
NAND Flash part number
NAND Flash size (Mbytes or
Gbytes) and type
Number of NAND Flash devices supported
ST72682/R20 device
ST72682/R21 device
Hynix HY27UH088G2M
1 GB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Hynix HY27UT084G2M
512 MB; MLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Hynix HY27UU088G5M
1 GB; MLC2K; Dual CE
2 or 4
1, 2 or 4
Micron 29F2G08AA
256 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Micron 29F4G08BA
512 MB; SLC2K; Single CE
1, 2, 4, 6 or 8
1, 2, 4, 6 or 8
Micron 29F8G08FA
1 GB; SLC2K; Dual CE
2 or 4
1, 2 or 4
4.1
NAND Flash error correction
No NAND Flash memory arrays are guaranteed by manufacturers to be error-free. Error
occurrence depends on the Flash cell type (MLC or SLC).
The ST72682 embeds hardware and firmware mechanisms to correct the errors.
4.1.1
Hardware error correction
The ST72682 embeds a Reed-Solomon algorithm-based hardware cell. This cell directly
manages 512-byte data packets on the NAND I/O system.
Based on the data packet content, the cell generates an 80-bit Error Correction Code (ECC)
consisting of 8 words, each containing 10 bits.
During write operations to NAND memory, the 512-bytes of data and the ECC are stored
together in the same page. The ECC is stored in the corresponding Redundant Area (RA),
using 10 bytes.
During read operations, the 512-bytes of data and the 8 ECC words are read back and are
passed through the Reed-Solomon cell for decoding. The cell allows the correction of 4
symbols in this 520-symbol packet (512 symbols from data + 8 symbols from ECC).
The hardware cell gives three possible results:
4.1.2
■
No error detected: the data packet can be used as it is.
■
Correctable error detected: the corrected data are available in a specific 512-byte buffer
in the Reed-Solomon cell and are ready to be used.
■
Uncorrectable error detected: data corruption cannot be repaired.
Firmware error management
The firmware defines the error correction possibilities with the corrected data packet.
When data cannot be repaired, the block is considered as a bad block and is replaced by
another one. See Section 4.2 for further information on bad block management.
13/36
NAND Flash memory interface
4.2
ST72682
Bad block management
NAND memory manufacturers deliver their devices with factory-marked bad blocks. This
marking depends on the manufacturer and the NAND memory type (page size, memory
technology, etc.). The ST72682 supports all bad block markings currently available on the
market.
4.2.1
Bad Block identification
During firmware initialization, the MCU scans the entire NAND memory configuration to
identify bad blocks.
A bad block is defined as follows:
4.2.2
●
Five different block status bytes are considered: 4 status bytes from page 0 and 1 from
an other page (page 127 for MLC NAND; page 1 for SLC NAND).
●
The considered block is marked as a bad block if one out of these five bytes contains at
least four bits set to ‘0’.
Bad block replacement
The firmware works on groups of 1024 blocks, called zones. A complete NAND
configuration can contain several zones:
●
Each zone is described in a Look Up Table (LUT) containing 1024 entries. A LUT is
composed of 3 parts: used blocks, free blocks and bad blocks.
●
The “bad blocks” part contains as many entries as the number of bad blocks identified
in that zone.
●
The “used blocks” part can have a size of 1000, 900 or 500 entries. This size is
configurable and also depends on the number of identified bad blocks.
●
The “free blocks” part contains the remaining entries.
The used blocks part is used to do a correspondence between NAND blocks and logical
address ranges.
This system allows all bad blocks to be masked from the Host. As a result, bad blocks are
never seen. Only a range of logical addresses are visible which correspond to the sum of
the used blocks part of all zones.
4.2.3
Late Fail block
During normal application life, defects may appear in the NAND memory. Under certain
conditions, these defects are not correctable and the corresponding block is declared as
“bad”.
In this case, new bad blocks are identified in the bad blocks part of the LUT and replaced by
new blocks from the “free blocks” part.
14/36
ST72682
4.3
NAND Flash memory interface
Wear levelling
During normal application life, the NAND memory is written and erased (at block level) many
times. The NAND device is guaranteed for a limited number of write operations (about 100
000 cycles). As a consequence, the controller must keep write/erase operations to a
minimum for any individual block.
A method to limit these cycles is to use a “Wear Levelling” scheme between all NAND
memory blocks.
LUT usage
The LUT is used for transfers between a logical address range and a block. It contains free
blocks which are used in the “wear levelling” scheme.
During write command treatment, the firmware calculates the zones, blocks and pages for
data write access. In a block write operation, the firmware applies the following scheme to
avoid block wearing:
●
The least recently-used block is chosen from the free block part of the LUT.
●
Valid data from the old block is copied to the new block.
●
New data from the write command is written to the new block.
●
The old block is erased.
●
The LUT is updated after identifying the new block in the used block part and the old
block in the free block part.
Using this scheme, a logical address range doesn’t correspond to a constant block. A write
command repeated several times to the same logical address writes physically into different
blocks.
This method shares the wearing evenly across all blocks of the concerned zone.
4.4
NAND Flash interface configuration
Applications based on ST72682 can be configured through a dedicated PC software tool.
The NAND memory RE and WE signals frequencies can be independently configured to
30 MHz, 20 MHz, 15 MHz, 12 MHz and 10 MHz.
The logical size reduction factor can be configured to 90% or 50% in the event of having too
many bad blocks. this option resizes the used blocks part of the LUT to 900 or 500.
15/36
Mass storage implementation
5
Mass storage implementation
5.1
USB characteristics
ST72682
The ST72682 is compliant with USB 2.0 specification.
It is able to operate in both high speed and full speed modes using a bidirectional control
endpoint 0 and a bidirectional bulk endpoint 2.
It automatically recognizes the speed to use on the bus by a process of negotiation with
USB Host.
5.2
BOT/SCSI implementation
5.2.1
BOT specification
The USB Mass Storage Class Bulk Only Transport (BOT) specification version 1.0 is
implemented. It allows the device to be recognized by the host as a mass-storage USB
device.
5.2.2
SCSI specification
Moreover, inside BOT transfers, SCSI commands are encapsulated for mass storage
operations.
The related specifications are SBC-2 revision 10 (SCSI Block Commands 2) and SPC-4
revision 7a (SCSI Primary Commands 4).
5.2.3
Bootability specification
The USB mass storage specification for bootability revision 1.0 is implemented.
It allows the PC host to boot the operating system from the USB mass storage application.
In this case, the Host uses BOT LUN 0 (logical unit number).
A specific tool must be used to format the logical drive in order to make it bootable by
programming the correct information.
5.3
Multi-LUN device characteristics
The application can be configured with a dedicated PC software tool as a multi-LUN device.
In this case, up to 3 different drives are available: public drive, additional drive and private
drive.
Public and additional drives can be configured as removable drive, hard disk drive or CDROM drive.
16/36
ST72682
5.3.1
Mass storage implementation
Public drive
The public drive is the default configuration in a mono-LUN mode. In this default case, it is
declared as a removable drive.
The public drive is mandatory and can not be removed from the configuration. By
customization (using PC software), it can be declared as a removable drive, a CD-ROM
drive or a hard disk drive.
This drive is the LUN 0 in BOT commands.
5.3.2
Private drive
The Private drive is optional. Its type is “removable drive” and is not configurable.
This drive is protected by password and cannot be directly accessed through the PC
operating system. A PC software tool is necessary to send a command with the password to
unlock the device. The device is then open and accessible by the PC operating system until
reset or reception of a new command to lock the drive.
This drive is the LUN 1 in BOT commands.
5.3.3
Additional drive
The additional drive is optional. Its type can be “removable drive”, “hard disk drive” or “CDROM drive”.
This drive is LUN 1 in BOT commands if the private drive option is not active, and is LUN 2 if
the private drive option is active.
5.3.4
CD-ROM considerations
When a drive is declared as CD-ROM, the ST72682/R21 manages this drive with a logical
block size of 2 Kbytes. To be correctly recognized by the host, it is preferable to build a
CDFS partition on this CD-ROM. See the ‘ST7268x Production Tool User Manual’ for more
information.
Note that the ST72682/R20 doesn’t consider the CD-ROM partition as a specific case. The
logical block size is 512 bytes and any file system can be used.
In both cases, the CD-ROM partition allows the use of the AutoRun operating system
feature. During device connection, the CD-ROM partition is recognized and the host tries to
run the application corresponding to the autorun.inf file present into this CD-ROM partition.
5.4
Mass storage interface configuration
In addition to the parameters already described as configurable in the previous chapters,
additional customizable information includes:
●
USB parameters: VID, PID, all string information.
●
SCSI parameters: strings for inquiry commands.
17/36
Human interface implementation
6
Human interface implementation
6.1
LED behavior
ST72682
The application is designed to manage 2 LEDs. This behavior is configurable through PC
dedicated software: ‘ST7268x Production Tool’.
By default, LED 1 responds to NAND memory access activity and LED 2 responds to USB
activity.
Use of LED 1 is optional. When this option is not active, LED 2 reacts to both USB and
NAND memory activity.
6.2
Read-only switch
The READ ONLY pin of the ST72682 is an input pin to be connected to VDD or GND
depending on the behavior of the device.
18/36
●
When this pin is connected to GND, no limitations are applied on the PC command
received.
●
When this pin is connected to VDD or unconnected, the firmware filters all accesses to
the NAND memory which modify the NAND memory state (write, erase, etc.) and
returns an error to the PC.
ST72682
Electrical characteristics
7
Electrical characteristics
7.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
7.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the Devices with an ambient temperature at TA=25 °C and TA=TAmax (given by the
selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3Σ).
7.1.2
Typical values
Unless otherwise specified, typical data are based on TA=25 °C, VDD33=3.3 V. They are
given only as design guidelines and are not tested.
7.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
7.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 4.
Figure 4.
Pin loading conditions
DEVICE PIN
CL
19/36
Electrical characteristics
7.1.5
ST72682
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 5.
Figure 5.
Pin input voltage
DEVICE PIN
VIN
7.2
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the Device. This is a stress rating only and functional operation of the Device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 8.
Voltage characteristics
Symbol
VDD33 - VSS
VIN(1)(2)
VESD(HBM)
Ratings
Supply voltage
Input voltage on any other pin
Electrostatic discharge voltage (Human Body
Model)
Maximum value
Unit
4.0
V
VSS−0.3 to
VDD33+0.3
V
see Section 7.6.3: Absolute
Maximum Ratings (Electrical
Sensitivity)
1. Directly connecting the RESET and I/O pins to VDD33 or VSS could damage the Device if an unintentional
internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a
corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up
or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). For the same reason, unused I/O pins must
not be directly tied to VDD33 or VSS.
2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise
refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD33 while a negative injection is
induced by VIN<VSS.
Table 9.
Symbol
IVDD33
IVSS
Current characteristics
Ratings
Maximum value
Total current into VDD33 power lines (source)(1)
Total current out of VSS ground lines
(sink)(1)
Unit
200
200
Output current sunk by any I/O D2 type
25
Output current sunk by any I/O D4 type
35
Output current sunk by any I/O D8 type
50
Output current source by any I/Os and control pin
−25
mA
IIO(2)
1. All power supply (VDD33) and ground (VSS) lines must always be connected to the external supply.
2. Refer to Table 6 for the output drive capability of each of the I/Os.
20/36
ST72682
Electrical characteristics
Table 10.
Thermal characteristics
Symbol
7.3
Ratings
TSTG
Storage temperature range
TJMAX
Maximum junction temperature
Value
Unit
−65 to +150
°C
120
°C
Operating conditions
Table 11.
General operating conditions
Symbol
VDD33
TA
Figure 6.
Parameter
Conditions
Min
Max
Unit
3.0
3.6
V
0
70
°C
Power Supply
Ambient temperature range
Clock frequency versus supply voltage
fCPU [MHz]
FUNCTIONALITY
GUARANTEED
IN THIS AREA
30
FUNCTIONALITY
T GUARANTEED 15
IN THIS AREA
6
3
SUPPLY VOLTAGE [VDD33]
0
2.0
7.4
2.5 2.7
3.3
3.0
3.6
Supply current characteristics
Table 12.
Symbol
IDD
Table 13.
RUN and SUSPEND modes current
Parameter
Conditions
Min
Typ
Max
Unit
Supply current in RUN mode
fOSC=12MHz
15
25
35
mA
Supply current in SUSPEND mode
VDD33=3.3V, TA=+25°C
60
90
190
µA
Supply and Clock managers current
Symbol
Parameter
IDD(CK)
Supply current of crystal oscillator(3)
Conditions
Typ(1) Max(2)
1000
2000
Unit
µA
1. Typical data are based on TA=25 °C and fCPU=12 MHz.
2. Data based on characterization results, not tested in production.
3. Data based on characterization results done with the external components specified in Section 7.5.1, not
tested in production.
21/36
Electrical characteristics
7.5
ST72682
Clock and timing characteristics
Subject to general operating conditions for VDD33, fOSC, and TA.
7.5.1
Crystal oscillator
The Device internal clock is supplied from a crystal oscillator. All the information given in this
paragraph are based on characterization results with specified typical external components.
In the application the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal
manufacturer for more details (frequency, package, accuracy...).
Table 14.
Clock characteristics
Symbol
Parameter
fOSC
Conditions
Min
Oscillator frequency
CKACC
αOSC
Typ
Max
Unit
12
Total crystal oscillator
accuracy
Absolute value +
temperature + aging
Crystal oscillator duty cycle(1)
45
50
MHz
±60
ppm
55
%
1. The crystal oscillator duty cycle has to be adjusted through the two CL capacitors. Refer to the crystal
manufacturer for more details.
Figure 7.
VDDA
Typical application with a crystal
CL
OSCIN
CRYSTAL
CL
OSCOUT
RSOSCOUT
Device
(1)
1. Depending on the crystal power dissipation, a serial resistor RsOscout may be added. Refer to the crystal
manufacturer for more details.
Table 15.
22/36
Typical CL and RS values by crystal
Supplier
Typical Crystal
CL (pF)
RSOSCOUT
(Ω)
NDK
AT51 or AT41
16
560
ST72682
7.6
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
7.6.1
Functional EMS (Electromagnetic Susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electrostatic Discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD33 and
VSS33 through a 100pF capacitor, until a functional disturbance occurs. This test
conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
●
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
–
Corrupted program counter
–
Unexpected reset
–
Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can
be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins
for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can
be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 16.
Symbol
EMS characteristics
Parameter
Conditions
Level/Class
VFESD
Voltage limits to be applied
on any I/O pin to induce a
functional disturbance
VDD33=3.3 V, TA=+25 °C, fOSC=12 MHz
compliant with IEC 1000-4-2
4B
VFFTB
Fast transient voltage burst
limits to be applied through
100pF on VDD33 and VSS33
pins to induce a functional
disturbance
VDD33=3.3 V, TA=+25 °C, fOSC=12 MHz
compliant with IEC 1000-4-4
4A
23/36
Electrical characteristics
7.6.2
ST72682
Electromagnetic Interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 17.
EMI characteristics
Symbol Parameter
SEMI
Peak level
Monitored
Frequency
Band
(fOSC at 12 MHz)
0.1 to 30 MHz
20
30 to 130 MHz
25
130 MHz to 1
GHz
25
SAE EMI Level
4
Conditions
VDD33=3.3 V, TA=+25 °C,
conforming to SAE J 1752/3(1)
Max vs.
Unit
dBµV
-
1. Refer to Application Note AN1709 for data on other package types.
7.6.3
Absolute Maximum Ratings (Electrical Sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic Discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard.
Table 18.
Symbol
VESD(HBM)
Absolute maximum ratings
Ratings
Electrostatic discharge voltage
(Human Body Model)
Conditions
TA=+25°C
Maximum
value(1)
Unit
2000
V
1. Data based on characterization results, not tested in production.
Static and Dynamic Latch-Up
24/36
■
LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
■
DLU: Electrostatic discharges (one positive then one negative test) are applied to each
pin of 3 samples when the micro is running to assess the latch-up performance in dynamic
mode. Power supplies are set to the typical values, the oscillator is connected as near as
possible to the pins of the micro and the component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the
application note AN1181.
ST72682
Electrical characteristics
Table 19.
Electrical sensitivities
Parameter
Conditions
Class(1)
Static latch-up class
TA=+25 °C
A
VDD33=3.3 V, fOSC=12 MHz,
TA=+25 °C
A
Symbol
LU
DLU
Dynamic latch-up class
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
7.7
I/O port pin characteristics
7.7.1
General characteristics
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Table 20.
I/O port characteristics
Symbol
Parameter
VIL
Min
Typ
Input low level voltage(1)
voltage(1)
VIH
Input high level
Vhys
Schmitt trigger voltage
hysteresis(2)
IL
Input leakage current
RPU
Conditions
Weak pull-up equivalent
resistor(1)
Max
Unit
0.16VDD33
400
mV
VSS ≤ VIN ≤ VDD33,
standard I/Os
VIN=VSS
V
0.85VDD33
TTL ports
VDD33= 3.3 V
32
50
1
µA
75
kΩ
1. The RPU pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, tested
in production at VDD33 max.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
Figure 8.
Two typical applications with unused I/O pin
VDD33
Device
10kΩ
UNUSED I/O PORT
UNUSED I/O PORT
10kΩ
Device
25/36
Electrical characteristics
Figure 9.
Typical VIL and VIH standard I/Os
ST72682
Figure 10. Typical RPU vs. VDD33 with VIN=VSS
I/ O s pull- up re s is t a nc e
I/Os pull-up
resistance (kW)
V IL/ V IH ( V )
VIL/VIH (V)
2.5
2
1.5
1
0.5
0
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VD D (V)
26/36
60
50
40
30
2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VD D (V)
ST72682
7.7.2
Electrical characteristics
Output driving current
Subject to general operating conditions for VDD33, fOSC, and TA unless otherwise specified.
Table 21.
Output driving current
Symbol
VOL(1)
Parameter
Conditions
Max
Output low level voltage for a D2 I/O pin
when 8 pins are sunk at same time
(see Figure )
IIO=2mA
300
Output low level voltage for a D4 I/O pin
when 8 pins are sunk at same time
(see Figure 12)
IIO=4mA
400
IIO=8mA
500
IIO=2mA
600
Output high level voltage for a D4 I/O pin
when 8 pins are sourced at same time
(see Figure 15)
IIO=4mA
600
Output high level voltage for a D8 I/O pin
when 8 pins are sourced at same time
(see Figure 16)
IIO=8mA
600
VDD33=3.3 V
Output low level voltage for a D8 I/O pin
when 8 pins are sunk at same time
(see Figure 13)
Output high level voltage for a D2 I/O pin
when 8 pins are sourced at same time
(see and Figure 14)
VDD33VOH(2)
Min
Unit
mV
mV
1. The IIO current sunk must always respect the absolute maximum rating specified in Section Table 9. and
the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section Table 9.
and the sum of IIO (I/O ports and control pins) must not exceed IVDD33. True open drain I/O pins does not
have VOH.
Figure 11. Typical VOL at VDD33=3.3 V (I/O D2)
Figure 12. Typical VOL at VDD33=3.3 V (I/O D4)
V O L I/ O s D 4 a t V D D =3 .3 V
150
100
50
0
0
1
2
IO L ( m A )
3
4
VOL 4mA (mV)
VOL 2mA (mV)
V O L I/ O s D 2 a t V D D =3 .3 V
150
100
50
0
0
2
4
6
IO L ( m A )
27/36
Electrical characteristics
ST72682
V O L I/ O s D 8 a t V D D =3 .3 V
V D D - V O H I/ O s D 2 a t V D D =3 .3 V
150
100
50
0
0
5
10
VOH 2mA (mV)
Figure 14. Typical VDD33-VOH vs. VDD33 (I/O D2)
VOL 8mA (mV)
Figure 13. Typical VOL at VDD33=3.3 V (I/O D8)
200
150
100
50
0
0
2
4
IO H ( m A )
IO L ( m A )
Figure 15. Typical VDD33-VOH vs. VDD33 (I/O D4) Figure 16. Typical VDD33-VOH vs. VDD33 (I/O D8)
150
100
50
0
0
2
IO H ( m A )
28/36
V D D - V O H I/ O s D 8 a t V D D =3 .3 V
4
6
VOH 8mA (mV)
VOH 4mA (mV)
V D D - V O H I/ O s D 4 a t V D D =3 .3 V
200
150
100
50
0
0
5
IO H ( m A )
10
ST72682
Electrical characteristics
7.8
Control pin characteristics
7.8.1
Asynchronous RESET pin
TA ranges between 0 and +55 °C unless otherwise specified.
.
Table 22.
Symbol
Asynchronous RESET pin characteristics
Parameter
Conditions
VIL
Input low level voltage(1)
VIH
Input high level voltage
Vhys
Schmitt trigger voltage
hysteresis(1)
RON
Pull-up equivalent resistor
Min
Unit
V
0.85VDD33
450
VDD33 = 3.3 V
20
40
mV
80
kΩ
VDD33 = 2 V
Filtered glitch
Max
0.16VDD33
teh(RSTL) External reset pulse hold time(2)
tg(RSTL)
Typ
100
2.5
duration(3)
µs
200
tew(RSTL) External reset pulse duration(4)
500
tiw(RSTL) Internal reset pulse duration
ns
µs
2
Tcpu
1. The level on the RESET pin must be free to go below the VIL max. level specified in Section 7.8.1.
Otherwise the reset will not be taken into account internally.
2. To guarantee the reset of the Device, a minimum pulse has to be applied to the RESET pin. All short
pulses applied on RESET pin with a duration below teh(RSTL) can be ignored. Not tested in production,
guaranteed by design.
3. The reset network protects the device against parasitic resets.
4. The external reset duration must respect this timing to guarantee a correct start-up of the internal regulator
at power-up. Not tested in production, guaranteed by design.
Figure 17. Typical RON on RESET pin
NRESET pull-up
(kOhms)
NRESET pull-up (kOhms)
100
80
60
40
2
3
VDD (V)
29/36
Electrical characteristics
ST72682
7.9
Other communication interface characteristics
7.9.1
MSCI parallel interface
Figure 18. Timing diagrams for input mode (with max load on CTRL signal = 50 pf)
CTRL
external
DATA
DATA(i)
ext device
DATA(i+1)
tDS(1)
1. tDS is the setup time for data sampling.
Figure 19. Timing diagrams for output mode (with max CTRL signal = 50 pf, DATA)
CTRL
external
DATA
DATA(i)
external
DATA(i+1)
tDO(1)
1. tDO is the data output time for data sampling.
Table 23.
MSCI parallel interface DC characteristics
MSCI DC Electrical Characteristics
Conditions
Symbol
Data setup time
tDS
11
ns
Data output time
tDO
6
ns
CTRL line capacitance
Cctrl
50
pF
Data line capacitance
Cdata
50
pF
1. Data based on design simulation and not tested in production.
30/36
Min.
Typ(1)
Parameter
Max.
Unit
ST72682
7.9.2
Electrical characteristics
USB (Universal Bus Interface)
Table 24.
USB Interface DC characteristics
Symbol
Parameter
Conditions
IDDsuspend Suspend current
RPU
Min.
Typ.
VDD33=3.3 V, regulator
and PHY ON
0.5(1)
1.5
6(1)
mA
VDD33=3.3 V, Powerdown mode, 25 °C (2)
60
90
190
µA
Pull-up resistor(1)
Max. Unit
1.5
kΩ
Full Speed Mode
VTERM
Termination voltage
0.8
2.0
V
VOH
High level output voltage
2.8
3.6
V
VOL
Low level output voltage
0.8
V
VCRS
Crossover voltage
2.0
V
1.3
High Speed Mode
VHSOH
HS data signalling high
400
mV
VHSOL
HS data signalling low
5
mV
1. Not tested in production, guaranteed by characterization.
2. In order to reach this value, the software must force the regulator into power-down mode and the I/Os
compensation cell off.
Table 25.
Symbol
USB Interface AC timing
Parameter
Conditions
Min.
Max.
Unit
Full Speed Mode
TFR
Rise Time
CL=50pF
4
20
ns
TFF
Fall Time
CL=50pF
4
20
ns
High Speed Mode
THSR
Rise Time
500(1)
ps
THSF
Fall Time
500(1)
ps
480.24
Mb/
s
THSDRAT
HS Data Rate
479.76
1. Not tested in production, guaranteed by characterization.
31/36
Electrical characteristics
ST72682
Figure 20. USB signal eye diagram
Table 26.
32/36
USB high speed transmit waveform requirements
Voltage Level (DP - DN)
Time
Unit Interval (UI)
-
2.082 to 2.084 ns
Level 1
475 mV
-
Level 2
−475 mV
-
Point 1
0V
5% UI
Point 2
0V
95% UI
Point 3
300 mV
35% UI
Point 4
300 mV
65% UI
Point 5
−300 mV
35% UI
Point 6
−300 mV
65% UI
ST72682
8
Package mechanical data
Package mechanical data
Figure 21. 64-pin Thin Quad Flat Package (10 x10) package outline
A
A2
D
D1
A1
b
E1 E
e
c
L1
L
Table 27.
θ
64-pin Thin Quad Flat Package (10 x10) mechanical data
mm
inches
Dim.
Min
Typ
A
Max
Min
Typ
1.60
A1
0.05
A2
1.35
b
0.17
c
0.09
Max
0.063
0.15
0.002
0.006
1.40
1.45
0.053
0.055
0.057
0.22
0.27
0.007
0.009
0.011
0.20
0.004
0.008
D
12.00
0.472
D1
10.00
0.394
E
12.00
0.472
E1
10.00
0.394
e
0.50
0.020
θ
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.018
0.024
0.030
L1
1.00
0.039
Number of pins
N
64
33/36
Device ordering information
9
ST72682
Device ordering information
Table 28.
Feature comparison
Features added in the ST72682/R21 versus
ST72682/R20
Continued AutoRun CDROM partition support
Table 29.
AutoRun runs a program when the USB
Flash drive is inserted into a computer.
Ordering Information
Package
Operating voltage
Temperature
range
ST72682/R20
LQFP64 10x10mm
3.0V to 3.6V
0°C to +70 °C
ST72682/R21 (latest firmware
revision
LQFP64 10x10mm
3.0V to 3.6V
0°C to +70 °C
Orderable part number
34/36
Description
ST72682
10
Revision history
Revision history
Table 30.
Document revision history
Date
Revision
Description of Changes
09-Feb-2006
1.0
Initial release
14-Aug-2007
2.0
Firmware revision updated to R21.
References to TQFP64 updated to LQFP64.
Datasheet reformatted.
35/36
ST72682
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36/36