Datasheet - STMicroelectronics

STM32F042x
ARM®-based 32-bit MCU, up to 32 KB Flash, crystal-less USB
FS 2.0, CAN, 8 timers, ADC & comm. interfaces, 2.0 - 3.6 V
Datasheet - production data
Features
 Core: ARM 32-bit Cortex-M0 CPU,
frequency up to 48 MHz
 Memories
– 16 to 32 Kbytes of Flash memory
– 6 Kbytes of SRAM with HW parity
 CRC calculation unit
 Reset and power management
– Digital and I/Os supply: VDD = 2 V to 3.6 V
– Analog supply: VDDA = VDD to 3.6 V
– Selected I/Os: VDDIO2 = 1.65 V to 3.6 V
– Power-on/Power down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low power modes: Sleep, Stop, Standby
– VBAT supply for RTC and backup registers
 Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x6 PLL option
– Internal 40 kHz RC oscillator
– Internal 48 MHz oscillator with automatic
trimming based on ext. synchronization
 Up to 37 fast I/Os
– All mappable on external interrupt vectors
– Up to 37 I/Os with 5 V tolerant capability
and 8 with independent supply VDDIO2
 5-channel DMA controller
 One 12-bit, 1.0 μs ADC (up to 10 channels)
– Conversion range: 0 to 3.6 V
– Separate analog supply: 2.4 V to 3.6 V
 Calendar RTC with alarm and periodic wakeup
from Stop/Standby
TSSOP20
 Communication interfaces
– One I2C interface supporting Fast Mode
Plus (1 Mbit/s) with 20 mA current sink,
SMBus/PMBus and wakeup
– Two USARTs supporting master
synchronous SPI and modem control; one
with ISO7816 interface, LIN, IrDA, auto
baud rate detection and wakeup feature
– Two SPIs (18 Mbit/s) with four to 16
programmable bit frames, one with I2S
interface multiplexed
– CAN interface
– USB 2.0 full-speed interface, able to run
from internal 48 MHz oscillator and with
BCD and LPM support
 HDMI CEC, wakeup on header reception
 Serial wire debug (SWD)
 96-bit unique ID
 All packages ECOPACK2
Table 1. Device summary
Reference
STM32F042xx
This is information on a product in full production.
WLCSP36
 Nine timers
– One 16-bit advanced-control timer for six
channel PWM output
– One 32-bit and four 16-bit timers, with up to
four IC/OC, OCN, usable for IR control
decoding
– Independent and system watchdog timers
– SysTick timer
 Up to 14 capacitive sensing channels for
touchkey, linear and rotary touch sensors
April 2014
UFQFPN48 7x7
UFQFPN32 5x5
UFQFPN28 4x4
LQFP48 7x7
LQFP32 5x5
DocID025832 Rev 2
Part number
STM32F042F4, STM32F042G4,
STM32F042K4, STM32F042T4,
STM32F042C4
STM32F042F6, STM32F042G6,
STM32F042K6, STM32F042T6,
STM32F042C6
1/117
www.st.com
Contents
STM32F042xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
ARM® Cortex®-M0 core with embedded Flash and SRAM . . . . . . . . . . . 13
3.2
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2
Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10
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3.5.1
3.9.1
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18
3.9.2
Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.10.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12.1
Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12.2
General-purpose timers (TIM2..3, TIM14, 16, 17) . . . . . . . . . . . . . . . . . 22
3.12.3
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12.4
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.12.5
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.14
Inter-integrated circuit interfaces (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID025832 Rev 2
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Contents
3.15
Universal synchronous/asynchronous receiver transmitters (USART) . . 25
3.16
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 26
3.17
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.19
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.20
Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.21
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4
Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 50
6.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 50
6.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.6
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.7
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.8
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.9
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.10
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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Contents
7
STM32F042xx
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.16
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.17
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.18
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.19
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.20
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
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STM32F042xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F042x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive sensing GPIOs available on STM32F042x devices . . . . . . . . . . . . . . . . . . . . . 20
No. of capacitive sensing channels available on STM32F042x devices. . . . . . . . . . . . . . . 21
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F042x I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F042x USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F042x SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F042x pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Alternate functions selected through GPIOA_AFR registers for port A . . . . . . . . . . . . . . . 38
Alternate functions selected through GPIOB_AFR registers for port B . . . . . . . . . . . . . . . 39
Alternate functions selected through GPIOF_AFR registers for port F. . . . . . . . . . . . . . . . 40
STM32F042x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 50
Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typical and maximum current consumption from VDD supply at VDD = 3.6 V . . . . . . . . . . 52
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . 54
Typical and maximum consumption in Stop and Standby modes . . . . . . . . . . . . . . . . . . . 55
Typical and maximum current consumption from the VBAT supply . . . . . . . . . . . . . . . . . . 56
Typical current consumption, code executing from Flash, running from HSE
8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSI14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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List of tables
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
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Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
IWDG min/max timeout period at 40 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
WWDG min/max timeout value at 48 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LQFP48 – 7 mm x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . . . . 95
UFQFPN48 – 7 mm x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . 99
WLCSP36, 0.4 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP32 – 7 mm x 7 mm 32-pin low-profile quad flat package mechanical data . . . . . . . 104
UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
TSSOP20 – 20-pin thin shrink small outline package mechanical data . . . . . . . . . . . . . . 112
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
DocID025832 Rev 2
STM32F042xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LQFP48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
UFQFPN48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
WLCSP36 36-pin package ball-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LQFP32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
UFQFPN32 32-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
UQFPN28 28-pin package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP20 20-pin package (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32F042x memory map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSI oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSI14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
HSI48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
I2S slave timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
LQFP48 – 7 mm x 7 mm, 48 pin low-profile quad flat package outline. . . . . . . . . . . . . . . . 95
LQFP48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LQFP48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
UFQFPN48 – 7 mm x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . 98
UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
UFQFPN48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
WLCSP36 - 0.4 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
WLCSP36 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP32 – 7 mm x 7 mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 104
LQFP32 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP32 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline . . 107
UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UFQFPN32 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline . . 109
UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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8
List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
8/117
STM32F042xx
UFQFPN28 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
TSSOP20 - 20-pin thin shrink small outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TSSOP20 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
DocID025832 Rev 2
STM32F042xx
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F042x microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website at
www.st.com.
For information on the ARM Cortex-M0 core, please refer to the Cortex-M0 Technical
Reference Manual, available from ARM website at www.arm.com.
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27
Description
2
STM32F042xx
Description
The STM32F042x microcontrollers incorporate the high-performance ARM Cortex-M0
32-bit RISC core operating at a 48 MHz frequency, high-speed embedded memories (up to
32 Kbytes of Flash memory and 6 Kbytes of SRAM), and an extensive range of enhanced
peripherals and I/Os. All devices offer standard communication interfaces (one I2C, two
SPIs/one I2S, one HDMI CEC and two USARTs), one USB Full speed device (crystal-less),
one CAN, one 12-bit ADC, four general-purpose 16-bit timers, a 32-bit timer and an
advanced-control PWM timer.
The STM32F042x microcontrollers operate in the -40 to +85 °C and -40 to +105 °C
temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
modes allows the design of low-power applications.
The STM32F042x microcontrollers include devices in seven different packages ranging
from 20 pins to 48 pins with a die form also available upon request. Depending on the
device chosen, different sets of peripherals are included. The description below provides an
overview of the complete range of STM32F042x peripherals proposed.
These features make the STM32F042x microcontrollers suitable for a wide range of
applications such as application control and user interfaces, handheld equipment, A/V
receivers and digital TV, PC peripherals, gaming and GPS platforms, industrial applications,
PLCs, inverters, printers, scanners, alarm systems, video intercoms, and HVACs.
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STM32F042xx
Description
Table 2. STM32F042x device features and peripheral counts
Peripheral
Flash (Kbytes)
SRAM (Kbytes)
Timers
STM32F042Fx
16
32
6
STM32F042G
16
STM32F042K
32
16
6
32
STM32F042C
16
6
1 (16-bit)
General
purpose
4 (16-bit)
1 (32-bit)
32
6
1 [1]
2 [1]
2
I C
1
USART
2
CAN
1
USB
1
CEC
1
12-bit ADC
(number of channels)
16
6
Advanced
control
SPI [I2S](1)
Comm.
interfaces
32
STM32F042T
1
(9 ext. + 3 int.)
1
(10 ext. + 3 int.)
GPIOs
16
24
26
28
30
38
Capacitive sensing
channels
7
11
13
14
14
14
Max. CPU frequency
48 MHz
Operating voltage
Operating temperature
Packages
2.0 to 3.6 V
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: -40 °C to 105 °C / -40 °C to 125 °C
TSSOP20
UQFPN28
LQFP32
UQFPN32
WLCSP36
LQFP48
UFQFPN48
1. The SPI1 interface can be used either in SPI mode or in I2S audio mode.
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27
Description
STM32F042xx
Figure 1. Block diagram
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12/117
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Functional overview
3
Functional overview
3.1
ARM® Cortex®-M0 core with embedded Flash and SRAM
The ARM Cortex-M0 processor is the latest generation of ARM processors for
embedded systems. It has been developed to provide a low-cost platform that meets the
needs of MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced system response to
interrupts.
The ARM Cortex-M0 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F0xx family has an embedded ARM core and is therefore compatible with all
ARM tools and software.
Figure 1 shows the general block diagram of the device family.
3.2
Memories
The device has the following features:

6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.

The non-volatile memory is divided into two arrays:
–
16 to 32 Kbytes of embedded Flash memory for programs and data
–
Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (Cortex-M0 serial wire) and boot
in RAM selection disabled
3.3
Boot modes
At startup, the boot pin and boot selector option bits are used to select one of the three boot
options:

Boot from User Flash

Boot from System Memory

Boot from embedded SRAM
The boot pin is shared with the standard GPIO and can be disabled through the boot
selector option bits. The boot loader is located in System Memory. It is used to reprogram
the Flash memory by using USART on pins PA14/PA15 or PA9/PA10, I2C on pins PB6/PB7
or through the USB DFU interface.
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27
Functional overview
3.4
STM32F042xx
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a CRC-32 (Ethernet) polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
3.5
Power management
3.5.1
Power supply schemes




3.5.2
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
VDDA = 2.0 to 3.6 V: external analog power supply for ADC, Reset blocks, RCs and
PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). The VDDA
voltage level must be always greater or equal to the VDD voltage level and must be
provided first.
VDDIO2 = 1.65 to 3.6 V: external power supply for marked I/Os. Provided externally
through the VDDIO2 pin. The VDDIO2 voltage level is completely independent from VDD
or VDDA, but it must not be provided without a valid supply on VDD. Refer to the pinout
diagrams or tables for concerned I/Os list.
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Power supply supervisors
The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.

The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.

The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The VDDIO2 supply is monitored and compared with the internal reference voltage (VREFINT).
When the VDDIO2 is below this threshold, all the I/Os supplied from this rail are disabled by
hardware. The output of this comparator is connected to EXTI line 31 and it can be used to
generate an interrupt.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
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3.5.3
Functional overview
Voltage regulator
The regulator has two operating modes and it is always enabled after reset.

Main (MR) is used in normal operating mode (Run).

Low power (LPR) can be used in Stop mode where the power demand is reduced.
In Standby mode, it is put in power down mode. In this mode, the regulator output is in high
impedance and the kernel circuitry is powered down, inducing zero consumption (but the
contents of the registers and SRAM are lost).
3.5.4
Low-power modes
The STM32F042x microcontrollers support three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:

Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.

Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the
HSE crystal oscillators are disabled. The voltage regulator can also be put either in
normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI lines. The EXTI line
source can be one of the 16 external lines, the PVD output, RTC alarm, I2C1, USART1
or the CEC.
The I2C1, USART1 and the CEC can be configured to enable the HSI RC oscillator for
processing incoming data. If this is used when the voltage regulator is put in low power
mode, the regulator is first switched to normal mode before the clock is provided to the
given peripheral.

Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the RTC
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pins, or an RTC event occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering
Stop or Standby mode.
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27
Functional overview
3.6
STM32F042xx
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
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STM32F042xx
Functional overview
Figure 2. Clock tree
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3.7
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions.
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27
Functional overview
STM32F042xx
The I/O configuration can be locked if needed following a specific sequence in order to
avoid spurious writing to the I/Os registers.
3.8
Direct memory access controller (DMA)
The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers.
The DMA supports circular buffer management, removing the need for user code
intervention when the controller reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
DMA can be used with the main peripherals: SPI, I2S, I2C, USART, all TIMx timers (except
TIM14) and ADC.
3.9
Interrupts and events
3.9.1
Nested vectored interrupt controller (NVIC)
The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to
32 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M0) and 4
priority levels.

Closely coupled NVIC gives low latency interrupt processing

Interrupt entry vector table address passed directly to the core

Closely coupled NVIC core interface

Allows early processing of interrupts

Processing of late arriving higher priority interrupts

Support for tail-chaining

Processor state automatically saved

Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.9.2
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The EXTI
can detect an external line with a pulse width shorter than the internal clock period. Up to 38
GPIOs can be connected to the 16 external interrupt lines.
3.10
Analog to digital converter (ADC)
The 12-bit analog to digital converter has up to 10 external and 3 internal (temperature
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Functional overview
sensor, voltage reference, VBAT voltage measurement) channels and performs conversions
in single-shot or scan modes. In scan mode, automatic conversion is performed on a
selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
3.10.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 3. Temperature sensor calibration values
Calibration value name
3.10.2
Description
Memory address
TS_CAL1
TS ADC raw data acquired at a
temperature of 30 °C (5 °C),
VDDA= 3.3 V (10 mV)
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at a
temperature of 110 °C (5 °C),
VDDA= 3.3 V (10 mV)
0x1FFF F7C2 - 0x1FFF F7C3
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage
of VREFINT is individually measured for each part by ST during production test and stored in
the system memory area. It is accessible in read-only mode.
Table 4. Internal voltage reference calibration values
Calibration value name
VREFINT_CAL
Description
Memory address
Raw data acquired at a
temperature of 30 °C (5 °C), 0x1FFF F7BA - 0x1FFF F7BB
VDDA= 3.3 V (10 mV)
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Functional overview
3.10.3
STM32F042xx
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage
using the internal ADC channel ADC_IN18. As the VBAT voltage may be higher than VDDA,
and thus outside the ADC input range, the VBAT pin is internally connected to a bridge
divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.11
Touch sensing controller (TSC)
The STM32F042x devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 14 capacitive sensing channels
distributed over 5 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
Table 5. Capacitive sensing GPIOs available on STM32F042x devices
Group
1
2
3
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Capacitive sensing
signal name
Pin
name
Capacitive sensing
signal name
Pin
name
TSC_G1_IO1
PA0
TSC_G4_IO1
PA9
TSC_G1_IO2
PA1
TSC_G4_IO2
PA10
TSC_G1_IO3
PA2
TSC_G4_IO3
PA11
TSC_G1_IO4
PA3
TSC_G4_IO4
PA12
TSC_G2_IO1
PA4
TSC_G5_IO1
PB3
TSC_G2_IO2
PA5
TSC_G5_IO2
PB4
TSC_G2_IO3
PA6
TSC_G5_IO3
PB6
TSC_G2_IO4
PA7
TSC_G5_IO4
PB7
TSC_G3_IO2
PB0
TSC_G3_IO3
PB1
TSC_G3_IO4
PB2
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Group
4
5
STM32F042xx
Functional overview
Table 6. No. of capacitive sensing channels available on STM32F042x devices
Number of capacitive sensing channels
STM32F042Cx
Analog I/O group
LQPF48
UQFPN48
STM32F042Tx
WLCSP36
STM32F042Kx
LQFP32
UQFPN32
STM32F042Gx
STM32F042Fx
UQFPN28
TSSOP20
G1
3
3
3
3
3
G2
3
3
3
3
3
G3
2
2
1
2
1
0
G4
3
3
3
1
1
G5
3
3
3
3
0
Number of capacitive
sensing channels
14
14
13
14
11
7
3.12
Timers and watchdogs
The STM32F042x devices include up to five general-purpose timers and an advanced
control timer.
Table 7 compares the features of the advanced-control and general-purpose timers.
Table 7. Timer feature comparison
Timer
type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA request
generation
Advanced
control
TIM1
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
Yes
TIM2
32-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM3
16-bit
Up,
down,
up/down
Any integer
between 1
and 65536
Yes
4
No
TIM14
16-bit
Up
Any integer
between 1
and 65536
No
1
No
TIM16,
TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
Yes
General
purpose
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Capture/compare Complementary
channels
outputs
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Functional overview
3.12.1
STM32F042xx
Advanced-control timer (TIM1)
The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six
channels. It has complementary PWM outputs with programmable inserted dead times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:

Input capture

Output compare

PWM generation (edge or center-aligned modes)

One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0-100%).
The counter can be frozen in debug mode.
Many features are shared with those of the standard timers which have the same
architecture. The advanced control timer can therefore work together with the other timers
via the Timer Link feature for synchronization or event chaining.
3.12.2
General-purpose timers (TIM2..3, TIM14, 16, 17)
There are five synchronizable general-purpose timers embedded in the STM32F042x
devices (see Table 7 for differences). Each general-purpose timer can be used to generate
PWM outputs, or as simple time base.
TIM2, TIM3
STM32F042x devices feature two synchronizable 4-channel general-purpose timers. TIM2
is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a
16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advancedcontrol timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM16 and TIM17
Both timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
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Functional overview
They each have a single channel for input capture/output compare, PWM or one-pulse
mode output.
The TIM16 and TIM17 timers can work together via the Timer Link feature for
synchronization or event chaining.
TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
3.12.3
Independent watchdog (IWDG)
The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 kHz internal RC and as it
operates independently from the main clock, it can operate in Stop and Standby modes. It
can be used either as a watchdog to reset the device when a problem occurs, or as a free
running timer for application timeout management. It is hardware or software configurable
through the option bytes. The counter can be frozen in debug mode.
3.12.4
System window watchdog (WWDG)
The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
3.12.5
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:

A 24-bit down counter

Autoreload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source (HCLK or HCLK/8)
3.13
Real-time clock (RTC) and backup registers
The RTC and the 5 backup registers are supplied through a switch that takes power either
on VDD supply when present or through the VBAT pin. The backup registers are five 32-bit
registers used to store 20 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby
mode.
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Functional overview
STM32F042xx
The RTC is an independent BCD timer/counter. Its main features are the following:

Calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.

Automatically correction for 28, 29 (leap year), 30, and 31 day of the month.

Programmable alarm with wake up from Stop and Standby mode capability.

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.

Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.

2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.

Timestamp feature which can be used to save the calendar content. This function can
triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
The RTC clock sources can be:

A 32.768 kHz external crystal

A resonator or oscillator

The internal low-power RC oscillator (typical frequency of 40 kHz)

The high-speed external clock divided by 32
3.14
Inter-integrated circuit interfaces (I2C)
The I2C interface (I2C1) can operate in multimaster or slave modes. It can support Standard
mode (up to 100 kbit/s), Fast mode (up to 400 kbit/s) and Fast Mode Plus (up to 1 Mbit/s)
with 20 mA output drive on some I/Os.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses,
1 with configurable mask). It also includes programmable analog and digital noise filters.
Table 8. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
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Functional overview
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C interface can be served by the DMA controller.
Table 9. STM32F042x I2C implementation
I2C features(1)
I2C1
7-bit addressing mode
X
10-bit addressing mode
X
Standard mode (up to 100 kbit/s)
X
Fast mode (up to 400 kbit/s)
X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
Independent clock
X
SMBus
X
Wakeup from STOP
X
1. X = supported.
3.15
Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds up to two universal synchronous/asynchronous receiver transmitters
(USART1 and USART2), which communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, master synchronous communication and single-wire
half-duplex communication mode. USART1 supports also SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and has a
clock domain independent from the CPU clock, allowing USART1 to wake up the MCU from
Stop mode.
The USART interfaces can be served by the DMA controller.
Refer to Table 10 for the differences between USART1 and USART2.
Table 10. STM32F042x USART implementation
USART modes/features(1)
USART1
USART2
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode
X
X
X(2)
Smartcard mode
Single-wire half-duplex communication
X
IrDA SIR ENDEC block
X
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Functional overview
STM32F042xx
Table 10. STM32F042x USART implementation (continued)
USART modes/features(1)
USART1
LIN mode
X
Dual clock domain and wakeup from Stop mode
X
Receiver timeout interrupt
X
Modbus communication
X
Auto baud rate detection
X
Driver Enable
X
USART2
X
1. X = supported.
2. USART1_CK is not available on 20/28 pin packages. Another source of clock (for example timer output
programmed to the desired clock frequency) is needed to clock the card.
3.16
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to two SPIs are able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
One standard I2S interface (multiplexed with SPI1) supporting four different audio standards
can operate as master or slave at half-duplex communication mode. It can be configured to
transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a
specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by an 8-bit
programmable linear prescaler. When operating in master mode, it can output a clock for an
external audio component at 256 times the sampling frequency.
Refer to Table 11 for the differences between SPI1 and SPI2.
Table 11. STM32F042x SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
Rx/Tx FIFO
X
X
NSS pulse mode
X
X
I2S mode
X
TI mode
X
1. X = supported.
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STM32F042xx
3.17
Functional overview
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC
controller to wakeup the MCU from Stop mode on data reception.
3.18
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.19
Universal serial bus (USB)
The STM32F042x embeds a full-speed USB device peripheral compliant with the USB
specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP
pull-up and also battery charging detection according to Battery Charging Specification
Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with
added support for USB 2.0 Link Power Management. It has software-configurable endpoint
setting with packet memory up-to 1 KB (the last 256 bytes are used for CAN peripheral if
enabled) and suspend/resume support. It requires a precise 48 MHz clock which can be
generated from the internal main PLL (the clock source must use an HSE crystal oscillator)
or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this
oscillator can be taken from the USB data stream itself (SOF signalization) which allows
crystal-less operation.
3.20
Clock recovery system (CRS)
The STM32F042x embeds a special block which allows automatic trimming of the internal
48 MHz oscillator to guarantee its optimal accuracy over the whole device operational
range. This automatic trimming is based on the external synchronization signal, which could
be either derived from USB SOF signalization, from LSE oscillator, from an external signal
on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also
possible to combine automatic trimming with manual trimming action.
3.21
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
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Pinouts and pin descriptions
4
STM32F042xx
Pinouts and pin descriptions
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STM32F042xx
Pinouts and pin descriptions
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Pinouts and pin descriptions
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3%
3%
3%
3%
3%
3$
3$
Figure 8. UQFPN28 28-pin package (top view)
,2SLQVXSSOLHGE\9'',2
3$
3$>3$@
3$>3$@
9'',2
9''
966
3%
3$
3%
3$
3$
3$
3$
3$
%2273%
3)26&B,1
3)26&B287
1567
9''$
3$
3$
069
1. Pin pair PA11/12 can be remapped instead of pin pair PA9/10 using the SYSCFG_CFGR1 register.
30/117
DocID025832 Rev 2
STM32F042xx
Pinouts and pin descriptions
Figure 9. TSSOP20 20-pin package (top view)
3$
3$
3$>3$@
3$>3$@
9''
966
3%
3$
3$
3$
%2273%
3)26&B,1
3)26&B287
1567
9''$
3$
3$
3$
3$
3$
069
1. Pin pair PA11/12 can be remapped instead of pin pair PA9/10 using the SYSCFG_CFGR1 register.
DocID025832 Rev 2
31/117
40
Pinouts and pin descriptions
STM32F042xx
Table 12. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during and
after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TC
Standard 3.3 V I/O
RST
Notes
Pin
functions
32/117
Definition
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
reset.
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
DocID025832 Rev 2
STM32F042xx
Pinouts and pin descriptions
Table 13. STM32F042x pin definitions
UFQFPN32
UFQFPN28
TSSPOP20
1
-
-
-
-
-
VBAT
Pin
type
Notes
LQFP32
Pin name
(function after
reset)
I/O structure
WLCSP36
Pin functions
LQFP48/UFQFPN48
Pin numbers
S
-
-
-
-
OSC32_IN
(2)
-
OSC32_OUT
FTf
-
CRS_ SYNC
I2C1_SDA
OSC_IN
I/O
FTf
-
I2C1_SCL
OSC_OUT
NRST
I/O
RST
-
Device reset input / internal reset output
(active low)
15
VSSA
S
-
Analog ground
5
VDDA
S
-
Analog power supply
A6
-
-
-
-
PC13
I/O
TC
3
B6
-
-
-
-
PC14OSC32_IN
(PC14)
I/O
TC
4
C6
-
-
-
-
PC15OSC32_OUT
(PC15)
I/O
TC
5
B5
2
2
2
2
PF0-OSC_IN
(PF0)
I/O
6
C5
3
3
3
3
PF1-OSC_OUT
(PF1)
7
D5
4
4
4
4
8
D6
32
0
16
9
E5
5
5
5
F6
6
6
6
Backup power supply
WKUP2,
RTC_TAMP1,
RTC_TS,
RTC_OUT
2
10
Additional
functions
Alternate function
6
PA0
I/O
TTa
(1)
(2)
(1)
(2)
(1)
-
USART2_CTS,
TIM2_CH1_ETR,
TSC_G1_IO1
RTC_
TAMP2,
WKUP1,
ADC_IN0,
ADC_IN1
11
D4
7
7
7
7
PA1
I/O
TTa
-
USART2_RTS,
TIM2_CH2,
TSC_G1_IO2,
EVENTOUT
12
E4
8
8
8
8
PA2
I/O
TTa
-
USART2_TX,
TIM2_CH3,
TSC_G1_IO3
ADC_IN2,
WKUP4
13
F5
9
9
9
9
PA3
I/O
TTa
-
USART2_RX,
TIM2_CH4,
TSC_G1_IO4
ADC_IN3
DocID025832 Rev 2
33/117
40
Pinouts and pin descriptions
STM32F042xx
Table 13. STM32F042x pin definitions (continued)
14
15
16
17
C3
D3
E3
F4
10
11
12
13
10
11
12
13
10
11
12
13
10
11
12
13
PA4
Pin
type
I/O
PA5
I/O
PA6
I/O
PA7
I/O
TTa
TTa
TTa
TTa
Notes
Pin name
(function after
reset)
I/O structure
TSSPOP20
Pin functions
UFQFPN28
UFQFPN32
LQFP32
WLCSP36
LQFP48/UFQFPN48
Pin numbers
Alternate function
Additional
functions
-
SPI1_NSS, I2S1_WS,
TIM14_CH1,
TSC_G2_IO1,
USART2_CK
USB_NOE
ADC_IN4
-
SPI1_SCK, I2S1_CK,
CEC,
TIM2_CH1_ETR,
TSC_G2_IO2
ADC_IN5
-
SPI1_MISO, I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
TSC_G2_IO3,
EVENTOUT
ADC_IN6
-
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N,
TIM17_CH1,
TSC_G2_IO4,
EVENTOUT
ADC_IN7
ADC_IN8
18
F3
14
14
14
-
PB0
I/O
TTa
-
TIM3_CH3,
TIM1_CH2N,
TSC_G3_IO2,
EVENTOUT
19
F2
15
15
15
14
PB1
I/O
TTa
-
TIM3_CH4, TIM14_CH1,
TIM1_CH3N,
TSC_G3_IO3
ADC_IN9
20
D2
-
16
-
-
PB2
I/O
FT
-
TSC_G3_IO4
-
21
-
-
-
-
-
PB10
I/O
FTf
-
SPI2_SCK, CEC,
TSC_SYNC, TIM2_CH3,
I2C1_SCL
-
22
-
-
-
-
-
PB11
I/O
FTf
-
TIM2_CH4,
EVENTOUT,
I2C1_SDA
-
23
F1
16
0
16
15
VSS
S
-
-
Ground
24
-
-
-
17
16
VDD
S
-
-
Digital power supply
25
-
-
-
-
-
PB12
I/O
FT
-
34/117
DocID025832 Rev 2
TIM1_BKIN, SPI2_NSS,
EVENTOUT
-
STM32F042xx
Pinouts and pin descriptions
Table 13. STM32F042x pin definitions (continued)
WLCSP36
LQFP32
UFQFPN32
UFQFPN28
TSSPOP20
Pin name
(function after
reset)
I/O structure
Notes
Pin functions
LQFP48/UFQFPN48
Pin numbers
26
-
-
-
-
-
PB13
I/O
FTf
-
SPI2_SCK,
TIM1_CH1N,
I2C1_SCL
-
27
-
-
-
-
-
PB14
I/O
FTf
-
SPI2_MISO,
TIM1_CH2N,
I2C1_SDA
-
28
-
-
-
-
-
PB15
I/O
FT
-
SPI2_MOSI,
TIM1_CH3N
WKUP7,
RTC_REFIN
FT
(3)
USART1_CK,
TIM1_CH1,
EVENTOUT, MCO,
CRS_SYNC
-
FTf
(3)
USART1_TX,
TIM1_CH2,
TSC_G4_IO1,
I2C1_SCL
-
(3)
USART1_RX,
TIM1_CH3,
TIM17_BKIN,
TSC_G4_IO2,
I2C1_SDA
-
(3)
CAN_RX,
USART1_CTS,
TIM1_CH4,
COMP1_OUT,
TSC_G4_IO3,
EVENTOUT,
I2C1_SCL
USB_DM
(3)
CAN_TX,USART1_RTS,
TIM1_ETR,
TSC_G4_IO4,
EVENTOUT,
I2C1_SDA
USB_DP
IR_OUT, SWDIO
USB_NOE
-
29
30
31
32
E2
D1
C1
C2
18
19
20
21
18
19
20
21
-
19
20
-
17
18
19(4) 17(4)
20(4) 18(4)
33
A1
22
22
34
B1
23
23
21
35
-
-
-
36
E1
17
17
PA8
Pin
type
I/O
PA9
I/O
PA10
PA11
I/O
I/O
FTf
FTf
Alternate function
Additional
functions
PA12
I/O
FTf
19
PA13
I/O
FT
-
-
VSS
S
-
-
Ground
18
16
VDDIO2
S
-
-
Digital power supply
DocID025832 Rev 2
(3)
(5)
35/117
40
Pinouts and pin descriptions
STM32F042xx
Table 13. STM32F042x pin definitions (continued)
UFQFPN32
UFQFPN28
TSSPOP20
37
B2
24
24
22
20
PA14
38
39
40
41
42
A2
B3
A3
E6
C4
25
26
27
28
29
25
26
27
28
29
23
24
25
26
27
-
-
-
-
-
PA15
PB3
Pin
type
I/O
FT
I/O
I/O
PB4
I/O
PB5
I/O
PB6
I/O
FT
FT
FT
FT
FTf
Notes
LQFP32
Pin name
(function after
reset)
I/O structure
WLCSP36
Pin functions
LQFP48/UFQFPN48
Pin numbers
Alternate function
Additional
functions
(5)
USART2_TX, SWCLK
-
(3)
SPI1_NSS, I2S1_WS,
USART2_RX,
TIM2_CH1_ETR,
EVENTOUT,
USB_NOE
-
-
SPI1_SCK, I2S1_CK,
TIM2_CH2,
TSC_G5_IO1,
EVENTOUT
-
-
SPI1_MISO, I2S1_MCK,
TIM17_BKIN,
TIM3_CH1,
TSC_G5_IO2,
EVENTOUT
-
-
SPI1_MOSI, I2S1_SD,
I2C1_SMBA,
TIM16_BKIN,
TIM3_CH2
WKUP6
-
I2C1_SCL,
USART1_TX,
TIM16_CH1N,
TSC_G5_I03
-
-
(3)
43
A4
30
30
28
-
PB7
I/O
FTf
-
I2C1_SDA,
USART1_RX,
USART4_CTS,
TIM17_CH1N,
TSC_G5_IO4
44
-
-
31
-
-
PF11
BOOT0
I/O
FT
-
-
Boot memory
selection
1
PB8
BOOT0
-
I2C1_SCL, CEC,
TIM16_CH1,
TSC_SYNC,
CAN_RX
Boot memory
selection
-
I2C1_SCL, CEC,
TIM16_CH1,
TSC_SYNC,
CAN_RX
-
-
45
36/117
B4
-
31
-
-
32
1
-
-
PB8
I/O
I/O
FTf
FTf
DocID025832 Rev 2
STM32F042xx
Pinouts and pin descriptions
Table 13. STM32F042x pin definitions (continued)
Pin
type
Notes
Pin name
(function after
reset)
I/O structure
TSSPOP20
Pin functions
UFQFPN28
UFQFPN32
LQFP32
WLCSP36
LQFP48/UFQFPN48
Pin numbers
Alternate function
Additional
functions
SPI2_NSS,
I2C1_SDA, IR_OUT,
TIM17_CH1,
EVENTOUT,
CAN_TX
-
46
-
-
-
-
-
PB9
I/O
FTf
-
47
-
32
0
-
-
VSS
S
-
-
Ground
48
A5
1
1
-
-
VDD
S
-
-
Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to
the RTC domain and RTC register descriptions in the reference manual.
3. PA8, PA9, PA10, PA11, PA12, PA13, PA14 and PA15 I/Os are supplied by VDDIO2.
4. Pin pair PA11/12 can be remapped instead of pin pair PA9/10 using SYSCFG_CFGR1 register.
5. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO
pin and the internal pull-down on the SWCLK pin are activated.
DocID025832 Rev 2
37/117
40
DocID025832 Rev 2
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
PA0
-
USART2_CTS
TIM2_CH1_ETR
TSC_G1_IO1
-
-
-
-
PA1
EVENTOUT
USART2_RTS
TIM2_CH2
TSC_G1_IO2
-
-
-
-
PA2
-
USART2_TX
TIM2_CH3
TSC_G1_IO3
-
-
-
-
PA3
-
USART2_RX
TIM2_CH4
TSC_G1_IO4
-
-
-
-
PA4
SPI1_NSS, I2S1_WS
USART2_CK
USB_NOE
TSC_G2_IO1
TIM14_CH1
-
-
-
PA5
SPI1_SCK, I2S1_CK
CEC
TIM2_CH1_ETR
TSC_G2_IO2
-
-
-
-
PA6
SPI1_MISO, I2S1_MCK
TIM3_CH1
TIM1_BKIN
TSC_G2_IO3
-
TIM16_CH1
EVENTOUT
-
PA7
SPI1_MOSI, I2S1_SD
TIM3_CH2
TIM1_CH1N
TSC_G2_IO4
TIM14_CH1
TIM17_CH1
EVENTOUT
-
PA8
MCO
USART1_CK
TIM1_CH1
EVENTOUT
CRS_SYNC
-
-
-
PA9
-
USART1_TX
TIM1_CH2
TSC_G4_IO1
I2C1_SCL
MCO
-
-
PA10
TIM17_BKIN
USART1_RX
TIM1_CH3
TSC_G4_IO2
I2C1_SDA
-
-
-
PA11
EVENTOUT
USART1_CTS
TIM1_CH4
TSC_G4_IO3
CAN_RX
I2C1_SCL
-
-
PA12
EVENTOUT
USART1_RTS
TIM1_ETR
TSC_G4_IO4
CAN_TX
I2C1_SDA
-
-
PA13
SWDIO
IR_OUT
USB_NOE
-
-
-
-
-
PA14
SWCLK
USART2_TX
-
-
-
-
-
-
PA15
SPI1_NSS, I2S1_WS
USART2_RX
TIM2_CH1_ETR
EVENTOUT
-
USB_NOE
-
-
Pinouts and pin descriptions
38/117
Table 14. Alternate functions selected through GPIOA_AFR registers for port A
STM32F042xx
DocID025832 Rev 2
Pin name
AF0
AF1
AF2
AF3
AF4
AF5
PB0
EVENTOUT
TIM3_CH3
TIM1_CH2N
TSC_G3_IO2
-
-
PB1
TIM14_CH1
TIM3_CH4
TIM1_CH3N
TSC_G3_IO3
-
-
PB2
-
-
-
TSC_G3_IO4
-
-
PB3
SPI1_SCK, I2S1_CK
EVENTOUT
TIM2_CH2
TSC_G5_IO1
-
-
PB4
SPI1_MISO, I2S1_MCK
TIM3_CH1
EVENTOUT
TSC_G5_IO2
-
TIM17_BKIN
PB5
SPI1_MOSI, I2S1_SD
TIM3_CH2
TIM16_BKIN
I2C1_SMBA
-
-
PB6
USART1_TX
I2C1_SCL
TIM16_CH1N
TSC_G5_IO3
-
-
PB7
USART1_RX
I2C1_SDA
TIM17_CH1N
TSC_G5_IO4
-
-
PB8
CEC
I2C1_SCL
TIM16_CH1
TSC_SYNC
CAN_RX
-
PB9
IR_OUT
I2C1_SDA
TIM17_CH1
EVENTOUT
CAN_TX
SPI2_NSS
PB10
CEC
I2C1_SCL
TIM2_CH3
TSC_SYNC
-
SPI2_SCK
PB11
EVENTOUT
I2C1_SDA
TIM2_CH4
-
-
-
PB12
SPI2_NSS
EVENTOUT
TIM1_BKIN
-
-
-
PB13
SPI2_SCK
-
TIM1_CH1N
-
-
I2C2_SCL
PB14
SPI2_MISO
-
TIM1_CH2N
-
-
I2C2_SDA
PB15
SPI2_MOSI
-
TIM1_CH3N
-
-
-
STM32F042xx
Table 15. Alternate functions selected through GPIOB_AFR registers for port B
Pinouts and pin descriptions
39/117
Pinouts and pin descriptions
STM32F042xx
Table 16. Alternate functions selected through GPIOF_AFR registers for port F
40/117
Pin name
AF0
AF1
PF0
CRS_SYNC
I2C1_SDA
PF1
-
I2C1_SCL
DocID025832 Rev 2
STM32F042xx
5
Memory mapping
Memory mapping
Figure 10. STM32F042x memory map
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069
DocID025832 Rev 2
41/117
43
Memory mapping
STM32F042xx
Table 17. STM32F042x peripheral register boundary addresses
Bus
AHB2
AHB1
APB
42/117
Boundary address
Size
Peripheral
0x4800 1800 - 0x5FFF FFFF
~384 MB
Reserved
0x4800 1400 - 0x4800 17FF
1 KB
GPIOF
0x4800 0C00 - 0x4800 13FF
2 KB
Reserved
0x4800 0800 - 0x4800 0BFF
1 KB
GPIOC
0x4800 0400 - 0x4800 07FF
1 KB
GPIOB
0x4800 0000 - 0x4800 03FF
1 KB
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 MB
Reserved
0x4002 4000 - 0x4002 43FF
1 KB
TSC
0x4002 3400 - 0x4002 3FFF
3 KB
Reserved
0x4002 3000 - 0x4002 33FF
1 KB
CRC
0x4002 2400 - 0x4002 2FFF
3 KB
Reserved
0x4002 2000 - 0x4002 23FF
1 KB
FLASH Interface
0x4002 1400 - 0x4002 1FFF
3 KB
Reserved
0x4002 1000 - 0x4002 13FF
1 KB
RCC
0x4002 0400 - 0x4002 0FFF
3 KB
Reserved
0x4002 0000 - 0x4002 03FF
1 KB
DMA
0x4001 8000 - 0x4001 FFFF
32 KB
Reserved
0x4001 5C00 - 0x4001 7FFF
9 KB
Reserved
0x4001 5800 - 0x4001 5BFF
1 KB
DBGMCU
0x4001 4C00 - 0x4001 57FF
3 KB
Reserved
0x4001 4800 - 0x4001 4BFF
1 KB
TIM17
0x4001 4400 - 0x4001 47FF
1 KB
TIM16
0x4001 3C00 - 0x4001 43FF
2 KB
Reserved
0x4001 3800 - 0x4001 3BFF
1 KB
USART1
0x4001 3400 - 0x4001 37FF
1 KB
Reserved
0x4001 3000 - 0x4001 33FF
1 KB
SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF
1 KB
TIM1
0x4001 2800 - 0x4001 2BFF
1 KB
Reserved
0x4001 2400 - 0x4001 27FF
1 KB
ADC
0x4001 0800 - 0x4001 23FF
7 KB
Reserved
0x4001 0400 - 0x4001 07FF
1 KB
EXTI
0x4001 0000 - 0x4001 03FF
1 KB
SYSCFG + COMP
0x4000 8000 - 0x4000 FFFF
32 KB
Reserved
DocID025832 Rev 2
STM32F042xx
Memory mapping
Table 17. STM32F042x peripheral register boundary addresses (continued)
Bus
APB
Boundary address
Size
Peripheral
0x4000 7C00 - 0x4000 7FFF
1 KB
Reserved
0x4000 7800 - 0x4000 7BFF
1 KB
CEC
0x4000 7400 - 0x4000 77FF
1 KB
Reserved
0x4000 7000 - 0x4000 73FF
1 KB
PWR
0x4000 6C00 - 0x4000 6FFF
1 KB
CRS
0x4000 6800 - 0x4000 6BFF0
1 KB
Reserved
0x4000 6400 - 0x4000 67FF
1 KB
BxCAN
0x4000 6000 - 0x4000 63FF
1 KB
USB/CAN RAM
0x4000 5C00 - 0x4000 5FFF
1 KB
USB
0x4000 5800 - 0x4000 5BFF
1 KB
Reserved
0x4000 5400 - 0x4000 57FF
1 KB
I2C1
0x4000 4800 - 0x4000 53FF
3 KB
Reserved
0x4000 4400 - 0x4000 47FF
1 KB
USART2
0x4000 3C00 - 0x4000 43FF
2 KB
Reserved
0x4000 3800 - 0x4000 3BFF
1 KB
SPI2
0x4000 3400 - 0x4000 37FF
1 KB
Reserved
0x4000 3000 - 0x4000 33FF
1 KB
IWDG
0x4000 2C00 - 0x4000 2FFF
1 KB
WWDG
0x4000 2800 - 0x4000 2BFF
1 KB
RTC
0x4000 2400 - 0x4000 27FF
1 KB
Reserved
0x4000 2000 - 0x4000 23FF
1 KB
TIM14
0x4000 0800 - 0x4000 1FFF
6 KB
Reserved
0x4000 0400 - 0x4000 07FF
1 KB
TIM3
0x4000 0000 - 0x4000 03FF
1 KB
TIM2
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Electrical characteristics
STM32F042xx
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3.3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 11.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 12.
Figure 11. Pin loading conditions
Figure 12. Pin input voltage
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069
44/117
DocID025832 Rev 2
069
STM32F042xx
6.1.6
Electrical characteristics
Power supply scheme
Figure 13. Power supply scheme
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Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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94
Electrical characteristics
6.1.7
STM32F042xx
Current consumption measurement
Figure 14. Current consumption measurement scheme
,
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069
46/117
DocID025832 Rev 2
STM32F042xx
6.2
Electrical characteristics
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 18: Voltage characteristics,
Table 19: Current characteristics and Table 20: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 18. Voltage characteristics(1)
Symbol
VDD–VSS
Ratings
Min
Max
Unit
-0.3
4.0
V
-0.3
4.0
V
-0.3
4.0
V
-
0.4
V
-0.3
4.0
V
Input voltage on FT and FTf pins
VSS  0.3
VDDIOx + 4.0
V
Input voltage on TTa pins
VSS  0.3
4.0
V
Input voltage on any other pin
VSS 0.3
4.0
V
Variations between different VDD power pins
-
50
mV
Variations between all the different ground
pins
-
50
mV
External main supply voltage
VDDIO2–VSS External I/O supply voltage
VDDA–VSS
External analog supply voltage
VDD–VDDA
Allowed voltage difference for VDD > VDDA
VBAT–VSS
External backup supply voltage
VIN(2)
|VDDx|
|VSSx VSS|
VESD(HBM)
Electrostatic discharge voltage
(human body model)
see Section 6.3.12: Electrical
sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 19: Current characteristics for the maximum
allowed injected current values.
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94
Electrical characteristics
STM32F042xx
Table 19. Current characteristics
Symbol
Ratings
Max.
IVDD
Total current into sum of all VDD power lines (source)(1)
120
IVSS
(1)
-120
Total current out of sum of all VSS ground lines (sink)
IVDD(PIN)
(1)
Maximum current into each VDD power pin (source)
100
IVSS(PIN)
Maximum current out of each VSS ground pin (sink)(1)
-100
IIO(PIN)
Output current sunk by any I/O and control pin
25
Output current source by any I/O and control pin
-25
(2)
IIO(PIN)
IINJ(PIN)(3)
Total output current sunk by sum of all I/Os and control pins
80
Total output current sourced by sum of all I/Os and control pins(2)
-80
Total output current sourced by sum of all I/Os supplied by VDDIO2
-40
Injected current on FT and FTf pins
-5/+0(4)
Injected current on TC and RST pin
±5
Injected current on TTa pins(5)
IINJ(PIN)
Total injected current (sum of all I/O and control
Unit
mA
±5
pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 18: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 56: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 20. Thermal characteristics
Symbol
TSTG
TJ
48/117
Ratings
Storage temperature range
Maximum junction temperature
DocID025832 Rev 2
Value
Unit
–65 to +150
°C
150
°C
STM32F042xx
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 21. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
0
48
fPCLK
Internal APB clock frequency
0
48
VDD
Standard operating voltage
2.0
3.6
V
1.65
3.6
V
VDD
3.6
2.4
3.6
1.65
3.6
TC and RST I/O
-0.3
VDDIOx+0.3
TTa I/O
-0.3
VDDA+0.3
VDDIO2
VDDA
VBAT
VIN
Must not be supplied if VDD
is not present
I/O supply voltage
Analog operating voltage
(ADC not used)
Must have a potential equal
to or higher than VDD
Analog operating voltage
(ADC used)
Backup operating voltage
I/O input voltage
FT and FTf I/O
PD
Power dissipation at TA = 85 °C
for suffix 6 or TA = 105 °C for
suffix 7(2)
-0.3
364
UFQFPN48
-
606
WLCSP36
-
313
LQFP32
-
351
UFQFPN32
-
526
UFQFPN28
-
170
TSSOP20
-
263
–40
85
–40
105
Maximum power dissipation
Ambient temperature for the
suffix 7 version
Maximum power dissipation
–40
105
Low power dissipation(3)
–40
125
Suffix 6 version
–40
105
Suffix 7 version
–40
125
Junction temperature range
V
5.5
-
Low power
V
(1)
Ambient temperature for the
suffix 6 version
TA
TJ
V
LQFP48
dissipation(3)
MHz
mW
°C
°C
°C
1. To sustain a voltage higher than VDDIOx+0.3 V, the internal pull-up/pull-down resistors must be disabled.
2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. See Section 7.2: Thermal characteristics.
3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.2:
Thermal characteristics).
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94
Electrical characteristics
6.3.2
STM32F042xx
Operating conditions at power-up / power-down
The parameters given in Table 22 are derived from tests performed under the ambient
temperature condition summarized in Table 21.
Table 22. Operating conditions at power-up / power-down
Symbol
Parameter
VDD rise time rate
tVDD
-
VDD fall time rate
VDDA rise time rate
tVDDA
6.3.3
Conditions
-
VDDA fall time rate
Min
Max
0

20

0

20

Unit
μs/V
Embedded reset and power control block characteristics
The parameters given in Table 23 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 23. Embedded reset and power control block characteristics
Symbol
VPOR/PDR(1)
VPDRhyst
tRSTTEMPO(4)
Parameter
Power on/power down
reset threshold
Conditions
Min
Typ
Max
Unit
Falling edge(2)
1.80
1.88
1.96(3)
V
1.84(3)
1.92
2.00
V
-
40
-
mV
1.50
2.50
4.50
ms
Rising edge
PDR hysteresis
Reset temporization
1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector
monitors only VDD.
2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
3. Data based on characterization results, not tested in production.
4. Guaranteed by design, not tested in production.
Table 24. Programmable voltage detector characteristics
Symbol
50/117
Parameter
VPVD0
PVD threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
Conditions
Min
Typ
Max
Unit
Rising edge
2.1
2.18
2.26
V
Falling edge
2
2.08
2.16
V
Rising edge
2.19
2.28
2.37
V
Falling edge
2.09
2.18
2.27
V
Rising edge
2.28
2.38
2.48
V
Falling edge
2.18
2.28
2.38
V
Rising edge
2.38
2.48
2.58
V
Falling edge
2.28
2.38
2.48
V
DocID025832 Rev 2
STM32F042xx
Electrical characteristics
Table 24. Programmable voltage detector characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Rising edge
2.47
2.58
2.69
V
Falling edge
2.37
2.48
2.59
V
Rising edge
2.57
2.68
2.79
V
Falling edge
2.47
2.58
2.69
V
Rising edge
2.66
2.78
2.9
V
Falling edge
2.56
2.68
2.8
V
Rising edge
2.76
2.88
3
V
Falling edge
2.66
2.78
2.9
V
PVD hysteresis
-
100
-
mV
PVD current consumption
-
0.15
0.26(1)
μA
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
VPVD7
PVD threshold 7
VPVDhyst
(1)
IDD(PVD)
Conditions
1. Guaranteed by design, not tested in production.
6.3.4
Embedded reference voltage
The parameters given in Table 25 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 25. Embedded internal reference voltage
Symbol
Parameter
VREFINT
Internal reference voltage
tS_vrefint
ADC sampling time when
reading the internal
reference voltage
VREFINT
Internal reference voltage
spread over the
temperature range
TCoeff
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.16
1.2
1.25
V
1.16
1.2
1.24(1)
V
4(2)
-
-
μs
-
-
10(2)
mV
- 100(2)
-
100(2) ppm/°C
–40 °C < TA < +85 °C
VDDA = 3 V
Temperature coefficient
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
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94
Electrical characteristics
6.3.5
STM32F042xx
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 14: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:

All I/O pins are in analog input mode

All peripherals are disabled except when explicitly mentioned

The Flash memory access time is adjusted to the fHCLK frequency:
–
0 wait state and Prefetch OFF from 0 to 24 MHz
–
1 wait state and Prefetch ON above 24 MHz

When the peripherals are enabled fPCLK = fHCLK
The parameters given in Table 26 to Table 30 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Parameter
Symbol
Table 26. Typical and maximum current consumption from VDD supply at VDD = 3.6 V
All peripherals enabled(1)
Conditions
IDD
Supply current in Run mode,
code executing from Flash
HSI48
HSE bypass,
PLL on
HSE bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
52/117
fHCLK
All peripherals disabled
Max @ TA(2)
Max @ TA(2)
Unit
Typ
Typ
25 °C
85 °C
105 °C
25 °C
85 °C
105 °C
48 MHz
20.3
23.2
23.4
24.6
12.7
14.4
14.4
14.7
48 MHz
20.2
22.9
23.0
23.9
12.6
14.1
14.3
14.4
32 MHz
14.0
16.0
16.1
16.7
8.7
9.5
9.7
10.3
24 MHz
11.0
13.5
13.7
13.8
6.9
7.6
7.8
8.2
8 MHz
3.9
5.2
5.3
5.6
2.6
3.1
3.2
3.3
1 MHz
0.9
1.3
1.5
1.8
0.7
1.0
1.1
1.3
48 MHz
20.5
23.1
23.3
23.6
12.8
14.6
14.6
15.0
32 MHz
14.3
15.6
15.9
17.0
8.6
9.5
9.7
10.0
24 MHz
11.2
13.6
13.8
14.8
6.9
7.4
7.5
7.7
8 MHz
4.1
5.2
5.3
5.6
2.6
3.1
3.1
3.3
DocID025832 Rev 2
mA
STM32F042xx
Electrical characteristics
Parameter
Symbol
Table 26. Typical and maximum current consumption from VDD supply at VDD = 3.6 V (continued)
All peripherals enabled(1)
Conditions
Supply current in Run mode,
code executing from RAM
HSI48
Supply current in Sleep mode,
code executing from Flash or RAM
IDD
fHCLK
48 MHz
All peripherals disabled
Max @ TA(2)
Max @ TA(2)
19.3
Unit
Typ
Typ
25 °C
85 °C
105 °C
21.9
22.1
23.7
11.9
105 °C
13.4
13.6
13.7
13.3
13.5
13.7(3)
16.0
7.9
8.8
8.9
9.7
13.0
13.4
6.2
8.0
8.2
8.3
4.1
4.3
4.4
2.0
2.1
2.1
2.5
0.8
0.9
0.9
1.1
0.4
0.5
0.6
0.8
48 MHz
19.5
22.0
22.1
22.5
11.8
13.6
13.8
13.9
32 MHz
13.5
16.3
16.4
16.6
8.0
8.8
9.1
9.9
24 MHz
10.5
12.8
13.0
13.8
6.5
8.0
8.1
8.4
HSI clock,
PLL off
8 MHz
3.7
4.7
5.0
5.3
2.1
2.3
2.4
3.0
HSI48
48 MHz
12.4
15.1
16.3
16.7
3.0
3.2
3.3
3.4
48 MHz
12.3
15.0(3)
16.0
16.2(3)
2.9
3.2(3)
3.3
3.4(3)
32 MHz
8.5
10.6
11.2
11.7
1.9
2.1
2.2
2.5
24 MHz
6.5
8.1
8.5
8.7
1.6
1.8
1.8
1.9
8 MHz
2.3
3.0
3.1
3.2
0.7
0.8
0.8
0.9
1 MHz
0.4
0.4
0.4
0.6
0.1
0.3
0.3
0.4
48 MHz
12.4
15.3
15.7
15.9
3.0
3.0
3.2
3.4
32 MHz
8.6
10.7
11.3
11.6
2.1
2.2
2.2
2.5
24 MHz
6.6
8.4
8.7
8.9
1.6
1.6
1.7
1.9
8 MHz
2.4
3.2
3.4
3.6
0.6
0.8
0.9
1.0
HSE bypass,
PLL on
HSE bypass,
PLL off
HSI clock,
PLL on
HSE bypass,
PLL on
HSE bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
22.0
48 MHz
19.2
32 MHz
13.4
15.8
15.9
24 MHz
10.3
12.6
8 MHz
3.6
1 MHz
(3)
85 °C
11.7
21.8
(3)
25 °C
22.1
(3)
mA
1. USB is kept disabled as this IP functions only with a 48 MHz clock.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
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94
Electrical characteristics
STM32F042xx
Table 27. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V
Symbol
Parameter
Conditions
(1)
HSI48
IDDA
Supply
current in
Run or
Sleep
mode,
code
executing
from
Flash or
RAM
HSE
bypass,
PLL on
HSE
bypass,
PLL off
HSI clock,
PLL on
HSI clock,
PLL off
fHCLK
VDDA = 3.6 V
Max @ TA(2)
Typ
25 °C
85 °C
105 °C
309
325
332
342
48 MHz
148
167(3)
176
32 MHz
102
119
124
126
111
24 MHz
80
95
99
100
8 MHz
2.7
3.7
4.2
1 MHz
2.7
3.7
48 MHz
220
32 MHz
48 MHz
Max @ TA(2)
Typ
Unit
25 °C 85 °C 105 °C
338
344
193
197(3)
128
135
137
88
102
106
108
4.5
3.5
4.7
5.2
5.5
4.2
4.2
3.6
4.7
5.2
5.5
242
251
254
242
264
275
279
173
193
200
202
191
211
219
221
24 MHz
151
169
175
177
167
184
191
193
8 MHz
72
82
85
85
82
92
95
95
179
(3)
317
161
334
181
(3)
μA
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash or RAM. Furthermore, when the PLL is off, IDDA is independent from the
frequency.
2. Data based on characterization results, not tested in production unless otherwise specified.
3. Data based on characterization results and tested in production (using one common test limit for sum of IDD and IDDA).
54/117
DocID025832 Rev 2
STM32F042xx
Electrical characteristics
= 2.4 V
= 2.7 V
= 3.0 V
= 3.3 V
= 3.6 V
14.3
14.5
14.6
14.7
14.8
14.9
21.0
47.0
64.0
2.9
3.1
3.2
3.3
3.4
3.5
6.5
32.0
44.0
LSI ON and IWDG
ON
0.8
0.9
1.1
1.2
1.3
1.5
-
-
-
LSI OFF and IWDG
OFF
0.6
0.7
0.8
0.9
1.0
1.1
2.0
2.5
3.0
Regulator in
stop mode, all
oscillators
OFF
2.0
2.1
2.2
2.4
2.5
2.7
3.5
3.5
4.5
Regulator in
low-power
mode, all
oscillators
OFF
2.0
2.1
2.2
2.4
2.5
2.7
3.5
3.5
4.5
LSI ON and
IWDG ON
2.4
2.6
2.8
3.0
3.1
3.4
-
-
-
LSI OFF and
IWDG OFF
1.9
2.0
2.1
2.3
2.4
2.5
3.4
3.5
4.5
Regulator in
stop mode, all
oscillators
OFF
1.3
1.3
1.3
1.4
1.4
1.5
-
-
-
Regulator in
low-power
mode, all
oscillators
OFF
1.3
1.3
1.3
1.4
1.4
1.5
-
-
-
LSI ON and
IWDG ON
1.7
1.8
1.8
2.0
2.1
2.2
-
-
-
LSI OFF and
IWDG OFF
1.1
1.2
1.2
1.3
1.3
1.4
-
-
-
Supply
current in
Standby
mode
Supply
current in
Stop mode
Supply
current in
Standby
mode
VDDA monitoring ON
Supply
current in
Stop mode Regulator in lowpower mode, all
oscillators OFF
Supply
current in
Stop mode
Supply
current in
Standby
mode
VDDA monitoring OFF
IDDA
TA = TA = TA =
25°C 85°C 105°C
Unit
= 2.0 V
Conditions
Regulator in stop
mode, all
oscillators OFF
IDD
Max(1)
Typ @VDD (VDD = VDDA)
Parameter
Symbol
Table 28. Typical and maximum consumption in Stop and Standby modes
μA
1. Data based on characterization results, not tested in production unless otherwise specified.
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94
Electrical characteristics
STM32F042xx
Table 29. Typical and maximum current consumption from the VBAT supply
Max(1)
= 2.7 V
= 3.3 V
= 3.6 V
RTC
domain
IDD_VBAT
supply
current
= 2.4 V
Parameter
= 1.8 V
Symbol
= 1.65 V
Typ @ VBAT
TA =
25 °C
LSE & RTC ON; “Xtal
mode”: lower driving
capability;
LSEDRV[1:0] = '00'
0.5
0.5
0.6
0.7
0.9
1.1
1.2
LSE & RTC ON; “Xtal
mode” higher driving
capability;
LSEDRV[1:0] = '11'
0.8
Conditions
TA =
TA =
85 °C 105 °C
1.5
Unit
2.0
μA
0.9
1.1
1.2
1.4
1.5
1.6
2.0
2.6
1. Data based on characterization results, not tested in production.
Typical current consumption
The MCU is placed under the following conditions:

VDD = VDDA = 3.3 V

All I/O pins are in analog input configuration

The Flash access time is adjusted to fHCLK frequency:
–
0 wait state and Prefetch OFF from 0 to 24 MHz
–
1 wait state and Prefetch ON above 24 MHz

When the peripherals are enabled, fPCLK = fHCLK

PLL is used for frequencies greater than 8 MHz

AHB prescaler of 2, 4, 8 and 16 is used for the frequencies 4 MHz, 2 MHz, 1 MHz and
500 kHz respectively
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STM32F042xx
Electrical characteristics
Table 30. Typical current consumption, code executing from Flash, running from HSE
8 MHz crystal
Typical consumption
in Run mode
Symbol
IDD
IDDA
Parameter
Current
consumption from
VDD supply
Current
consumption from
VDDA supply
Typical consumption
in Sleep mode
fHCLK
Unit
Peripherals
enabled
Peripherals
disabled
Peripherals
enabled
Peripherals
disabled
48 MHz
20.7
12.8
12.3
3.4
36 MHz
15.9
9.9
9.5
2.7
32 MHz
14.3
9.0
8.5
2.5
24 MHz
11.0
7.1
6.6
2.1
16 MHz
7.7
5.0
4.7
1.6
8 MHz
4.3
3.0
2.7
1.2
4 MHz
2.6
2.0
1.7
0.9
2 MHz
1.8
1.5
1.2
0.8
1 MHz
1.4
1.2
1.0
0.8
500 kHz
1.2
1.1
0.8
0.7
48 MHz
163.3
36 MHz
124.3
32 MHz
111.9
24 MHz
87.1
16 MHz
62.5
8 MHz
2.5
4 MHz
2.5
2 MHz
2.5
1 MHz
2.5
500 kHz
2.5
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μA
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Electrical characteristics
STM32F042xx
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 50: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 32: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx  f SW  C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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STM32F042xx
Electrical characteristics
Table 31. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDDIOx = 3.3 V
C =CINT
VDDIOx = 3.3 V
CEXT = 0 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 10 pF
C = CINT + CEXT+ CS
ISW
I/O current
consumption
VDDIOx = 3.3 V
CEXT = 22 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 33 pF
C = CINT + CEXT+ CS
VDDIOx = 3.3 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
VDDIOx = 2.4 V
CEXT = 47 pF
C = CINT + CEXT+ CS
C = Cint
I/O toggling
frequency (fSW)
Typ
4 MHz
0.07
8 MHz
0.15
16 MHz
0.31
24 MHz
0.53
48 MHz
0.92
4 MHz
0.18
8 MHz
0.37
16 MHz
0.76
24 MHz
1.39
48 MHz
2.188
4 MHz
0.32
8 MHz
0.64
16 MHz
1.25
24 MHz
2.23
48 MHz
4.442
4 MHz
0.49
8 MHz
0.94
16 MHz
2.38
24 MHz
3.99
4 MHz
0.64
8 MHz
1.25
16 MHz
3.24
24 MHz
5.02
4 MHz
0.81
8 MHz
1.7
16 MHz
3.67
4 MHz
0.66
8 MHz
1.43
16 MHz
2.45
24 MHz
4.97
Unit
mA
1. CS = 7 pF (estimated value).
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Electrical characteristics
STM32F042xx
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 32. The MCU is placed
under the following conditions:

All I/O pins are in analog mode

All peripherals are disabled unless otherwise mentioned

The given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on

Ambient operating temperature and supply voltage conditions summarized in Table 18:
Voltage characteristics
Table 32. Peripheral current consumption
Peripheral
AHB
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Typical consumption at 25 °C
BusMatrix(1)
2.2
CRC
1.9
DMA
5.1
Flash interface
15.0
GPIOA
8.2
GPIOB
7.7
GPIOC
2.1
GPIOF
1.8
SRAM
1.1
TSC
4.9
ALL AHB Peripherals
50.7
DocID025832 Rev 2
Unit
μA/MHz
STM32F042xx
Electrical characteristics
Table 32. Peripheral current consumption (continued)
Peripheral
Typical consumption at 25 °C
(2)
APB
APB-Bridge
2.1
ADC(3)
4.7
CAN
13.8
CEC
2.4
CRS
1.8
DEBUG (MCU debug feature)
1.1
I2C1
4.5
PWR
2.3
SPI1
9.4
SPI2
6.5
SYSCFG
2.7
TIM1
16.0
TIM2
17.6
TIM3
12.5
TIM14
6.4
TIM16
7.9
TIM17
7.8
USART1
18.6
USART2
6.5
USB
6.6
WWDG
2.2
ALL APB Peripherals
Unit
μA/MHz
153.8
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. The APB Bridge is automatically active when at least one peripheral is ON on the Bus.
3. The power consumption of the analog part (IDDA) of peripherals such as ADC is not included. Refer to the
tables of characteristics in the subsequent sections.
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Electrical characteristics
6.3.6
STM32F042xx
Wakeup time from low-power mode
The wakeup times given in Table 33 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 21: General operating conditions.
Table 33. Low-power mode wakeup timings
Typ @VDD = VDDA
Symbol
Parameter
Conditions
Max Unit
= 2.0 V = 2.4 V = 2.7 V
tWUSTOP
Wakeup from Stop
mode
Wakeup from
tWUSTANDBY
Standby mode
tWUSLEEP
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=3V
= 3.3 V
Regulator in run
mode
3.2
3.1
2.9
2.9
2.8
5
Regulator in low
power mode
7.0
5.8
5.2
4.9
4.6
9
μs
60.4
Wakeup from Sleep
mode
55.6
53.5
52
4 SYSCLK cycles
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51
-
STM32F042xx
6.3.7
Electrical characteristics
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 15: High-speed external clock
source AC timing diagram.
Table 34. High-speed external user clock characteristics
Symbol
Parameter(1)
Conditions
Min
Typ
Max
Unit
fHSE_ext
User external clock source frequency
-
-
8
32
MHz
VHSEH
OSC_IN input pin high level voltage
-
0.7 VDDIOx
-
VDDIOx
VHSEL
OSC_IN input pin low level voltage
-
VSS
-
0.3 VDDIOx
-
15
-
-
tw(HSEH)
OSC_IN high or low time
tw(HSEL)
tr(HSE)
tf(HSE)
V
ns
OSC_IN rise or fall time
-
-
-
20
1. Guaranteed by design, not tested in production.
Figure 15. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+
9+6(/
WU+6(
WI+6(
WZ+6(/
W
7+6(
069
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Electrical characteristics
STM32F042xx
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 6.3.14. However,
the recommended clock input waveform is shown in Figure 16.
Table 35. Low-speed external user clock characteristics
Parameter(1)
Symbol
Conditions
Min
Typ
Max
Unit
kHz
fLSE_ext
User external clock source frequency
-
32.768
1000
VLSEH
OSC32_IN input pin high level voltage
0.7 VDDIOx
-
VDDIOx
VLSEL
OSC32_IN input pin low level voltage
VSS
-
0.3 VDDIOx
450
-
-
tw(LSEH)
OSC32_IN high or low time
tw(LSEL)
tr(LSE)
tf(LSE)
V
ns
OSC32_IN rise or fall time
-
-
50
1. Guaranteed by design, not tested in production.
Figure 16. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+
9/6(/
WU/6(
WI/6(
WZ/6(/
W
7/6(
069
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DocID025832 Rev 2
STM32F042xx
Electrical characteristics
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 36. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 36. HSE oscillator characteristics
Symbol
fOSC_IN
Parameter
Conditions(1)
Min(2)
Typ
Max(2)
Unit
4
8
32
MHz
-
200
-
k
Oscillator frequency
Feedback resistor
RF
(3)
During startup
IDD
HSE current consumption
gm
tSU(HSE)
Oscillator transconductance
(4)
Startup time
-
8.5
VDD = 3.3 V,
Rm = 30 ,
CL = 10 pF@8 MHz
-
0.4
-
VDD = 3.3 V,
Rm = 45 ,
CL = 10 pF@8 MHz
-
0.5
-
VDD = 3.3 V,
Rm = 30 ,
CL = 5 pF@32 MHz
-
0.8
-
VDD = 3.3 V,
Rm = 30 ,
CL = 10 pF@32 MHz
-
1
-
VDD = 3.3 V,
Rm = 30 ,
CL = 20 pF@32 MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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94
Electrical characteristics
STM32F042xx
Figure 17. Typical application with an 8 MHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
I+6(
26&B,1
0+ ]
UHVRQDWRU
&/
5(;7 5)
%LDV
FRQWUROOHG
JDLQ
26&B287
069
1. REXT value depends on the crystal characteristics.
66/117
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STM32F042xx
Electrical characteristics
Low-speed external clock generated from a crystal resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 37. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 37. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
IDD
gm
Parameter
LSE current consumption
Oscillator
transconductance
tSU(LSE)(3) Startup time
Conditions(1)
Min(2)
Typ
Max(2) Unit
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]= 01
medium low driving capability
-
-
1
LSEDRV[1:0] = 10
medium high driving capability
-
-
1.3
LSEDRV[1:0]=11
higher driving capability
-
-
1.6
LSEDRV[1:0]=00
lower driving capability
5
-
-
LSEDRV[1:0]= 01
medium low driving capability
8
-
-
LSEDRV[1:0] = 10
medium high driving capability
15
-
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
VDDIOx is stabilized
-
2
-
μA
μA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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94
Electrical characteristics
STM32F042xx
Figure 18. Typical application with a 32.768 kHz crystal
5HVRQDWRUZLWK
LQWHJUDWHGFDSDFLWRUV
&/
I/6(
26&B,1
'ULYH
SURJUDPPDEOH
DPSOLILHU
N+ ]
UHVRQDWRU
26&B28 7
&/
069
Note:
68/117
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DocID025832 Rev 2
STM32F042xx
6.3.8
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 38 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI) RC oscillator
Table 38. HSI oscillator characteristics(1)
Symbol
fHSI
TRIM
DuCy(HSI)
ACCHSI
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
-
8
-
MHz
HSI user trimming step
-
-
1(2)
%
Duty cycle
(2)
45
Accuracy of the HSI
oscillator (factory
calibrated)
-
55
(2)
%
%
TA = –40 to 105 °C
–3.8(3)
-
4.6(3)
TA = –10 to 85 °C
–2.9(3)
-
2.9(3)
%
TA = 0 to 70 °C
–2.3(3)
-
2.2(3)
%
–1
-
1
%
TA = 25 °C
tsu(HSI)
HSI oscillator startup
time
1(2)
-
2(2)
μs
IDDA(HSI)
HSI oscillator power
consumption
-
80
100(2)
μA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 19. HSI oscillator accuracy characterization results
-!8
-).
4; #=
!
-36
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Electrical characteristics
STM32F042xx
High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC)
Table 39. HSI14 oscillator characteristics(1)
Symbol
fHSI14
TRIM
Parameter
Conditions
Min
Typ
-
14
Frequency
HSI14 user-trimming step
-
DuCy(HSI14) Duty cycle
45
Accuracy of the HSI14
oscillator (factory calibrated)
TA = –10 to 85 °C
TA = 25 °C
tsu(HSI14)
IDDA(HSI14)
HSI14 oscillator startup time
MHz
-
1
55
%
(2)
%
(3)
-
5.1
%
–3.2(3)
-
3.1(3)
%
–2.5
-
(3)
2.3
%
–1
-
1
%
-
(2)
μs
1
HSI14 oscillator power
consumption
(2)
(3)
(3)
TA = 0 to 70 °C
Unit
-
(2)
TA = –40 to 105 °C –4.2
ACCHSI14
Max
(2)
-
100
2
150(2)
μA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 20. HSI14 oscillator accuracy characterization results
-!8
-).
4; #=
!
-36
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Electrical characteristics
High-speed internal 48 MHz (HSI48) RC oscillator
Table 40. HSI48 oscillator characteristics(1)
Symbol
fHSI48
TRIM
Parameter
Conditions
Frequency
HSI48 user-trimming step
Unit
-
48
-
MHz
TA = –10 to 85 °C
Accuracy of the HSI48
oscillator (factory calibrated) T = 0 to 70 °C
A
(2)
(2)
0.14
-
(2)
%
(2)
%
(3)
%
0.2
55
(3)
-
4.7
-4.1(3)
-
3.7(3)
%
-
(3)
%
-4.9
-3.8
TA = 25 °C
IDDA(HSI48)
Max
45
TA = –40 to 105 °C
tsu(HSI48)
Typ
0.09
DuCy(HSI48) Duty cycle
ACCHSI48
Min
(3)
-2.8
3.4
-
2.9
%
(2)
μs
HSI48 oscillator startup time
-
-
6
HSI48 oscillator power
consumption
-
312
350(2)
μA
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
Figure 21. HSI48 oscillator accuracy characterization results
-!8
-).
4; #=
!
-36
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Electrical characteristics
STM32F042xx
Low-speed internal (LSI) RC oscillator
Table 41. LSI oscillator characteristics(1)
Symbol
fLSI
tsu(LSI)
Parameter
Min
Typ
Max
Unit
30
40
50
kHz
LSI oscillator startup time
-
-
85
μs
LSI oscillator power consumption
-
0.75
1.2
μA
Frequency
(2)
IDDA(LSI)(2)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.9
PLL characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 21: General operating
conditions.
Table 42. PLL characteristics
Value
Symbol
fPLL_IN
fPLL_OUT
tLOCK
JitterPLL
Parameter
Unit
Min
Typ
Max
1(2)
8.0
24(2)
MHz
PLL input clock duty cycle
40
(2)
-
60(2)
%
PLL multiplier output clock
16(2)
-
48
MHz
PLL lock time
-
-
200(2)
μs
Cycle-to-cycle jitter
-
-
300(2)
ps
PLL input clock(1)
1. Take care to use the appropriate multiplier factors to obtain PLL input clock values compatible with the
range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
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6.3.10
Electrical characteristics
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 43. Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA–40 to +105 °C
40
53.5
60
μs
Page (1 KB) erase time
TA –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA –40 to +105 °C
20
-
40
ms
IDD
Supply current
Write mode
-
-
10
mA
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design, not tested in production.
Table 44. Flash memory endurance and data retention
Symbol
NEND
Parameter
Endurance
Conditions
TA = –40 to +105 °C
1
tRET
Data retention
kcycle(2)
at TA = 85 °C
1 kcycle(2) at TA = 105 °C
(2)
10 kcycles
at TA = 55 °C
Min(1)
Unit
10
kcycles
30
10
Years
20
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
6.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:

Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
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Electrical characteristics
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Table 45. EMS characteristics
Symbol
Parameter
Level/
Class
Conditions
VFESD
VDD 3.3 V, LQFP48, TA +25 °C,
Voltage limits to be applied on any I/O pin
fHCLK 48 MHz,
to induce a functional disturbance
conforming to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, LQFP48, TA +25°C,
fHCLK 48 MHz,
conforming to IEC 61000-4-4
4B
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical Data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Symbol Parameter
SEMI
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Conditions
Monitored
frequency band
0.1 to 30 MHz
VDD 3.6 V, TA 25 °C,
30 to 130 MHz
LQFP48 package
Peak level
compliant with
130 MHz to 1 GHz
IEC 61967-2
EMI Level
DocID025832 Rev 2
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
-9
9
dBμV
17
3
-
STM32F042xx
6.3.12
Electrical characteristics
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
Electrostatic discharge
TA +25 °C, conforming
voltage (human body model) to JESD22-A114
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA +25 °C, conforming
to ANSI/ESD STM5.3.1
Class
Maximum
value(1)
2
2000
Unit
V
II
500
1. Data based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
LU
6.3.13
Parameter
Static latch-up class
Conditions
TA +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIOx (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
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Electrical characteristics
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Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 μA/+0 μA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 49.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
Table 49. I/O current injection susceptibility
Functional
susceptibility
Symbol
Description
Unit
Negative Positive
injection injection
IINJ
6.3.14
Injected current on PA12 pin
-0
+5
Injected current on PA9, PB3, PB13, PF11 pins with
induced leakage current on adjacent pins less than 50 μA
-5
NA
Injected current on PB0, PB1 and all other FT and FTf pins
-5
NA
Injected current on all other TC, TTa and RST pins
-5
+5
mA
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under the conditions summarized in Table 21: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
Table 50. I/O static characteristics
Symbol
VIL
Parameter
Low level input
voltage
Conditions
Min
Typ
Max
TC and TTa I/O
-
-
0.3 VDDIOx+0.07(1)
FT and FTf I/O
-
-
0.475 VDDIOx–0.2(1)
All I/Os
-
-
0.3 VDDIOx
-
-
0.5 VDDIOx+0.2(1)
-
-
0.7 VDDIOx
-
-
-
200(1)
-
-
100(1)
-
TC and TTa I/O
VIH
High level input
voltage
FT and FTf I/O
All I/Os
Vhys
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Schmitt trigger
hysteresis
TC and TTa I/O
FT and FTf I/O
0.445
VDDIOx+0.398(1)
DocID025832 Rev 2
Unit
V
V
mV
STM32F042xx
Electrical characteristics
Table 50. I/O static characteristics (continued)
Symbol
Ilkg
RPU
Parameter
Input leakage
current(2)
Weak pull-up
equivalent resistor
(4)
RPD
Weak pull-down
equivalent
resistor(4)
CIO
I/O pin capacitance
Conditions
Min
Typ
Max
Unit
TC, FT and FTf I/O
TTa in digital mode
VSS  VIN  VDDIOx
-
-
 0.1

TTa in digital mode
VDDIOx  VIN  VDDA
-
-
1
TTa in analog mode
VSS  VIN  VDDA
-
-
 0.2

FT and FTf I/O (3)
VDDIOx  VIN  5 V
-
-
10
VIN VSS
25
40
55
k
VIN VDDIOx
25
40
55
k
-
5
-
pF
μA
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 49:
I/O current injection susceptibility.
3. To sustain a voltage higher than VDDIOx + 0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
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All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for
5 V tolerant I/Os. The following curves are design simulation results, not tested in
production.
Figure 22. TC and TTa I/O input characteristics
3
VIN (V)
2.5
TESTED RANGE
TTL standard requirement
2
1.5
UNDEFINED INPUT RANGE
1
TTL standard requirement
0.5
TESTED RANGE
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDDIOx
(V)
MS32130V3
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Electrical characteristics
Figure 23. Five volt tolerant (FT and FTf) I/O input characteristics
3
VIN (V)
2.5
TESTED RANGE
TTL standard requirement
2
1.5
1
TTL standard requirement
0.5
TESTED RANGE
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDDIOx (V)
MS32131V3
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STM32F042xx
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:

The sum of the currents sourced by all the I/Os on VDDIOx, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 18: Voltage characteristics).

The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see
Table 18: Voltage characteristics).
Output voltage levels
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT, TTa or
TC unless otherwise specified).
Table 51. Output voltage characteristics(1)
Symbol
Parameter
VOL
Output low level voltage for an I/O pin
VOH
Output high level voltage for an I/O pin
VOL
Output low level voltage for an I/O pin
VOH
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOL(3)
Output low level voltage for an I/O pin
VOH(3)
Output high level voltage for an I/O pin
VOLFm+(3)
Output low level voltage for an FTf I/O pin in
Fm+ mode
Conditions
Min
Max
CMOS port(2)
|IIO| = 8 mA
VDDIOx  2.7 V
-
0.4
VDDIOx–0.4
-
-
0.4
2.4
-
-
1.3
VDDIOx–1.3
-
-
0.4
VDDIOx–0.4
-
-
0.4
V
VDDIOx–0.4
-
V
|IIO| = 20 mA
VDDIOx  2.7 V
-
0.4
V
|IIO| = 10 mA
-
0.4
V
TTL port(2)
|IIO| = 8 mA
VDDIOx  2.7 V
|IIO| = 20 mA
VDDIOx  2.7 V
|IIO| = 6 mA
VDDIOx  2 V
|IIO| = 4 mA
Unit
V
V
V
V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 52, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 21: General
operating conditions.
Table 52. I/O AC characteristics(1)(2)
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
Min
Max
Unit
-
2
MHz
-
125
-
125
-
1
-
125
-
125
-
10
-
25
-
25
-
4
-
62.5
-
62.5
CL = 30 pF, VDDIOx  2.7 V
-
50
CL = 50 pF, VDDIOx  2.7 V
-
30
CL = 50 pF, 2 V VDDIOx  2.7 V
-
20
CL = 50 pF, VDDIOx  2 V
-
10
CL = 30 pF, VDDIOx  2.7 V
-
5
CL = 50 pF, VDDIOx  2.7 V
-
8
CL = 50 pF, 2 V VDDIOx  2.7 V
-
12
CL = 50 pF, VDDIOx  2 V
-
25
CL = 30 pF, VDDIOx  2.7 V
-
5
CL = 50 pF, VDDIOx  2.7 V
-
8
CL = 50 pF, 2 V VDDIOx  2.7 V
-
12
CL = 50 pF, VDDIOx  2 V
-
25
fmax(IO)out Maximum frequency(3)
x0
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF, VDDIOx  2 V
fmax(IO)out Maximum frequency(3)
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF, VDDIOx  2 V
fmax(IO)out Maximum frequency(3)
01
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF, VDDIOx  2 V
fmax(IO)out Maximum frequency(3)
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF, VDDIOx  2 V
fmax(IO)out Maximum frequency(3)
11
tf(IO)out
tr(IO)out
Output fall time
Output rise time
DocID025832 Rev 2
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
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Electrical characteristics
STM32F042xx
Table 52. I/O AC characteristics(1)(2) (continued)
OSPEEDRy
[1:0] value(1)
Symbol
Parameter
Conditions
fmax(IO)out Maximum frequency(3)
Fm+
configuration
(4)
tf(IO)out
Output fall time
tr(IO)out
Output rise time
CL = 50 pF, VDDIOx  2 V
fmax(IO)out Maximum frequency(3)
CL = 50 pF, VDDIOx  2 V
tf(IO)out
Output fall time
tr(IO)out
Output rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
Min
Max
Unit
-
2
MHz
-
12
-
34
-
0.5
-
16
-
44
10
-
ns
MHz
ns
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32F0xxxx RM0091 reference manual for a
description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 24.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the STM32F0xxxx reference manual RM0091
for a detailed description of Fm+ I/O configuration.
Figure 24. I/O AC characteristics definition
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6.3.15
NRST pin characteristics
The NRST pin input driver uses the CMOS technology. It is connected to a permanent pullup resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 21: General operating conditions.
Table 53. NRST pin characteristics
Symbol
Parameter
VIL(NRST)
VIH(NRST)
82/117
Conditions
Min
Typ
Max
NRST input low level voltage
-
-
0.3 VDD+0.07(1)
NRST input high level voltage
0.445 VDD+0.398(1)
-
-
DocID025832 Rev 2
Unit
V
STM32F042xx
Electrical characteristics
Table 53. NRST pin characteristics (continued)
Symbol
Parameter
Conditions
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
RPU
Weak pull-up equivalent
resistor(2)
VF(NRST)
NRST input filtered pulse
VIN VSS
VNF(NRST) NRST input not filtered pulse
Min
Typ
Max
Unit
-
200
-
mV
25
40
55
k
-
-
100(1)
ns
2.7 < VDD < 3.6
300(3)
-
-
2.0 < VDD < 3.6
(3)
-
-
500
ns
1. Data based on design simulation only. Not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
3. Data based on design simulation only. Not tested in production.
Figure 25. Recommended NRST pin protection
([WHUQDO
UHVHWFLUFXLW 9 ''
5 38
1567 ,QWHUQDOUHVHW
)LOWHU
—)
069
1. The external capacitor protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53: NRST pin characteristics. Otherwise the reset will not be taken into account by the device.
6.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 54 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 21: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 54. ADC characteristics
Symbol
Parameter
VDDA
Analog supply voltage for
ADC ON
IDDA (ADC)
Current consumption of
the ADC(1)
Conditions
VDD = VDDA = 3.3 V
Min
Typ
Max
Unit
2.4
-
3.6
V
-
0.9
-
mA
fADC
ADC clock frequency
0.6
-
14
MHz
fS(2)
Sampling rate
0.05
-
1
MHz
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Electrical characteristics
STM32F042xx
Table 54. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fTRIG(2)
External trigger frequency
fADC = 14 MHz
-
-
823
kHz
-
-
17
1/fADC
VAIN
Conversion voltage range
0
-
VDDA
V
RAIN(2)
External input impedance
-
-
50
k
RADC(2)
Sampling switch
resistance
-
-
1
k
CADC(2)
Internal sample and hold
capacitor
-
-
8
pF
tCAL(2)
Calibration time
See Equation 1 and
Table 55 for details
fADC = 14 MHz
tlatr(2)
ADC_DR register write
latency
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
fADC = fPCLK/2 = 14 MHz
0.196
μs
fADC = fPCLK/2
5.5
1/fPCLK
0.219
μs
10.5
1/fPCLK
fADC = fHSI14 = 14 MHz
0.188
-
0.259
μs
fADC = fHSI14
-
1
-
1/fHSI14
fADC = 14 MHz
0.107
-
17.1
μs
1.5
-
239.5
1/fADC
0
0
1
μs
1
-
18
μs
ADC jitter on trigger
conversion
Sampling time
tSTAB(2)
Power-up time
tCONV(2)
Total conversion time
(including sampling time)
1/fADC
1.5 ADC
cycles + 3
fPCLK cycles
Trigger conversion latency fADC = fPCLK/4 = 12 MHz
tS(2)
83
-
fADC = fPCLK/4
JitterADC
μs
1.5 ADC
cycles + 2
fPCLK cycles
ADC clock = HSI14
WLATENCY(2)
5.9
fADC = 14 MHz
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 μA on IDDA and 60 μA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
Equation 1: RAIN max formula
TS
R AIN  ------------------------------------------------------------- – R ADC
N+2
f ADC  C ADC  ln  2

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Electrical characteristics
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 55. RAIN max for fADC = 14 MHz
Ts (cycles)
tS (μs)
RAIN max (k)(1)
1.5
0.11
0.4
7.5
0.54
5.9
13.5
0.96
11.4
28.5
2.04
25.2
41.5
2.96
37.2
55.5
3.96
50
71.5
5.11
NA
239.5
17.1
NA
1. Guaranteed by design, not tested in production.
Table 56. ADC accuracy(1)(2)(3)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
ET
Total unadjusted error
Test conditions
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 k
VDDA = 3 V to 3.6 V
TA = 25 °C
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 k
VDDA = 2.7 V to 3.6 V
TA = 40 to 105 °C
Typ
Max(4)
±1.3
±2
±1
±1.5
±0.5
±1.5
±0.7
±1
±0.8
±1.5
±3.3
±4
±1.9
±2.8
±2.8
±3
±0.7
±1.3
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
±1.2
±1.7
ET
Total unadjusted error
±3.3
±4
EO
Offset error
±1.9
±2.8
EG
Gain error
±2.8
±3
ED
Differential linearity error
±0.7
±1.3
EL
Integral linearity error
±1.2
±1.7
fPCLK = 48 MHz,
fADC = 14 MHz, RAIN < 10 k
VDDA = 2.4 V to 3.6 V
TA = 25 °C
Unit
LSB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
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Electrical characteristics
STM32F042xx
Figure 26. ADC accuracy characteristics
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Figure 27. Typical connection diagram using the ADC
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1. Refer to Table 54: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
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6.3.17
Electrical characteristics
Temperature sensor characteristics
Table 57. TS characteristics
Symbol
Parameter
TL(1)
VSENSE linearity with temperature
(1)
Avg_Slope
V30
Average slope
(2)
Voltage at 30 °C (5 °C)
Min
Typ
Max
Unit
-
 1

 2

°C
4.0
4.3
4.6
mV/°C
1.34
1.43
1.52
V
tSTART(1)
Startup time
4
-
10
μs
tS_temp(1)
ADC sampling time when reading the
temperature
4
-
-
μs
1. Guaranteed by design, not tested in production.
2. Measured at VDDA = 3.3 V 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byteRefer to Table 3:
Temperature sensor calibration values.
6.3.18
VBAT monitoring characteristics
Table 58. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
k
R
Resistor bridge for VBAT
-
50
-
Q
Ratio on VBAT measurement
-
2
-
Error on Q
–1
-
+1
%
ADC sampling time when reading the VBAT
4
-
-
μs
Er(1)
tS_vbat(1)
1. Guaranteed by design, not tested in production.
6.3.19
Timer characteristics
The parameters given in the following tables are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 59. TIMx characteristics
Symbol
Parameter
Conditions
tres(TIM)
Timer resolution time
fEXT
Timer external clock
frequency on CH1 to
CH4
ResTIM
tCOUNTER
Timer resolution
16-bit counter clock
period
Min
Max
Unit
1
-
tTIMxCLK
20.8
-
ns
0
fTIMxCLK/2
MHz
fTIMxCLK = 48 MHz
0
24
MHz
TIMx (except TIM2)
-
16
TIM2
-
32
1
65536
tTIMxCLK
0.0208
1365
μs
fTIMxCLK = 48 MHz
fTIMxCLK = 48 MHz
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Electrical characteristics
STM32F042xx
Table 59. TIMx characteristics (continued)
Symbol
Parameter
Conditions
tMAX_COUNT
Maximum possible count
with 32-bit counter
fTIMxCLK = 48 MHz
Min
Max
Unit
-
65536 × 65536
tTIMxCLK
-
89.48
s
Table 60. IWDG min/max timeout period at 40 kHz (LSI)(1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
6 or 7
6.4
26214.4
Unit
ms
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 61. WWDG min/max timeout value at 48 MHz (PCLK)
6.3.20
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.0853
5.4613
2
1
0.1706
10.9226
4
2
0.3413
21.8453
8
3
0.6826
43.6906
Unit
ms
Communication interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:

Standard-mode (Sm): with a bit rate up to 100 kbit/s

Fast-mode (Fm): with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
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Electrical characteristics
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
Table 62. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
tAF
Maximum pulse width of spikes
that are suppressed by the analog
filter
50(2)
260(3)
ns
1. Guaranteed by design, not tested in production.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
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Electrical characteristics
STM32F042xx
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 63 for SPI or in Table 64 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 21: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 63. SPI characteristics(1)
Symbol
fSCK
1/tc(SCK)
Parameter
SPI clock frequency
Conditions
Min
Max
Master mode
-
18
Slave mode
-
18
-
6
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 15 pF
tsu(NSS)
NSS setup time
Slave mode
4Tpclk
-
th(NSS)
NSS hold time
Slave mode
2Tpclk + 10
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk/2 -2
Tpclk/2 + 1
Master mode
4
-
Slave mode
5
-
Master mode
4
-
Slave mode
5
-
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO)(2)
Data output access time
Slave mode, fPCLK = 20 MHz
0
3Tpclk
tdis(SO)(3)
Data output disable time
Slave mode
0
18
tv(SO)
Data output valid time
Slave mode (after enable edge)
-
22.5
tv(MO)
Data output valid time
Master mode (after enable edge)
-
6
Slave mode (after enable edge)
11.5
-
Master mode (after enable edge)
2
-
Slave mode
25
75
th(SO)
th(MO)
DuCy(SCK)
Data output hold time
SPI slave input clock
duty cycle
Unit
MHz
ns
ns
%
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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Electrical characteristics
Figure 28. SPI timing diagram - slave mode and CPHA = 0
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Figure 29. SPI timing diagram - slave mode and CPHA = 1
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1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
STM32F042xx
Figure 30. SPI timing diagram - master mode
(IGH
.33INPUT
3#+/UTPUT
#0(! #0/,
3#+/UTPUT
TC3#+
#0(!
#0/,
#0(! #0/,
#0(!
#0/,
TW3#+(
TW3#+,
TSU-)
-)3/
).0 54
TR3#+
TF3#+
-3 ").
") 4).
,3").
TH-)
-/3)
/54054
- 3"/54
" ) 4/54
TV-/
,3"/54
TH-/
AI6
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
Table 64. I2S characteristics(1)
Symbol
fCK
1/tc(CK)
Parameter
I2S
clock frequency
tr(CK)
I2S clock rise time
tf(CK)
I2S clock fall time
Conditions
Min
Max
1.597
1.601
Slave mode
0
6.5
Capacitive load CL = 15 pF
-
10
-
12
306
-
312
-
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
tw(CKH)
I2S clock high time
tw(CKL)
I2S clock low time
tv(WS)
WS valid time
Master mode
2
-
th(WS)
WS hold time
Master mode
2
-
tsu(WS)
WS setup time
Slave mode
7
-
th(WS)
WS hold time
Slave mode
0
-
I2S slave input clock duty
cycle
Slave mode
25
75
DuCy(SCK)
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Unit
MHz
ns
%
STM32F042xx
Electrical characteristics
Table 64. I2S characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
tsu(SD_MR)
Data input setup time
Master receiver
6
-
tsu(SD_SR)
Data input setup time
Slave receiver
2
-
Master receiver
4
-
Slave receiver
0.5
-
th(SD_MR)
(2)
th(SD_SR)(2)
Data input hold time
tv(SD_ST)(2)
Data output valid time
th(SD_ST)
Data output hold time
tv(SD_MT)
(2)
th(SD_MT)
Slave transmitter (after enable edge)
Slave transmitter (after enable edge)
Master transmitter (after enable edge)
Master transmitter (after enable edge)
Data output valid time
Data output hold time
13
-
-
4
0
-
Unit
ns
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on fPCLK. For example, if fPCLK = 8 MHz, then TPCLK = 1/fPLCLK = 125 ns.
Figure 31. I2S slave timing diagram (Philips protocol)
&.,QSXW
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1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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Electrical characteristics
STM32F042xx
Figure 32. I2S master timing diagram (Philips protocol)
TF#+
TR#+
#+OUTPUT
TC#+
#0/,
TW#+(
#0/,
TV73
TH73
TW#+,
73OUTPUT
TV3$?-4
3$TRANSMIT
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AIB
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CAN (controller area network) interface
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
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Package characteristics
7
Package characteristics
7.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 33. LQFP48 – 7 mm x 7 mm, 48 pin low-profile quad flat package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
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+
!
$
$
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,
$
%
%
%
B
0).
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E
"?-%?6
1. Drawing is not to scale.
Table 65. LQFP48 – 7 mm x 7 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
A
Typ
Max
Min
Typ
Max
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
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115
Package characteristics
STM32F042xx
Table 65. LQFP48 – 7 mm x 7 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
K
0°
3.5°
7°
0°
3.5°
7°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 34. LQFP48 recommended footprint
AID
1. Dimensions are in millimeters.
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Package characteristics
Marking of engineering samples for LQFP48
The following figure shows the engineering sample marking for the LQFP48 package. Only
the information field containing the engineering sample marking is shown.
Figure 35. LQFP48 package top view
8QPDUNDEOHVXUIDFH
(6
0DUNLQJFRPSRVLWLRQILHOG
(QJLQHHULQJVDPSOHPDUNLQJ
069
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
DocID025832 Rev 2
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115
Package characteristics
STM32F042xx
Figure 36. UFQFPN48 – 7 mm x 7 mm, 0.5 mm pitch, package outline
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ODVHUPDUNLQJDUHD
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7
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1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.
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Package characteristics
Table 66. UFQFPN48 – 7 mm x 7 mm, 0.5 mm pitch, package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
D
6.900
7.000
7.100
0.2717
0.2756
0.2795
E
6.900
7.000
7.100
0.2717
0.2756
0.2795
D2
5.500
5.600
5.700
0.2165
0.2205
0.2244
E2
5.500
5.600
5.700
0.2165
0.2205
0.2244
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
T
-
0.152
-
-
0.0060
-
b
0.200
0.250
0.300
0.0079
0.0098
0.0118
e
-
0.500
-
-
0.0197
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. UFQFPN48 recommended footprint
7.30
48
37
1
36
6.20
0.20
6.20
7.30
5.80
5.60
5.60
0.30
12
25
13
0.55
24
5.80
0.50
0.75
ai15697
1. Dimensions are in millimeters.
DocID025832 Rev 2
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115
Package characteristics
STM32F042xx
Marking of engineering samples for UFQFPN48
The following figure shows the engineering sample marking for the UFQFPN48 package.
Only the information field containing the engineering sample marking is shown.
Figure 38. UFQFPN48 package top view
(6
(QJLQHHULQJVDPSOH
069
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
100/117
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Package characteristics
Figure 39. WLCSP36 - 0.4 mm pitch, package outline
H
$EDOOORFDWLRQ
)
H
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1. Drawing is not to scale.
DocID025832 Rev 2
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115
Package characteristics
STM32F042xx
Table 67. WLCSP36, 0.4 mm pitch, package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.555
0.525
0.585
0.0219
0.0207
0.0230
A1
0.175
-
-
0.0069
-
-
A2
0.380
-
-
0.0150
-
-
(2)
0.025
-
-
0.0010
-
-
(3)
0.250
0.220
0.280
0.0098
0.0087
0.0110
D
2.605
2.570
2.640
0.1026
0.1012
0.1039
E
2.703
2.668
2.738
0.1064
0.1050
0.1078
e
0.400
-
-
0.0157
-
-
e1
2.000
-
-
0.0787
-
-
e2
2.000
-
-
0.0787
-
-
F
0.3025
-
-
0.0119
-
-
G
0.2825
-
-
0.0111
-
-
ccc
0.100
-
-
0.0039
-
-
ddd
0.050
-
-
0.0020
-
-
eee
0.050
-
-
0.0020
-
-
A3
b
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
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Package characteristics
Marking of engineering samples for WLCSP36
The following figure shows the engineering sample marking for the WLCSP36 package.
Only the information field containing the engineering sample marking is shown.
Figure 40. WLCSP36 package top view
(
(QJLQHHULQJVDPSOH
069
1. Samples marked “E” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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Package characteristics
STM32F042xx
Figure 41. LQFP32 – 7 mm x 7 mm 32-pin low-profile quad flat package outline
C
!
!
!
3%!4).'
0,!.%
#
MM
CCC
'!5'%0,!.%
#
+
$
!
,
$
,
$
0).
)$%.4)&)#!4)/.
%
%
%
B
E
7@.&@7
1. Drawing is not to scale.
Table 68. LQFP32 – 7 mm x 7 mm 32-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
104/117
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
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Package characteristics
Table 68. LQFP32 – 7 mm x 7 mm 32-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. LQFP32 recommended footprint
6?&0?6
1. Drawing is not to scale.
2. Dimensions are in millimeters.
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Package characteristics
STM32F042xx
Marking of engineering samples for LQFP32
The following figure shows the engineering sample marking for the LQFP32 package. Only
the information field containing the engineering sample marking is shown.
Figure 43. LQFP32 package top view
(QJLQHHULQJVDPSOH (6
069
1. Samples marked “ES” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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Package characteristics
Figure 44. UFQFPN32 - 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package outline
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E
b
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
A0B8_ME
1. Drawing is not to scale.
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. This pad is used for the device ground and must
be connected. It is referred to as pin 0 in Table 12: Legend/abbreviations used in the pinout table.
Table 69. UFQFPN32 – 5 x 5 mm, 32-lead ultra thin fine pitch quad flat no-lead package
mechanical data
inches(1)
millimeters
Dim.
Min
Typ
Max
Min
Typ
Max
A
0.5
0.55
0.6
0.0197
0.0217
0.0236
A1
0.00
0.02
0.05
0
0.0008
0.0020
A3
-
0.152
-
-
0.006
-
b
0.18
0.23
0.28
0.0071
0.0091
0.0110
D
4.90
5.00
5.10
0.1929
0.1969
0.2008
D2
-
3.50
-
-
0.1378
-
E
4.90
5.00
5.10
0.1929
0.1969
0.2008
E2
3.40
3.50
3.60
0.1339
0.1378
0.1417
e
-
0.500
-
-
0.0197
-
L
0.30
0.40
0.50
0.0118
0.0157
0.0197
ddd
0.08
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
STM32F042xx
Figure 45. UFQFPN32 recommended footprint
1. Drawing is not to scale.
2. Dimensions are in millimeters.
Marking of engineering samples for UFQFPN32
The following figure shows the engineering sample marking for the UFQFPN32 package.
Only the information field containing the engineering sample marking is shown.
Figure 46. UFQFPN32 package top view
Engineering sample 1
E
MS34954V1
1. Samples marked “E” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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Package characteristics
Figure 47. UFQFPN28 - 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package outline
$
"
$
!
3EATING
0LANE
#OX 0INCORNER
% %
,
,
0IN)$
$ETAIL:
$ETAIL:
E
4
2O4YP
!
!
3EATING
0LANE
B
!"?-%?6
1. Drawing is not to scale.
2. Dimensions are in millimeters.
3. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
X
Table 70. UFQFPN28 – 4 x 4 mm, 28-lead ultra thin fine pitch quad flat no-lead package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.5
0.55
0.6
0.0197
0.0217
0.0236
A1
-0.05
0
0.05
-0.002
0
0.002
D
3.9
4
4.1
0.1535
0.1575
0.1614
D1
2.9
3
3.1
0.1142
0.1181
0.122
E
3.9
4
4.1
0.1535
0.1575
0.1614
E1
2.9
3
3.1
0.1142
0.1181
0.122
L
0.3
0.4
0.5
0.0118
0.0157
0.0197
L1
0.25
0.35
0.45
0.0098
0.0138
0.0177
T
-
0.152
-
-
0.006
-
b
0.2
0.25
0.3
0.0079
0.0098
0.0118
e
-
0.5
-
-
0.0197
-
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
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Figure 48. UFQFPN28 recommended footprint
1. Dimensions are in millimeters
2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
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Package characteristics
Marking of engineering samples for UFQFPN28
The following figure shows the engineering sample marking for the UFQFPN28 package.
Only the information field containing the engineering sample marking is shown.
Figure 49. UFQFPN28 package top view
(QJLQHHULQJVDPSOH (
069
1. Samples marked “E” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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Package characteristics
STM32F042xx
Figure 50. TSSOP20 - 20-pin thin shrink small outline
$
C
%
%
K
AAA #0
!
!
,
!
,
B
E
9!?-%
1. Drawing is not to scale.
Table 71. TSSOP20 – 20-pin thin shrink small outline package mechanical data
inches(1)
millimeters
Symbol
Min
A
Typ
Max
Min
Typ
-
1.2
-
-
0.0472
A1
0.05
-
0.15
0.002
-
0.0059
A2
0.8
1
1.05
0.0315
0.0394
0.0413
b
0.19
0.3
0.0075
-
0.0118
c
0.09
0.2
0.0035
-
0.0079
D(2)
6.4
6.5
6.6
0.252
0.2559
0.2598
E
6.2
6.4
6.6
0.2441
0.252
0.2598
E1(3)
4.3
4.4
4.5
0.1693
0.1732
0.1772
e
-
0.65
-
-
0.0256
-
L
0.45
0.6
0.75
0.0177
0.0236
0.0295
L1
-
1
-
-
0.0394
-
k
0.0°
-
8.0°
0.0°
-
8.0°
aaa
-
-
0.1
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per
side.
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Package characteristics
Figure 51. TSSOP20 recommended footprint
1. Dimensions are in millimeters.
Marking of engineering samples for TSSOP20
The following figure shows the engineering sample marking for the TSSOP20 package.
Only the information field containing the engineering sample marking is shown.
Figure 52. TSSOP20 package top view
(QJLQHHULQJVDPSOH
(
069
1. Samples marked “E” are to be considered as “Engineering Samples”: i.e. they are intended to be sent to
customer for electrical compatibility evaluation and may be used to start customer qualification where
specifically authorized by ST in writing. In no event ST will be liable for any customer usage in production.
Only if ST has authorized in writing the customer qualification Engineering Samples can be used for
reliability qualification trials.
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115
Package characteristics
7.2
STM32F042xx
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 21: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x JA)
Where:

TA max is the maximum ambient temperature in °C,

JA is the package junction-to-ambient thermal resistance, in C/W,

PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),

PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 72. Package thermal characteristics
Symbol
JA
7.2.1
Parameter
Value
Thermal resistance junction-ambient
LQFP48 - 7 mm x 7 mm
55
Thermal resistance junction-ambient
UFQFPN48 - 7 mm x 7 mm
33
Thermal resistance junction-ambient
WLCSP36 die 445
64
Thermal resistance junction-ambient
LQFP32 - 7 mm x 7 mm
57
Thermal resistance junction-ambient
UFQFPN32 - 5 mm x 5 mm
38
Thermal resistance junction-ambient
UFQFPN28 - 4 mm x 4 mm
118
Thermal resistance junction-ambient
TSSOP20 - 6.5 mm x 6.4 mm
76
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
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8
Part numbering
Part numbering
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
+
Table 73. Ordering information scheme
Example:
STM32
F
042
C
6
T
6
x
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
042 = STM32F042xx
Pin count
F = 20 pins
G = 28 pins
K = 32 pins
T = 36 pins
C = 48 pins
Code size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
P = TSSOP
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
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Revision history
9
STM32F042xx
Revision history
Table 74. Document revision history
Date
Revision
25-Feb-2014
1
Initial release.
2
Updated:
– The document status to Datasheet - production data,
– Table 10: STM32F042x USART implementation: added one
table footnote.
– Figure 3: LQFP48 48-pin package pinout (top view),
– Figure 8: UQFPN28 28-pin package (top view),
– Table 13: STM32F042x pin definitions,
– Table 19: Current characteristics,
– Table 26: Typical and maximum current consumption from
VDD supply at VDD = 3.6 V,
– Table 27: Typical and maximum current consumption from the
VDDA supply,
– Table 28: Typical and maximum consumption in Stop and
Standby modes,
– Table 29: Typical and maximum current consumption from the
VBAT supply,
– Table 30: Typical current consumption, code executing from
Flash, running from HSE 8 MHz crystal,
– Table 43: Flash memory characteristics,
– Table 45: EMS characteristics,
– Table 46: EMI characteristics,
– Table 50: I/O static characteristics,
– Table 49: I/O current injection susceptibility,
– Figure 13: Power supply scheme,
– Figure 22: TC and TTa I/O input characteristics,
– Figure 23: Five volt tolerant (FT and FTf) I/O input
characteristics.
Added the sample engineering sections for all the packages in
Chapter 7: Package characteristics:
– Figure 35: LQFP48 package top view,
– Figure 38: UFQFPN48 package top view,
– Figure 40: WLCSP36 package top view,
– Figure 43: LQFP32 package top view,
– Figure 46: UFQFPN32 package top view,
– Figure 49: UFQFPN28 package top view,
– Figure 52: TSSOP20 package top view.
04-Apr-2014
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