TI SN75ALS176AP

SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
D
D
D
D
D
D
D
D
D
D
D
D OR P PACKAGE
(TOP VIEW)
Meet or Exceed the Requirements of
TIA/EIA-422-B, TIA/EIA-485-A, and ITU
Recommendations V.11 and X.27
Operate at Data Rates up to 35 MBaud
Four Skew Limits Available:
SN65ALS176 . . . 15 ns
SN75ALS176 . . . 10 ns
SN75ALS176A . . . 7.5 ns
SN75ALS176B . . . 5 ns
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
Low Supply-Current Requirements . . .
30 mA Max
Wide Positive and Negative Input/Output
Bus-Voltage Ranges
Thermal Shutdown Protection
Driver Positive and Negative Current
Limiting
Receiver Input Hysteresis
Glitch-Free Power-Up and Power-Down
Protection
Receiver Open-Circuit Fail-Safe Design
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
description
The SN65ALS176 and SN75ALS176 series differential bus transceivers are designed for bidirectional data
communication on multipoint bus transmission lines. They are designed for balanced transmission lines and
meet TIA/EIA-422-B, TIA/EIA-485-A, and ITU Recommendations V.11 and X.27.
The SN65ALS176 and SN75ALS176 series combine a 3-state, differential line driver and a differential input line
receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, that can be connected together externally to function as a direction control.
The driver differential outputs and the receiver differential inputs are connected internally to form a differential
input/output (I/O) bus port that is designed to offer minimum loading to the bus when the driver is disabled or
VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device
suitable for party-line applications.
The SN65ALS176 is characterized for operation from – 40°C to 85°C, and the SN75ALS176 series is
characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
AVAILABLE OPTIONS
PACKAGED DEVICES
tsk(lim)†
TA
SMALL OUTLINE
(D) ‡
10
7.5
5
0°C to 70°C
PLASTIC DIP
(P)
SN75ALS176D
SN75ALS176AD
SN75ALS176BD
SN75ALS176P
SN75ALS176AP
SN75ALS176BP
– 40°C to 85°C
15
SN65ALS176D
SN65ALS176P
† tsk(lim) This is the maximum range that the driver or receiver delay times vary
over temperature, VCC, and process (device to device).
‡ The D package is available taped and reeled. Add the suffix R to the device type
(e.g., SN75ALS176DR).
Function Tables
DRIVER
OUTPUTS
INPUT
D
ENABLE
DE
H
H
H
L
L
H
L
H
X
L
Z
Z
A
B
H = high level, L = low level, X = irrelevant,
Z = high impedance
RECEIVER
DIFFERENTIAL INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
– 0.2 V < VID < 0.2 V
L
H
L
?
VID ≤ – 0.2 V
X
L
L
H
Z
Inputs open
L
H
H = high level, L = low level, X = irrelevant,
Z = high impedance
logic symbol§
DE
RE
D
R
3
2
logic diagram (positive logic)
DE
EN1
EN2
6
4
1
1
1
D
3
4
A
7
B
2
RE
R
2
6
1
§ This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
2
POST OFFICE BOX 655303
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7
A
Bus
B
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
TYPICAL OF A AND B I/O PORTS
VCC
R(eq)
Input
85 Ω
NOM
180 kΩ
NOM
VCC
Connected
on A Port
A or B
18 kΩ
NOM
Driver Input: R(eq) = 3 kΩ NOM
Enable Inputs: R(eq) = 8 kΩ NOM
R(eq) = equivalent resistor
TYPICAL OF RECEIVER OUTPUT
180 kΩ
NOM
Connected
on B Port
3 kΩ
NOM
Output
1.1 kΩ
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 7 V to 12 V
Enable input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51.
POST OFFICE BOX 655303
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3
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
recommended operating conditions (unless otherwise noted)
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
Input voltage at any bus terminal (separately or common mode),
mode) VI or VIC
–7
High-level input voltage, VIH
D, DE, and RE
Low-level input voltage, VIL
D, DE, and RE
2
Differential input voltage, VID (see Note 3)
Driver
High level output current,
High-level
current IOH
Receiver
V
0.8
V
± 12
V
– 60
mA
– 400
µA
Driver
Low level output current
Low-level
current, IOL
60
Receiver
SN65ALS176
Operating free-air
free air temperature,
temperature TA
SN75ALS176 series
8
– 40
85
0
70
NOTE 3: Differential input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
mA
°C
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
TEST CONDITIONS†
PARAMETER
VIK
VO
Input clamp voltage
Output voltage
II = – 18 mA
IO = 0
| VOD1 |
Differential output voltage
IO = 0
| VOD2 |
g
Differential output voltage
VOD3
Differential output voltage
∆| VOD |
Change in magnitude of differential
output voltage ¶
VOC
Common mode output voltage
Common-mode
∆| VOC |
Change in magnitude of
common-mode output voltage¶
IO
Output current
IIH
IIL
High-level input current
Low-level input current
Short-circuit output current#
UNIT
– 1.5
V
0
6
V
1.5
6
V
See Figure 1
1/2 VOD1
or 2§
RL = 54 Ω,
See Figure 1
1.5
Vtest = – 7 V to 12 V,
See Figure 2
1.5
RL = 54 Ω or 100 Ω
Ω,
Outputs disabled,,
See Note 4
TYP‡
MAX
RL = 100 Ω,
V
2.5
See Figure 1
VO = 12 V
VO = – 7 V
Supply current
SN65ALS176
V
± 0.2
V
3
–1
V
± 0.2
V
mA
20
µA
– 400
µA
– 250
SN75ALS176
VO = 0
VO = VCC
No load
V
5
1
– 150
mA
250
VO = 8 V
ICC
5
– 0.8
VI = 2.4 V
VI = 0.4 V
VO = – 4 V
VO = – 6 V
IOS
MIN
Outputs enabled
23
30
Outputs disabled
19
26
mA
† The power-off measurement in TIA/EIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡ All typical values are at VCC = 5 V and TA = 25°C.
§ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
¶ ∆ | VOD | and ∆ | VOC | are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from one logic state
to the other.
# Duration of the short circuit should not exceed one second for this test.
NOTE 4: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions. The TIA/EIA-422-B limit does not apply for a
combined driver and receiver terminal.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
SN65ALS176
PARAMETER
td(OD)
tsk(p)
Differential output delay time
Pulse skew‡
tsk(lim)
tt(OD)
Pulse skew§
tPZH
tPZL
Output enable time to high level
TEST CONDITIONS
RL = 54 Ω,
CL = 50 pF,
RL = 54 Ω,
Ω
Output enable time to low level
TYP†
See Figure 3
CL = 50 pF,
pF
See Figure 3
CL = 50 pF,
RL = 110 Ω, CL = 50 pF,
RL = 110 Ω, CL = 50 pF,
See Figure 3
RL = 54 Ω,
Differential output transition time
MIN
MAX
15
0
2
15
8
UNIT
ns
ns
ns
See Figure 4
80
ns
See Figure 5
30
ns
50
ns
30
ns
tPHZ
Output disable time from high level
RL = 110 Ω, CL = 50 pF,
See Figure 4
tPLZ
Output disable time from low level
RL = 110 Ω, CL = 50 pF,
See Figure 5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
§ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
3
8
13
4
7
11.5
5
8
10
0
2
’ALS176
RL = 54 Ω,
CL = 50 pF,
See Figure 3
RL = 54 Ω,
CL = 50 pF,
See Figure 3
RL = 54 Ω,
CL = 50 pF,
See Figure 3
Differential output transition time
RL = 54 Ω,
CL = 50 pF,
See Figure 3
8
Output enable time to high level
RL = 110 Ω, CL = 50 pF,
RL = 110 Ω, CL = 50 pF,
See Figure 4
23
50
ns
See Figure 5
14
20
ns
RL = 110 Ω, CL = 50 pF,
RL = 110 Ω, CL = 50 pF,
See Figure 4
20
35
ns
8
17
ns
td(OD)
(
)
Differential output delay time
tsk(p)
Pulse skew‡
tsk(lim)
( )
Pulse skew§
tt(OD)
tPZH
tPZL
tPHZ
Output enable time to low level
’ALS176A
’ALS176B
’ALS176
’ALS176A
Output disable time from high level
ns
ns
5
tPLZ
Output disable time from low level
See Figure 5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
§ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER
TIA/EIA-422-B
TIA/EIA-485-A
VO
| VOD1 |
Voa, Vob
Vo
Voa, Vob
Vo
| VOD2 |
Vt (RL = 100 Ω)
| VOD3 |
None
Vt (RL = 54 Ω)
Vt (test termination
measurement 2)
∆ | VOD |
| | Vt | – | Vt | |
| | Vt | – | Vt | |
VOC
∆ | VOC |
| Vos |
| Vos |
| Vos – Vos |
IOS
IO
ns
10
7.5
’ALS176B
6
UNIT
| Vos – Vos |
| Isa |, | Isb |
None
| Ixa |, | Ixb |
Iia, Iib
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature range (unless otherwise noted)
PARAMETER
VIT+
VIT –
Positive-going input threshold voltage
Vhys
VIK
Hysteresis voltage (VIT + – VIT –)
Negative-going input threshold voltage
TEST CONDITIONS
VO = 2.7 V,
VO = 0.5 V,
IO = – 0.4 mA
IO = 8 mA
II = – 18 mA
VOH
High level output voltage
High-level
VID = 200 mV,,
See Figure 6
IOH = – 400 µ
µA,,
VOL
Low level output voltage
Low-level
VID = – 200 mV,,
See Figure 6
IOL = 8 mA,,
IOZ
High-impedance-state output current
VO = 0.4 V to 2.4 V
VI
Line input current
Other input = 0 V,,
See Note 4
IIH
IIL
High-level-enable input current
rI
Input resistance
IOS
Short-circuit output current
ICC
Supply current
TYP†
MAX
0.2
– 0.2‡
27
2.7
VI = 12 V
VI = – 7 V
No load
0 45
0.45
V
± 20
µA
1
– 0.8
20
– 100
VO = 0
Outputs enabled
20
– 15
Outputs disabled
V
V
VIH = 2.7 V
VIL = 0.4 V
VID = 200 mV,
V
mV
– 1.5
12
UNIT
V
60
Enable-input clamp voltage
Low-level-enable input current
MIN
mA
µA
µA
kΩ
– 85
23
30
19
26
mA
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 5: This applies for power on and power off. Refer to TIA/EIA-485-A for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
SN65ALS176
PARAMETER
TEST CONDITIONS
tpd
Propagation time
tsk(p)
VID = – 1.5 V to 1.5 V,,
See Figure 7
CL = 15 pF,,
Pulse skew§
tsk(lim)
Pulse skew¶
RL = 54 Ω,
See Figure 3
CL = 50 pF,
tPZH
tPZL
Output enable time to high level
Output enable time to low level
CL = 15 pF,
pF
MIN
See Figure 8
• DALLAS, TEXAS 75265
MAX
UNIT
25
ns
2
ns
15
ns
11
18
ns
11
18
ns
50
ns
30
ns
0
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
† All typical values are at VCC = 5 V, TA = 25°C.
§ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
¶ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
POST OFFICE BOX 655303
TYP†
7
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) (continued)
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
’ALS176
tpd
Propagation time
tsk(p)
Pulse skew‡
tsk(lim)
( )
Pulse skew§
’ALS176A
’ALS176B
’ALS176
’ALS176A
VID = – 1.5 V to 1.5 V,,
See Figure 7
CL = 15 pF,,
9
14
19
10.5
14
18
11.5
13
16.5
0
2
CL = 50 pF,
ns
7.5
ns
5
Output enable time to high level
7
14
ns
Output enable time to low level
20
35
ns
20
35
ns
8
17
ns
CL = 15 pF,
pF
See Figure 8
tPHZ
Output disable time from high level
tPLZ
Output disable time from low level
† All typical values are at VCC = 5 V, TA = 25°C.
‡ Pulse skew is defined as the |tPLH – tPHL| of each channel of the same device.
§ Skew limit is the maximum difference in propagation delay times between any two channels of any two devices.
PARAMETER MEASUREMENT INFORMATION
VOD2
RL
2
RL
2
VOC
Figure 1. Driver VOD2 and VOC
375 Ω
VOD3
60 Ω
375 Ω
Vtest
Figure 2. Driver VOD3
8
ns
10
RL = 54 Ω,
See Figure 3
’ALS176B
tPZH
tPZL
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
3V
1.5 V
Input
RL = 54 Ω
Generator
(see Note B)
1.5 V
CL = 50 pF
(see Note A)
0V
Output
50 Ω
td(ODL)
(see Note C)
≈2.5 V
td(ODH)
(see Note C)
90% 90%
Output
3V
50%
10%
50%
10%
≈ – 2.5 V
tt(OD)
tt(OD)
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
C. td(OD) = td(ODH) or td(ODL)
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
3V
S1
Input
1.5 V
1.5 V
0 V or 3 V
0V
tPZH
RL = 110 Ω
Generator
(see Note B)
CL = 50 pF
(see Note A)
50 Ω
Output
TEST CIRCUIT
VOH
2.3 V
tPHZ
Voff ≈0
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 4. Driver Test Circuit and Voltage Waeforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
5V
3V
RL = 110 Ω
S1
1.5 V
0V
Output
0 V or 3 V
Generator
(see Note B)
1.5 V
Input
tPZL
tPLZ
CL = 50 pF
(see Note A)
50 Ω
5V
0.5 V
2.3 V
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 5. Driver Test Circuit and Voltage Waveforms
VID
VOH
+ IOL
– IOH
VOL
Figure 6. Receiver VOH and VOL Test Circuit
3V
Input
Generator
(see Note B)
1.5 V
1.5 V
Output
51 Ω
1.5 V
CL = 15 pF
(see Note A)
0V
tPHL
(see Note C)
VOH
tPLH
(see Note C)
0V
1.3 V
Output
1.3 V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
C. tpd = tPLH or tPHL
Figure 7. Receiver Test Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
5V
S2
S1
1.5 V
2 kΩ
– 1.5 V
Output
CL = 15 pF
(see Note A)
Generator
(see Note B)
5 kΩ
1N916 or Equivalent
50 Ω
S3
TEST CIRCUIT
Input
1.5 V
3V
S1 to 1.5 V
S2 Open
S3 Closed
0V
3V
Input
1.5 V
tPZL
tPZH
VOH
Output
≈4.5 V
Output
1.5 V
1.5 V
0V
VOL
3V
Input
S1 to 1.5 V
S2 Closed
S3 Closed
1.5 V
Input
3V
S1 to – 1.5 V
S2 Closed
S3 Closed
0V
1.5 V
0V
tPHZ
tPLZ
≈1.3 V
VOH
Output
S1 to – 1.5 V
0 V S2 Closed
S3 Open
0.5 V
Output
0.5 V
≈ 1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
Figure 8. Receiver Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS†
DRIVER
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
5
VCC = 5 V
TA = 25°C
VCC = 5 V
TA = 25°C
4.5
VOL – Low-Level Output Voltage – V
VOH – High-Level Output Voltage – V
4.5
4
3.5
3
2.5
2
1.5
1
4
3.5
3
2.5
2
1.5
1
0.5
0.5
0
0
0
– 20
– 40
– 60
– 80
– 100
IOH – High-Level Output Current – mA
0
– 120
80
100
20
40
60
IOL – Low-Level Output Current – mA
Figure 9
120
Figure 10
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
VOD – Differential Output Voltage – V
4
VCC = 5 V
TA = 25°C
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30 40 50 60 70 80
IO – Output Current – mA
90
100
Figure 11
† Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS†
RECEIVER
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
VID = 0.3 V
TA = 25°C
4.5
4.5
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
5
4
3.5
3
VCC = 5.25 V
2.5
VCC = 5 V
2
1.5
VCC = 4.75 V
1
0.5
4
VCC = 5 V
VID = 300 mV
IOH = – 440 µA
3.5
3
2.5
2
1.5
1
0.5
0
0
– 40
0 – 5 – 10 – 15 – 20 – 25 – 30 – 35 – 40 – 45 – 50
IOH – High-Level Output Current – mA
– 20
0
20
40
60
80
TA – Free-Air Temperature – °C
Figure 12
120
Figure 13
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
0.6
VCC = 5 V
TA = 25°C
VID = – 300 mV
0.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
100
0.4
0.3
0.2
0.1
0
0
15
20
25
10
IOL – Low-Level Output Current – mA
5
30
0.5
VCC = 5 V
VID = – 300 mA
IOL = 8 mA
0.4
0.3
0.2
0.1
0
– 40
– 20
80
100
0
20
40
60
TA – Free-Air Temperature – °C
Figure 14
120
Figure 15
† Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040G – AUGUST 1987 – REVISED DECEMBER 1999
TYPICAL CHARACTERISTICS†
RECEIVER
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
VO – Output Voltage – V
VCC = 4.75 V
3
VID = 0.3 V
Load = 1 kΩ to VCC
TA = 25°C
5
VO – Output Voltage – V
VCC = 5.25 V
4
6
VID = 0.3 V
Load = 8 kΩ to GND
TA = 25°C
VCC = 5 V
2
VCC = 5.25 V
VCC = 4.75 V
4
VCC = 5 V
3
2
1
1
0
0
0.5
1
1.5
2
2.5
0
3
0
0.5
VI(en) – Enable Voltage – V
1.5
2
2.5
1
VI(en) – Enable Voltage – V
3
Figure 17
Figure 16
† Operation of the device at these or any other conditions beyond those indicated under ‘‘recommended operating conditions” is not implied.
APPLICATION INFORMATION
RT
RT
Up to 53
Transceivers
• • •
NOTE A: The line should terminate at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short
as possible.
Figure 18. Typical Application Circuit
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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