TI SN65LVDS152DA

SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
A Member of the MuxIt Serializer-
SN65LVDS152DA
(Marked as 65LVDS152)
(TOP VIEW)
Deserializer Building-Block Chip Family
Supports Deserialization of One Serial Link
Data Channel Input at Rates up to
200 Mbps
PLL Lock/Valid Input Provided to Enable
Parallel Data and Clock Outputs
Cascadable With Additional SN65LVDS152
MuxIt Receiver–Deserializers for Wider
Parallel Output Data Channel Widths
LVDS Compatible Differential Inputs and
Outputs Meet or Exceed the Requirements
of ANSI TIA/EIA-644-A
LVDS Input and Output ESD Protection
Exceeds 12 kV HBM
LVTTL Compatible Inputs for Lock/Valid
and Enables Are 5-V Tolerant
Operates With 3.3-V Supply
Packaged in 32-Pin DA Thin Shrink SmallOutline Package With 26-Mil Terminal Pitch
DI+
DI–
GND
LCI+
LCI–
GND
CO_EN
VCC
GND
VCC
VCC
GND
GND
EN
CO–
CO+
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
LVI
MCI–
MCI+
GND
DCO
DO–9
DO–8
DO–7
DO–6
DO–5
DO–4
DO–3
DO–2
DO–1
DO–0
description
MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers and
deserializers. The system allows for wide parallel data to be transmitted through a reduced number of
transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or LVCMOS)
data interface. The number of bits multiplexed per transmission line is user selectable, allowing for higher
transmission efficiencies than with other existing fixed ratio solutions. MuxIt utilizes the LVDS (TIA/EIA-644-A)
low voltage differential signaling technology for communications between the data source and data destination.
The MuxIt family initially includes three devices supporting simplex communications: the SN65LVDS150 phase
locked loop frequency multiplier, the SN65LVDS151 serializer-transmitter, and the SN65LVDS152 receiverdeserializer.
The SN65LVDS152 consists of three LVDS differential transmission line receivers, an LVDS differential
transmission line driver, a 10-bit serial-in/parallel-out shift register, plus associated input and output buffers. It
receives serialized data over an LVDS transmission line link, deserializes (demultiplexes) it, and delivers it on
parallel data outputs, DO–0 through DO–9. Data received over the link is clocked at a factor of M times the
original parallel data frequency. The multiplexing ratio M, or number of bits per data clock cycle, is programmed
with configuration pins (M1 → M5) on the companion SN65LVDS150 MuxIt programmable PLL frequency
multiplier. Up to 10 bits of data may be deserialized and output by each SN65LVDS152. Two or more
SN65LVDS152 units may be connected in series (cascaded) to accommodate wider parallel data paths for
higher serialization values. The range of multiplexing ratio M supported by the SN65LVDS150 MuxIt
programmable PLL frequency multiplier is between 4 and 40. Table 1 shows some of the combinations of LCI
and MCI supported by the SN65LVDS150 MuxIt programmable PLL frequency multiplier.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MuxIt is a trademark of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
description (continued)
Data is serially shifted into the SN65LVDS152 shift register on the falling edges of the M-clock input (MCI). The
data is latched out in parallel from the SN65LVDS152 shift register on the second rising edge after the first falling
edge of the M-clock following a rising edge of the link clock input (LCI). The SN65LVDS152 includes LVDS
differential line receivers for both the serialized link data stream (DI) and link clock (LCI). High-speed signals
from the SN65LVDS150 MuxIt programmable frequency multiplier (MCI), plus the input and output for cascaded
data (DI, CO) are carried over differential connections to minimize skew and jitter. Examples of operating
waveforms for values of M = 4 and M = 10 are provided in Figure 1.
The enable input (EN) along with internal power-on reset (POR) controls the outputs. When Vcc is below 1.5
volts, or when EN is low, outputs are disabled. When VCC is above 3 V and EN is high, outputs are enabled and
operating to specifications.
Parallel data bits are output from DO–n outputs in an order dependent on the value of the multiplexing ratio
(frequency multiplier value) M. For values of M from 4 through 10, the cascade output (CO+/–) is not used, and
only the top M parallel outputs (DO–9 through DO–[10–M]) are used. The data bit output on DO–9 corresponds
to the data bit input on DI–[M–1] of the SN65LVDS151 serializer. Likewise, the data bit output on DO–[10–M]
will correspond to the data bit input on DI–0 of the SN65LVDS151 serializer.
For values of M greater than 10, the cascade output (CO+/–) is used to connect multiple SN65LVDS152
deserializers. In this case the higher-order unit(s) output 10 bits each of the highest numbered bits that are input
into the SN65LVDS151 serializer(s). The lowest numbered input bits are output on the lowest-order
SN65LVDS152 deserializer in descending order from output DO–9. The number of bits is equal to M mod(10).
Table 2 reflects this information, where X = M mod(10)
Table 1. Example Combinations of LCI and MCI Supported by the
SN65LVDS150 MuxIt Programmable PLL Frequency Multiplier
LCI, MHz
MCI, MHz
M
MINIMUM
MAXIMUM
MINIMUM
MAXIMUM
4
5
50
20
200
10
5
20
50
200
20
5
10
100
200
40
5
5
200
200
Table 2. Output Data BIts as a Function of Multiplier Value M
X=1
X=2
X=3
X=4
X=5
X=6
X=7
X=8
X=9
X=0
DO–9 output bit
DI–0
DI–1
DI–2
DI–3
DI–4
DI–5
DI–6
DI–7
DI–8
DI–9
DO–8 output bit
Invalid
DI–0
DI–1
DI–2
DI–3
DI–4
DI–5
DI–6
DI–7
DI–8
DO–7 output bit
Invalid
Invalid
DI–0
DI–1
DI–2
DI–3
DI–4
DI–5
DI–6
DI–7
DO–6 output bit
Invalid
Invalid
Invalid
DI–0
DI–1
DI–2
DI–3
DI–4
DI–5
DI–6
DO–5 output bit
Invalid
Invalid
Invalid
Invalid
DI–0
DI–1
DI–2
DI–3
DI–4
DI–5
DO–4 output bit
Invalid
Invalid
Invalid
Invalid
Invalid
DI–0
DI–1
DI–2
DI–3
DI–4
DO–3 output bit
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
DI–0
DI–1
DI–2
DI–3
DO–2 output bit
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
DI–0
DI–1
DI–2
DO–1 output bit
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
DI–0
DI–1
DO–0 output bit
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
DI–0
Additional information on output bit ordering in cascaded applications can be found in the MuxIt Application
Report.
2
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SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
description (continued)
M=4
Next Frame
DI
DI(2)
DI(3)
DI(0)
DI(1)
DI(2)
DI(3)
LCI
MCI
DCO
DO–n
Prior Frame
Current Frame
M = 10
Next Frame
DI
DI(9)
DI(0)
DI(1)
DI(2)
DI(3)
DI(4)
DI(5)
DI(6)
DI(7)
DI(8)
DI(9)
DI(0)
LCI
MCI
DCO
DO–n
Prior Frame
Current Frame
Figure 1. Operating Waveform Examples
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3
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
functional block diagram
LCI
EN
LVI
Control Logic
MCI
DCO
CO_EN
DI
DO–9
DO–8
DO–7
Output Latches
Shift Register
DO–6
DO–5
DO–4
DO–3
DO–2
DO–1
DO–0
CO
4
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SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
equivalent input and output schematic diagrams
VCC
VCC
300 kΩ
300 kΩ
5Ω
LCI–, MCI–,
or DI–
Inputs
LCI+, MCI+,
or DI+
Inputs
4V
10 kΩ
CO+, or CO–
Output
4V
4V
VCC
VCC
5Ω
400 Ω
DCO, DO–n
Outputs
5V
EN, LVI, CO_EN
Input
6V
300 kΩ
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SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
Terminal Functions
TERMINAL
I/O
LEVEL
DESCRIPTION
15, 16
Output
LVDS
Cascade output. This is used to connect to additional SN65LVDS152 units when the
multiplexing ratio M (and M-clock) value is greater than 10.
CO_EN
7
Input
LVTTL
Cascade output enable. Used to control the CO output. A high-level input enables the CO
output, a low-level input disables the CO output.
DCO
27
Output
LVTTL
Data clock output. This is the recovered (original frequency) clock that is synchronized to
the deserialized parallel data.
DI+, DI–
1, 2
Input
LVDS
Link data input. This is the data being received from the source end of the serialized link.
Also used for cascade data input from additional SN65LVDS152 units when the
multiplexing ratio M value is greater than 10.
EN
14
Input
LVTTL
Enable. Used to control overall device operation. A high-level input enables the device. A
low-level input disables the device by resetting the internal latches and forcing the CO and
LVTTL outputs to a high-impedance state.
3, 6, 9, 12,
13, 28
Power
NA
LCI+, LCI–
4, 5
Input
LVDS
Link clock input. This is the data block synchronization clock received from the source end
of the serialized link.
LVI
31
Input
LVTTL
Lock/valid input. This is a signal required for proper Muxlt system operation. It is to be
directly connected to the LVO output of an SN65LVDS150. It is used to inhibit the
operation of this device until after the PLL has stabilized. A low level input disables the
data and clock outputs, a high level input enables the outputs
MCI+, MCI–
29,30
Input
LVDS
M-clock input. This is the high frequency multiplied clock input from the local PLL
frequency multiplier. It synchronizes the reception of the link data
DO–0–DO–9
17–26
Output
LVTTL
Parallel data outputs. Data from the serial shift register is transferred to the output data
latches in synchronization with the rising edge of LCI.
8, 10, 11,
32
Power
NA
NAME
CO–, CO+
GND
VCC
NO.
Circuit ground
Supply voltage
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range: EN, LVI, CO_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
LCI±, MCI±, DI±, CO± . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge, human body model (see Note 2): LCI±, MCI±, DI±, CO±, and GND . . . . . . . ±12 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 kV
Charged-device model (see Note 3): All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114–B.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
6
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DA
1453 mW
11.6 mW/°C
756 mW
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SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
recommended operating conditions
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
VCC
0.8
V
Supply voltage, VCC
High-level input voltage, VIH
2
EN LVI,
LVI CO
EN
EN,
CO_EN
Low-level input voltage, VIL
Magnitude of differential input voltage, |VID|
0.1
|V
ID
2
LCI±, MCI±, DI±
Common-mode
Common
mode in
input
ut voltage, VIC
Operating free-air temperature, TA
|
V
0.6
|V
V
|
ID
2
VCC – 0.8
V
85
°C
2.4–
– 40
V
timing requirements
PARAMETERS
tsu(1)
tsu(2)
Clock setup time, MCI↓ before LCI↑
tsu(3)
th(3)
Link data setup time, DI before MCI↓
TEST CONDITIONS
See Figure 2
Clock setup time, LCI↑ before MCI↓
See Figure 3
Link data hold time, DI after MCI↓
LCI
LCI
0V
MAX
UNIT
0
ns
1
ns
0.3
ns
0.5
ns
0V
tsu(1)
MCI
MIN
tsu(2)
MCI
0V
0V
Figure 2
+100 mV
DI
+100 mV
DI
–100 mV
–100 mV
t h(3)
t su(3)
MCI
0V
MCI
0V
Figure 3. Input Data and M-Clock Setup and Hold Time Waveforms
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SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
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PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
|VOD(SS)|
Steady-state differential output voltage magnitude
∆|VOD(SS)|
Change in steady-state differential output voltage
magnitude between logic states
VOC(SS)
Steady-stade common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
VOH
Peak-to-peak change common-mode output voltage
VOL
Low-level output voltage
Negative-going differential input voltage threshold
High-level output voltage
DO n DCO
DO-n,
Supply current
See Figure 4
–50
50
mV
1.125
1.375
See Figure 7
–50
50
mV
150
mV
IOH = –8 mA
IOL = 8 mA
2.4
RL = 100 Ω,
14
25
Disabled
0.5
1
f(MCI) = 200 MHz,
f(LCI) = 20 MHz, RL = 100 Ω,
DI–n= 1010101010 at 200 Mbit/s
35
60
Differential input current
LCI, MCI, DI inputs
VIC = 0.05 V to 2.35 V,
VID = ±0.1 V
II(OFF)
IIH
Power-off input current
LCI, MCI, DI inputs
High-level input current
EN, LVI, CO_EN
IIL
Low-level input current
EN, LVI, CO_EN
CO
DO-n, DCO
VCC = 0 V ,
VIH = 2 V
V
V
mA
–2
– 20
–1.2
–2
VI = 3.6 V
µA
2
µA
20
µA
20
µA
VIL = 0.8 V
VO+ or VO– = 0 V
10
µA
–10
10
mA
VOD = 0 V
–10
10
mA
–5
5
–5
5
VO = 0 V or VCC
IO(OFF)
Power-off output current
CO
CI
Input capacitance
LCI, MCI, DI inputs
† All typical values are at TA = 25°C and with VCC = 3.3 V.
VCC = 1.5 V , VO = 3.6 V
VID = (0.4sin(4E6πt) + 0.5) V
8
• DALLAS, TEXAS 75265
POST OFFICE BOX 655303
340
0.4
IID
High im edance out
High-impedance
output
ut
current
247
50
VI = 0 V
VI = 2.4 V
IOZ
mV
mV
LCI MCI,
MCI DI inputs
LCI,
CO
UNIT
454
RL = 100 Ω
Ω, VID = ±100 mV,
mV
See Figures 5 and 6
Input current
Short circuit output current
Short-circuit
MAX
–100
II
IOS
TYP†
100
Enabled,
ICC
MIN
–5
5
3
µA
µA
pF
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
Á
ÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
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ÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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PARAMETER
TEST CONDITIONS
td(1)
td(2)
Propagation delay time, LCI↑ to DCO↑
tsu(4)
th(4)
Set-up time, DO-n valid to DCO↑
td(3)
Delay time, MCI↓ to CO
See Figure 9
Differential output signal rise time, CO
RL = 100 Ω, CL = 10 pF,
See Figure 10
Output signal rise time, DCO, DO-n
CL = 10 pF, See Figure 11
Differential output signal fall time, CO
RL = 100 Ω, CL = 10 pF,
See Figure 10
Output signal fall time, DCO, DO-n
CL = 10 pF, See Figure 11
tsk(p)
Pulse skew (| tPHL – tPLH|), CO
RL = 100 Ω, CL = 10 pF,
See Figure 10
tPZH
Propagation delay time, high-impedance to high-level output
(DCO only)
tr
tf
MIN
Delay time, MCI↑ to DO–n
See Figure 8
Hold time, DCO↑ to DO-n valid
TYP
MAX
2
3
3.3
5.5
UNIT
ns
5
5
tPZL
tPHZ
Propagation delay time, high-impedance to low-level output
tPLZ
Propagation delay time, low-level to high-impedance output
tPZH
Propagation delay time, high-impedance to high-level output
(DCO only)
Propagation delay time, high-level to high-impedance output
tPZL
tPHZ
Propagation delay time, high-impedance to low-level output
tPLZ
Propagation delay time, low-level to high-impedance output
Propagation delay time, high-level to high-impedance output
POST OFFICE BOX 655303
DCO DO-n,
DO-n
EN to DCO,
F,
CL = 10 pF,
g
See Figure
12
LVI to DCO,
DCO DO-n
CL = 10 pF,
F,
g
See Figure
12
• DALLAS, TEXAS 75265
0.3
0.3
2.9
4.5
0.8
1.5
0.6
1.5
0.8
1.5
0.6
1.5
0
300
5
15
5
15
5
15
6
15
5
15
5
15
5
15
5
15
ns
ns
ns
ps
ns
ns
9
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
+
VID
–
(VI+ + VI–)/2
VI+
VIC
VI–
Figure 4. Receiver Voltage Definitions
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Table 3. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED
VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VI+
1.25 V
VI–
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
+
IO+
IO–
VOD
VO+
–
VO–
VOC
(VO+ + VO–)/2
Figure 5. Driver Voltage and Current Definitions
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
3.74 kΩ
+
VOD
+
_
100 Ω
0 V ≤ Vtest ≤ 2.4 V
–
3.74 kΩ
Figure 6. VOD Test Circuit
49.9 Ω ±1% (2 PLCS)
VOC(PP)
+
VOC(SS)
VOC
–
50 pF
VOC
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
Pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 5 GHz.
Figure 7. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
LCI
0V
tsu(2)
MCI
0V
td(2)
td(1)
DCO
1.4 V
DO–n
1.4 V
tsu(4)
th(4)
Figure 8. Data Clock and Data Output Timing Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
0V
MCI
td(3)
0V
CO
Figure 9. MCI to CO Timing Waveforms
+
DI (0–9)
Logic
LCI
100 Ω ±1%
VOD
CO
–
MCI
CL = 10 pF
(2 PLCS)
DUT
0.4 V
MCI
0V
–0.4 V
tPLH
tPHL
100%
80%
VOD(H)
CO
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 100 Mpps,
Pulse width = 5 ± 0.1 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 10. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
DI
V OH
80%
MCI
LCI
DUT
DCO,
DO–n
VO
1.4 V
20%
tf
tr
V OL
CL = 10 pF
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, MCI pulse repetition rate (PRR) = 50 Mpps,
Pulse width = 10 ± 0.2 ns . LCI pulse repetition rate (PRR) = 5 Mpps, pulsewidth = 100 ±2 ns. CL includes instrumentation and fixture
capacitance within 0,06 m of the D.U.T.
Figure 11. Timing Test Circuit and Waveforms
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
PARAMETER MEASUREMENT INFORMATION
DI
500 Ω
MCI
DUT
EN
VO
LVI
V test
+
_
CL = 10 pF
NOTE: VTEST = 2.5 V for tPZL or tPLZ, VTEST = 0 V for tPZH or tPHZ. All input pulses are supplied by a generator having the following
characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns . CL includes instrumentation and fixture
capacitance within 0,06 m of the D.U.T.
2V
1.4 V
EN,
LVI
0.8 V
tPLZ
tPZL
2.5 V
1.4 V
VOL+0.5 V
VOL
2V
1.4 V
EN,
LVI
0.8 V
tPHZ
tPZH†
VOH
VOH–0.5 V
1.4 V
0V
† DCO only
Figure 12. Enable/Disable Time Test Circuit and Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
FREQUENCY
I CC – Average Supply Current – mA
40
VCC = 3.3 V,
TA = 25°C
35
30
25
20
15
10
5
0
0
50
100
150
200
f – Frequency – Hz
Figure 13. Average Supply Current vs Frequency
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS152
MuxIt RECEIVER-DESERIALIZER
SLLS445 – DECEMBER 2000
MECHANICAL DATA
DA (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
38 PINS SHOWN
0,30
0,19
0,65
38
0,13 M
20
6,20
NOM
8,40
7,80
0,15 NOM
Gage Plane
1
19
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
30
32
38
A MAX
11,10
11,10
12,60
A MIN
10,90
10,90
12,40
DIM
4040066 / D 11/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS152DA
ACTIVE
TSSOP
DA
32
SN65LVDS152DAR
ACTIVE
TSSOP
DA
SN65LVDS152DARG4
ACTIVE
TSSOP
DA
46
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
32
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
32
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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information may not be available for release.
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Addendum-Page 1
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