TI SN65LVDS108DBT

SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
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D
D
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D
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DBT PACKAGE
(TOP VIEW)
One Line Receiver and Eight Line Drivers
Configured as an 8-Port LVDS Repeater
Line Receiver and Line Drivers Meet or
Exceed the Requirements of ANSI
EIA/TIA-644 Standard
Designed for Signaling Rates up to
622 Mbps
Enabling Logic Allows Individual Control of
Each Driver Output, Plus all Outputs
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100Ω Load
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
Propagation Delay Times < 4.7 ns
Output Skew Less Than 300 ps and
Part-to-Part Skew Less Than 1.5 ns
Total Power Dissipation at 200 MHz
Typically Less Than 330 mW With 8
Channels Enabled
Driver Outputs or Receiver Input Equals
High Impedance When Disabled or With
VCC < 1.5 V
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
GND
VCC
GND
NC
ENM
ENA
ENB
ENC
END
A
B
ENE
ENF
ENG
ENH
NC
GND
VCC
GND
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
ANC
AY
AZ
BY
BZ
CY
CZ
DY
DZ
EY
EZ
FY
FZ
GY
GZ
HY
HZ
NC
NC
description
The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers.
Individual output enables are provided for each output and an additional enable is provided for all outputs.
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. It can be used to transmit data at speeds up to at
least 622 Mbps and over relatively long distances. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
The intended application of this device, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The
large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced
signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is
particularly advantageous for implementing system clock or data distribution trees.
The SN65LVDS108 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
logic diagram (positive logic)
AY
ENA
AZ
ENM
BY
BZ
ENB
CY
CZ
ENC
DY
END
DZ
A
B
EY
ENE
EZ
FY
FZ
ENF
GY
GZ
ENG
HY
HZ
ENH
selection guide to LVDS splitter
The SN65LVDS108 is one member of a family of LVDS splitters and repeaters. A brief overview of the family
is provided in the following table.
LVDS SPLITTER AND REPEATER FAMILY
NUMBER
OF INPUTS
NUMBER OF
OUTPUTS
SN65LVDS104
1 LVDS
4 LVDS
16-pin D
4-Port LVDS Repeater
SN65LVDS105
1 LVTTL
4 LVDS
16-pin D
4-Port TTL-to-LVDS Repeater
SN65LVDS108
1 LVDS
8 LVDS
38-pin DBT
8-Port LVDS Repeater
SN65LVDS109
2 LVDS
8 LVDS
38-pin DBT
Dual 4-Port LVDS Repeater
SN65LVDS116
1 LVDS
16 LVDS
64-pin DGG
16-Port LVDS Repeater
SN65LVDS117
2 LVDS
16 LVDS
64-pin DGG
Dual 8-Port LVDS Repeater
DEVICE
2
PACKAGE
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COMMENTS
• DALLAS, TEXAS 75265
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
FUNCTION TABLE
OUTPUTS
INPUTS
VID = VA – VB
X
ENM
ENx
xY
xZ
L
X
Z
Z
X
X
L
Z
Z
VID ≥ 100 mV
–100 mV < VID < 100 mV
H
H
H
L
H
H
?
?
VID ≤–100 mV
H
H
L
H
H = high level, L = low level, Z = high impedance, X = don’t care,
? = indeterminate
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
(ENM Only)
300 kΩ
300 kΩ
50 Ω
Enable
Inputs
A Input
10 kΩ
5Ω
Y or Z
Output
7V
B Input
7V
300 kΩ
7V
7V
(ENx Only)
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge, Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B: 500 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 85°C
POWER RATING
DBT
1277 mW
10.2 mW/°C
644 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
with no air flow.
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3
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
0.1
V
Ť
Common-mode input voltage, VIC
ID
2
Operating free-air temperature, TA
UNIT
3.6
V
V
Low-level input voltage, VIL
Magnitude of differential input voltage, VID
MAX
0.8
V
3.6
V
V
Ť
Ť
2.4 –
ID
2
Ť
V
VCC – 0.8
85
–40
V
°C
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
ICC
Supply current
II
Input current (A or B inputs)
II(OFF)
IIH
Power-off input current (A or B inputs)
IIL
Low-level input current (enables)
IOS
Short circuit output current
Short-circuit
IOZ
IO(OFF)
High-impedance output current
CIN
Input capacitance (A or B inputs)
CO
Output capacitance (Y or Z outputs)
Negative-going differential input voltage threshold
See Figure 1 and Table 1
RL= 100 Ω
Ω,
VID= ±100 mV,
mV
See Figure 1 and Figure 2
See Figure 3
Enabled,
High-level input current (enables)
Power-off output current
247
340
–50
50
1.125
1.375
–50
50
50
150
62
85
8
12
–2
UNIT
mV
454
–20
–1.2
mV
V
mV
mA
µA
20
µA
±20
µA
VIL = 0.8 V
VOY or VOZ = 0 V
±10
µA
VOD = 0 V
VO = 0 V or VCC
±12
VCC = 1.5 V,
VIH = 2 V
VI = 2.4 V
VCC = 1.5 V,
VO = 3.6 V
VI = 0.4 sin (4E6πt) + 0.5 V
POST OFFICE BOX 655303
MAX
–100
RL = 100 Ω
VI = 0 V
VI = 2.4 V
TYP†
100
Disabled
VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled
† All typical values are at 25°C and with a 3.3 V supply.
4
MIN
• DALLAS, TEXAS 75265
±24
mA
±1
µA
±1
µA
5
9.4
pF
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
MIN
TYP†
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
1.6
2.8
4.5
Propagation delay time, high-to-low-level output
1.6
2.8
4.5
tr
tf
Differential output signal rise time
0.3
0.8
1.2
0.3
0.8
1.2
150
500
PARAMETER
tsk(p)
tsk(o)
TEST CONDITIONS
RL = 100 Ω,
CL = 10 pF,
See Figure 4
Differential output signal fall time
Pulse skew (|tPHL - tPLH|)‡
Output skew§
300
tsk(pp)
tPZH
Part-to-part skew#
tPZL
tPHZ
Propagation delay time, high-impedance-to-low-level output
1.5
Propagation delay time, high-impedance-to-high-level output
See Figure 5
Propagation delay time, high-level-to-high-impedance output
5.7
15
7.7
15
3.2
15
UNIT
ns
ns
ps
ns
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
3.2
15
ns
† All typical values are at 25°C and with a 3.3 V supply.
‡ tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
§ tsk(o) is the magnitude of the time difference between the tPLH or tPHL measured at any two outputs.
# tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
IIA
IIB
VID
IOY
A
Y
B
Z
VIA
IOZ
VOD
VOY
VOZ
VIB
VOC
(VOY + VOZ)/2
Figure 1. Voltage and Current Definitions
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5
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VIA
1.25 V
VIB
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
-100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
-100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
-100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
-600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
-600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
-600 mV
0.3 V
3.75 kΩ
Y
100 Ω
3.75 kΩ
VOD
Input
Z
±
0 V ≤ VTEST ≤ 2.4 V
Figure 2. VOD Test Circuit
49.9 Ω ± 1% (2 Places)
Y
Input
Input
VI
1.4 V
VI
1V
Z
50 pF
VOC(PP)
VOC
VOC(SS)
VO
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulsewidth = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
6
POST OFFICE BOX 655303
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SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
A
Y
B
Z
Input
1.4 V
1.2 V
1V
VIB
Input
VIA
tPLH
VOD
tPHL
100 Ω ± 1 %
VOD(H)
Output
CL = 10 pF
(2 Places)
100%
80%
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulsewidth = 10 ±0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Y
1 V or 1.4 V
49.9 Ω ± 1% (2 Places)
Z
1.4 V or 1 V
1.2 V
CL = 10 pF
ENM (2 Places)
ENx
Inputs
VOY
VOZ
2V
1.4 V
0.8 V
Input
VOY
or
VOZ
tPZH
tPHZ
100%, ≅ 1.4 V
50%
0%, 1.2 V
tPZL
tPLZ
100%, 1.2 V
VOZ
50%
or
0%, ≅ 1 V
VOY
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
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SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
I CC – Supply Current – mA
120
VCC = 3.6 V
100
VCC = 3 V
80
VCC = 3.3 V
60
40
20
All Outputs Loaded
and Enabled
0
0
50
100
150
200
250
300
3.8
t PLH – Low-To-High Propagation Delay Time – ns
140
3.7
3.6
3.5
VCC = 3.3 V
3.4
VCC = 3 V
VCC = 3.6 V
3.3
3.2
3.1
–50
350
–25
0
Figure 6
Figure 7
t PHL – High-To-Low Propagation Delay Time – ns
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.7
3.6
3.5
3.4
3.3
VCC = 3.3 V
VCC = 3.6 V
VCC = 3 V
3.2
3.1
3.0
2.9
–50
–25
0
25
50
75
TA – Free–Air Temperature – °C
Figure 8
8
25
50
TA – Free–Air Temperature – °C
f – Frequency – MHz
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100
75
100
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
Figure 9. Typical Differential Eye Pattern at 400 Mbps
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9
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
The SN65LVDS108 device solves several problems common to the distribution of timing critical clock and data
signals. These problems include:
D
D
D
D
D
Excessive skew between the signal paths
Noise pickup over long signaling paths
High power consumption
Control of which signal paths are enabled or disabled
Elimination of radiation from unterminated lines
Buffering and splitting the signal on the same silicon die minimizes corruption of the timing relation between the
copies of the signal. Buffering and splitting the signal in separate devices will introduce considerably higher
levels of uncontrolled timing skew between the signals. Higher speed operation and more timing tolerance for
other components of the system is enabled by the tighter system timing budgets provided by the single die
implementations of the SN65LVDS108.
The use of LVDS signaling technology for both the inputs and the outputs provides superior common-mode and
noise tolerance compared to single-ended I/O technologies. This is particularly important because the signals
that are being distributed must be transmitted over longer distances, and at higher rates, than can be
accommodated with single-ended I/Os. In addition, LVDS consumes considerably less power than other
high-performance differential signaling schemes.
The enable inputs provided for each output may be used to turn on or off any of the paths. This function is
required to prevent radiation of signals from the unterminated signal lines on open connectors when boards or
devices are being swapped in the end equipment. The individual channel enables are also required if redundant
paths are being utilized for reliability reasons.
The following diagram shows how an input signal is being identically repeated out two of the available outputs.
A third output is shown in the disabled state.
SOURCE
EQUIPMENT/
BOARD
n-PORT REPEATER
DESTINATION
EQUIPMENT/
BOARD #1
Output Pair Disabled
DESTINATION
EQUIPMENT/
BOARD #2
DESTINATION
EQUIPMENT/
BOARD #n
Figure 10. LVDS Repeating Splitter Application Example Showing Individual Path Control
10
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SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
A LVDS receiver can be used to receive various other types of logic signals. Figure 12 through Figure 20 show the
termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
VDD
25 Ω
50 Ω
A
50
Ω
1/2 VDD
B
0.1 µF
LVDS Receiver
Figure 11. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
VDD
50 Ω
A
50 Ω
B
1.35 V < VTT < 1.65 V
0.1 µF
LVDS Receiver
Figure 12. Center-Tap Termination (CTT)
1.14 V < VTT < 1.26 V
VDD
1 kΩ
50 Ω
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 13. Gunning Transceiver Logic (GTL)
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11
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Z0
Z0
A
B
1.47 V < VTT < 1.62 V
0.1 µF
LVDS Receiver
Figure 14. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
50 Ω
120 Ω
120 Ω
33 Ω
ECL
A
50 Ω
33 Ω
B
51 Ω
51 Ω
LVDS Receiver
Figure 15. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
12
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SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
5V
5V
82 Ω
50 Ω
82 Ω
100 Ω
ECL
A
50 Ω
100 Ω
B
33 Ω
33 Ω
LVDS Receiver
Figure 16. Positive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 17. 3.3-V CMOS
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13
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
5V
5V
10 kΩ
560 Ω
A
B
560 Ω
3.32 kΩ
0.1 µF
LVDS Receiver
Figure 18. 5-V CMOS
5V
5V
10 kΩ
470 Ω
A
B
3.3 V
4.02 kΩ
0.1 µF
Figure 19. TTL
14
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LVDS Receiver
SN65LVDS108
8-PORT LVDS REPEATER
SLLS399A – NOVEMBER 1999 – REVISED MARCH 2000
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
DIM
4073252/D 09/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
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15
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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