STMICROELECTRONICS STM1404CTOCQ6F

STM1404
3 V FIPS-140
security supervisor with battery switchover
Features
■
■
■
■
STM1404 supports FIPS-140 security level 4
– Four high-impedance physical tamper
inputs
– Over/under operating voltage detector
– Security alarm (SAL) on tamper detection
– Over/under operating temperature detector
– Over/under temperature thresholds are
customer-selectable and factoryprogrammed
Supervisory functions
– Automatic battery switchover
– RST output (open drain)
– Manual (push-button) reset input (MR)
– Power-fail comparator (PFI/PFO)
Vccsw (VCC switch output)
– Low when switched to VCC
– High when switched to VBAT (BATT ON
indicator)
QFN16, 3 mm x 3 mm (Q)
■
Optional VREF (1.237 V)
– (Available for STM1404A only)
■
Low battery supply current (5.3 µA typ)
■
Secure low profile 16-pin, 3 x 3 mm, QFN
package
■
RoHS compliance
– Lead-free components compliant with the
RoHS directive
Battery low voltage detector (power-up)
Table 1.
Device summary
Device
Physical Over/under Over/under
VREF
Standard
VOUT status,
voltage
temperature (1.237 V)
supervisory tamper
during alarm
(1)
inputs
alarms
alarms
option
functions
Vccsw status,
during alarm
STM1404A
✔
✔
✔
✔
✔
ON
Normal mode(2)
STM1404B(3)
✔
✔
✔
✔
Note(4)
High-Z
High
✔
Note(4)
Ground
High
STM1404C
✔
✔
✔
1. Reset output, power-fail comparator, battery low detection (SAL, RST, PFO, and BLD are open drain).
2. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to battery.
3. Contact local ST sales office for availability.
4. Pin 9 is the VREF pin for STM1404A. It is the VTPU pin for STM1404B/C.
August 2008
Rev 5
1/36
www.st.com
1
Contents
STM1404
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
2
VOUT pin modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1
STM1404A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.2
STM1404B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.3
STM1404C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
SAL, security alarm output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
TP1, TP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
TP2, TP4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1
3
4
2.4
BLD, VBAT low voltage detect output (open drain) . . . . . . . . . . . . . . . . . . 13
2.5
Active-low RST output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6
MR, manual reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7
PFO, power-fail output (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8
PFI, power-fail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9
VREF, reference voltage output (1.237, typ) . . . . . . . . . . . . . . . . . . . . . . . 14
2.10
VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11
VTPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.13
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.14
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2
Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3
Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Negative-going VCC transients and undershoot . . . . . . . . . . . . . . . . . . . . 17
Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
2/36
Vccsw, VCC switch output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM1404
Contents
4.2
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3/36
List of tables
STM1404
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
4/36
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Physical and environmental tamper detection levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size mechanical data . . . . 32
Ordering information scheme (see Figure 31 on page 34 for marking information) . . . . . . 33
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM1404
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QFN16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch closed) . . . . . . . . . 10
Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch open). . . . . . . . . . . 10
Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch closed) . . . . . . . . . . 10
Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch open). . . . . . . . . . . . 11
Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VBAT -to-VOUt on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VCC to reset propagation delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM1404 switchover diagram, condition A (VBAT < VSW) . . . . . . . . . . . . . . . . . . . . . . . . . 26
STM1404 switchover diagram, condition B (VBAT > VSW) . . . . . . . . . . . . . . . . . . . . . . . . . 26
Temperature hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline . . . . . . . . . . . 31
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended footprint . . . . . . 32
Topside marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5/36
Description
1
STM1404
Description
The STM1404 family of security supervisors are a low power family of intrusion (tamper)
detection chips targeted at manufacturers of POS terminals and other systems, to enable
them to meet physical and/or environmental intrusion monitoring requirements as
mandated by various standards, such as Federal Information Processing Standards (FIPS)
Pub 140 entitled “Security Requirements for Cryptographic Modules,” published by the
National Institute of Standards and Technology, U.S. Department of Commerce), EMVCo,
ISO, ZKA, and VISA PED.
STM1404 will target the highest security level 4 and include both physical and
environmental (voltage and temperature) monitoring.
The STM1404 include automatic battery switchover, RST output (open drain), manual
(push-button) reset input (MR), power-fail comparator (PFI/PFO), physical and/or
environmental tamper detect/security alarm, and battery low voltage detect features.
The STM1404A also offers a VREF (1.237V) as an option on pin 9. On STM1404B/C this pin
is VTPU (internally switched VCC or VBAT).
1.1
VOUT pin modes
The STM1404 is available in three versions, corresponding to three modes of the VOUT pin
(supply voltage out), when the SAL (security alarm) is asserted (active-low) upon tamper
detection:
1.1.1
STM1404A
VOUT stays ON (at VCC or VBAT) when SAL is driven low (activated).
1.1.2
STM1404B
VOUT is set to High-Z when SAL is driven low (activated).
1.1.3
STM1404C
VOUT is driven to ground when SAL is activated (may be used when VOUT is connected
directly to the VCC pin of the external SRAM that holds the cryptographic codes).
All variants (see Table 1: Device summary) are pin-compatible and available in a securityfriendly, low profile, 16-pin QFN package.
6/36
STM1404
Description
Figure 1.
Logic diagram
VREF
BLD(3) or VBAT VCC
VTPU(1)
VCCSW(2)
VOUT
RST(3)
MR
STM1404
PFI
PFO(3)
TP1 (NH)
SAL(3)
TP2 TP3
(NL) (NH)
TP4 VSS
(NL)
AI09682a
1. VREF only for STM1404A; VTPU for STM1404B/C.
2. Normal mode: low when VOUT is internally switched to VCC and High when VOUT is internally switched to
battery.
3. SAL, RST, PFO, and BLD are open drain.
Table 2.
Signal names
Vccsw(1)
VCC switch output
MR
Manual (push-button) reset input
PFI
Power-fail input
TP1 - TP4
Independent physical tamper detect pins 1 through 4
VOUT
Supply voltage output
RST(2)
Active-low reset output
PFO
(2)
SAL(2)
BLD
(2)
VREF(3)
VTPU
(3)
Power-fail output
Security alarm output
Battery low voltage detect
1.237 V reference voltage
Tamper pull-up (VCC or VBAT)
VBAT
Backup supply voltage
VCC
Supply voltage
VSS
Ground
1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
2. SAL, RST, PFO, and BLD are open drain.
3. VREF only for STM1404A; VTPU for STM1404B/C.
Note:
See Section 2: Pin descriptions on page 11 for details.
7/36
Description
STM1404
Figure 2.
QFN16 connections
BLD(2) PFI VCCSW(1) VCC
15
14
RST(2)
1
13
12
VOUT
MR
2
11
VBAT
SAL(2)
3
10
PFO(2)
VSS
4
16
5
6
7
TP1 TP2 TP3
(NH) (NL) (NH)
Note:
8
9
TP4
(NL)
VREF or VTPU(3)
AI09683
See Section 2: Pin descriptions on page 11 for details.
1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
2. SAL, RST, PFO, and BLD are open drain.
3. VREF only for STM1404A; VTPU for STM1404B/C.
Figure 3.
Block diagram
VCC
VOUT
BAT54J(1,2)
COMPARE
VSO
VBAT(1)
VCCSW
VINT
COMPARE
VRST
trec
Generator
MR
PFI
RST(3)
VPFI
COMPARE
PFO(3)
VDET
COMPARE @
POWER-UP
BLD(3)
VTPU(4)
1.237V VREF
Generator
VHV
COMPARE
VLV
COMPARE
VREF(4)
TP1 (NH)
TP2 (NL)
SAL(3)
TP3 (NH)
TP4 (NL)
High Temp.
Sense
TA > TH
Low Temp.
Sense
TA < TL
1. Required for battery-reverse charging protection
2. User supplied
3. Open drain
4. VREF only for STM1404A; VTPU for STM1404B/C
8/36
AI09684a
STM1404
Description
Figure 4.
Hardware hookup
VCCSW(1)
Regulator
Unregulated
Voltage
VIN
VCC
VCC
VCC
VOUT
VCC
C(2)
0.1μF
STM1404
LPSRAM
R1
PFI
PFO(3)
To Microprocessor NMI
MR
RST(3)
To Microprocessor Reset
VBAT
BLD(3)
To Microprocessor
R2
Push-Button
BAT54J(4)
1.0μF
TP1
TP2
TP3
From Actuator Device
(e.g., Switches, Wire Mesh)
SAL(3)
TP4
VREF(5)
or
VTPU
To ADC
To Physical Tamper Pins TPX
AI09690a
1. Normal mode: low when VOUT is internally switched to VCC and high when VOUT is internally switched to
battery.
2. Capacitor (C) is typically ≥ 10 µF.
3. Open drain
4. Diode is required for battery reverse charge protection.
5. VREF only for STM1404A; VTPU for STM1404B/C
Figure 5.
Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch
closed)
VOUT (STM1404A)
or
VTPU (STM1404B/C)
Switch Normally Closed;
Tamper Detection on Open
TP1 or TP3
R(1)
AI09698a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
9/36
Description
STM1404
Figure 6.
Tamper pin (TP1 or TP3) normally high (NH) external hookup (switch
open)
VOUT (STM1404A)
or
VTPU (STM1404B/C)
R(1)
TP1 or TP3
Switch Normally Open
Tamper Detection when Closed
AI10461a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 7.
Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch
closed)
VOUT (STM1404A)
or
VTPU (STM1404B/C)
R(1)
TP2 or TP4
Switch Normally Closed;
Tamper Detection on Open
AI09699a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
Figure 8.
Tamper pin (TP2 or TP4) normally low (NL) external hookup (switch open)
VOUT (STM1404A)
or
VTPU (STM1404B/C)
Switch Normally Open;
Tamper Detection when Closed
TP2 or TP4
R(1)
AI10462a
1. R typical is 10 MΩ. Resistors must be protected against conductive materials.
10/36
STM1404
2
Pin descriptions
Pin descriptions
See Figure 1: Logic diagram and Table 2: Signal names for a brief overview of the signals
connected to this device.
2.1
SAL, security alarm output (open drain)
This signal can be generated when ANY of the following conditions occur:
Note:
2.2
●
VINT > VHV, where VHV = upper voltage trip limit (4.2 V typ); and where VINT = VCC or
VBAT;
●
VINT < VLV, where VLV = lower voltage trip limit (2.0 V typ); and where VINT = VCC or
VBAT; or
●
When any of the physical tamper inputs, TP1 to TP4, change from their normal states to
the opposite (i.e., intrusion of a physical enclosure).
●
TA > TH, where TH is an upper temperature trip limit specified by the customer (+80°C,
+85°C, and +95°C), factory-programmed (STM1404 only);
●
TA < TL, where TL is a lower temperature trip limit specified by the customer (–25°C or
–35°C), factory-programmed (STM1404 only);
1
The default state of the SAL output during initial power-up is undetermined.
2
The alarm function will operate either with VCC on or when the part is internally switched
from VCC to VBAT.
TP1, TP3
Physical tamper detect pin set normally to high (NH). They are connected externally through
a closed switch or a high-impedance resistor to VOUT (in the case of STM1404A) or VTPU (in
the case of STM1404B/C. A tamper condition will be detected when the input pin is pulled
low (see Figure 5 and Figure 6 on page 10). If not used, tie the pin to VOUT (for STM1404A)
or VTPU (for STM1404B/C).
2.3
TP2, TP4
Physical tamper detect pin set normally to low (NL). They are connected externally through
a high-impedance resistor or a closed switch to VSS. A tamper condition will be detected
when the input pin is pulled high (see Figure 7 and Figure 8 on page 10). If not used, tie the
pin to VSS.
2.3.1
Vccsw, VCC switch output
This output is low when VOUT (see Section 2.10: VOUT on page 13) is internally switched to
VCC; in this mode it may be used to turn on an external p-channel MOSFET switch which
can source an external device directly from VCC for currents greater than 80 mA (bypassing
the STM1404).
This pin goes high when VOUT is internally switched to VBAT and may be used as a
“BATTERY ON” indicator.
11/36
Pin descriptions
STM1404
If a security alarm (SAL) is issued on tamper, then the state of the Vccsw pin is as follows:
2.4
1.
STM1404A (VOUT remains ON when SAL is active-low): Vccsw pin will continue to
operate in normal mode;
2.
STM1404B (VOUT is taken to High-Z when SAL is active-low): Vccsw pin will be set to
high when this occurs; and
3.
STM1404C (VOUT is driven to ground when SAL is active-low): Vccsw pin will be set to
high when this occurs.
BLD, VBAT low voltage detect output (open drain)
This is an internally loaded test of the battery, activated only during a power-up sequence to
insure that the battery is good either prior to or after encapsulation of the module. There are
three customer options for VDET:
●
2.3 V (2.5 V – external diode drop of about 0.2 V) for a 3 V lithium cell
●
2.5 V (2.7 V – 0.2 V) for a 3 V lithium cell or
●
3.2 V (3.4 V – 0.2 V) for a 3.68 V lithium “AA” battery
This output pin will go active-low when it detects a voltage on the VBAT pin below VDET. BLD
will be released when VCC drops below VRST.
2.5
Active-low RST output (open drain)
Goes low and stays low when VCC drops below VRST (Reset Threshold selected by the
customer), or when MR is logic low. It remains low for trec (200ms, typical) AFTER VCC rises
above VRST and MR goes from low to high.
2.6
MR, manual reset input
A logic low on MR asserts the RST output. The RST output remains asserted as long as MR
is low and for trec after MR returns to high. This active low input has an internal 40 kΩ
(typical) pull-up resistor. It can be driven from a TTL or CMOS logic line or shorted to ground
with a switch. Leave it open if unused.
2.7
PFO, power-fail output (open drain)
When PFI is less than VPFI (power-fail input threshold voltage) or VCC falls below VSW
(battery switchover threshold ~ 2.4 V), PFO goes low, otherwise, PFO remains high. Leave
this pin open if unused.
2.8
PFI, power-fail input
When PFI is less than VPFI, or when VCC falls below VSW (see PFO, above), PFO goes
active-low. If this function is unused, connect this pin to VSS.
12/36
STM1404
2.9
Pin descriptions
VREF, reference voltage output (1.237, typ)
This is valid only when VCC is between 2.4 V and 3.6 V. When VCC falls below 2.4 V (VSW),
VREF is pulled to ground with an internal 100 kΩ resistor. This is an optional feature
available on the STM1404A. On the STM1404B/C, this pin is VTPU (internally switched VCC
or VBAT). If unused, this pin should float.
2.10
VOUT
This is the supply voltage output. When VCC rises above VSO (battery backup switchover
voltage), VOUT is supplied from VCC. In this condition, VOUT may be connected externally to
VCC through a p-channel MOSFET switch. When VCC falls below the lower value of VSW
(~2.4 V), or VBAT, VOUT is supplied from VBAT. It is recommended that the VOUT pin be
connected externally to a capacitor that will retain a charge for a period of time, in case an
intruder forces VCC or VBAT to ground. The rectifying diode connected from the positive
terminal of the battery to the VBAT pin of the STM1404 will prevent discharge of the
capacitor. Three variations of parts will be offered with the following options:
2.11
1.
STM1404A: VOUT remains ON when SAL is active-low; Vccsw pin will continue to
operate in normal mode (see Section 2.3.1: Vccsw, VCC switch output on page 11);
2.
STM1404B: VOUT is taken to High-Z when SAL is active-low; Vccsw pin will be set to
high when this occurs; and
3.
STM1404C: VOUT is driven to ground when SAL is active-low; Vccsw pin will be set to
high when this occurs.
VTPU
For STM1404B and STM1404C, this pin provides pull-up voltage for the physical tamper
pins (TP1-4). This pin is not to be used as voltage supply source for any other purpose.
Note:
VTPU is the internally switched supply voltage from either the VCC pin or the VBAT pin.
2.12
VCC
This is the supply voltage (2.2 V to 3.6 V).
2.13
VBAT
This is the secondary (backup battery) supply voltage. The pin is connected to the positive
terminal of the battery with a rectifying diode like the BAT54J from STMicroelectronics for
reverse charge protection. Voltage at this pin, after diode rectification, will be approximately
0.2 V less than the battery voltage, and will depend on the type of battery used as well as
the IBAT being drawn. (A capacitor of at least 1.0 µF connected between the VBAT pin and
VSS is required.) If no battery is used, connect the VBAT pin to the VCC pin.
2.14
VSS
Ground, VSS, is the reference for the power supply. It must be connected to system ground.
13/36
Operation
STM1404
3
Operation
3.1
Reset input
The STM1404 security supervisor asserts a reset signal to the MCU whenever VCC goes
below the reset threshold (VRST), or when the push-button reset input (MR) is taken low.
RST is guaranteed to be a logic low for 0 V < VCC < VRST if VBAT is greater than 1 V. Without
a backup battery, RST is guaranteed valid down to VCC =1V.
During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, trec. After this interval RST returns high.
If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold
the internal timer clears. The reset timer starts when VCC returns above the reset threshold.
3.2
Push-button reset input
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see
Figure 25 on page 24) after it returns high. The MR input has an internal 40 kΩ pull-up
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open-drain/collector outputs. Connect a normally open momentary switch from
MR to ground to create a manual reset function; external debounce circuitry is not required.
If MR is driven from long cables or the device is used in a noisy environment, connect a
0.1µF capacitor from MR to VSS to provide additional noise immunity. MR may float, or be
tied to VCC when not used.
3.3
Backup battery switchover
In the event of a power failure, it may be necessary to preserve the contents of external
SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices
automatically switch the SRAM to the backup supply when VCC falls.
Note:
If backup battery is not used, connect both VBAT and VOUT to VCC.
This family of security supervisors does not always connect VBAT to VOUT when VBAT is
greater than VCC. VBAT connects to VOUT (through a 100Ω switch) when VCC is below VSW
(~2.4 V) or VBAT (whichever is lower). This is done to allow the backup battery (e.g., a 3.6 V
battery) to have a higher voltage than VCC.
Assuming that VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered
before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most
external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO
point. VOUT is connected to VCC through a 3 Ω PMOS power switch.
Note:
14/36
The backup battery may be removed while VCC is valid, assuming VBAT is adequately
decoupled (0.1 µF typ), without danger of triggering a reset.
STM1404
Operation
Table 3.
I/O status in battery backup
Pin
Status
VOUT
Connected to VBAT through internal switch
VCC
Disconnected from VOUT
PFI
Disabled
PFO
Logic low
MR
Disabled
RST
Logic low
VBAT
Connected to VOUT
Vccsw
Logic high
VREF
Pulled to VSS below 2.4 V (VSW)
BLD
Logic high
VTPU
Connected to VBAT through an internal switch
The power-fail input (PFI) is compared to an internal reference voltage (independent from
the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail
output (PFO) will go low. This function is intended for use as an undervoltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see Figure 4 on page 9) to either the unregulated DC input (if it is available) or the
regulated output of the VCC regulator. The voltage divider can be set up such that the
voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the
STM1404 or the microprocessor drops below the minimum operating voltage.
During battery backup, the power-fail comparator is turned off and PFO goes (or remains)
low (see Figure 9 on page 16). This occurs after VCC drops below VSW (~2.4 V). When
power returns, the power-fail comparator is enabled and PFO follows PFI. If the comparator
is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be
connected to MR so that a low voltage on PFI will generate a reset output.
3.4
Applications information
These supervisor circuits are not short-circuit protected. Shorting VOUT to ground excluding power-up transients such as charging a decoupling capacitor - destroys the
device. Decouple both VCC and VBAT pins to ground by placing 0.1 µF capacitors as close to
the device as possible.
15/36
Operation
STM1404
Figure 9.
Power-fail comparator waveform
VCC
VRST
VSW (2.4V)
trec
PFO
PFO follows PFI
PFO follows PFI
RST
AI08861a
3.5
Negative-going VCC transients and undershoot
The STM1404 devices are relatively immune to negative-going VCC transients (glitches).
Figure 23 on page 22 was generated using a negative pulse applied to VCC, starting at VRST
+ 0.3 V and ending below the reset threshold by the magnitude indicated (comparator
overdrive). The graph indicates the maximum pulse width a negative VCC transient can have
without causing a reset pulse. As the magnitude of the transient increases (further below the
threshold), the maximum allowable pulse width decreases. Any combination of duration and
overdrive which lies under the curve will NOT generate a reset signal. Typically, a VCC
transient that goes 100 mV below the reset threshold and lasts 40 µs or less will not cause a
reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the VCC pin
provides additional transient immunity (see Figure 10).
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on VCC that drive it to values below VSS by as much as
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
Figure 10. Supply voltage protection
VCC
VCC
0.1μF
DEVICE
VSS
AI02169
16/36
STM1404
Tamper detection
4
Tamper detection
4.1
Physical
There are four (4) high-impedance physical tamper detect input pins, 2 normally set to high
(NH) and 2 normally set to low (NL). Each input is designed with a glitch immunity (see
Table 7 on page 29). These inputs can be connected externally to several types of actuator
devices (e.g., switches, wire mesh). A tamper on any one of the four inputs that causes its
state to change will trigger the security alarm (SAL) and drive it to active-low. Once the
tamper condition no longer exists, the SAL will return to its normal high state.
TP1 and TP3 are set normally to high (NH). They are connected externally through a closed
switch or a high-impedance resistor to VOUT (in the case of STM1404A or STM1404A) or
VTPU (in the case of STM1404B/C), A tamper condition will be detected when the input pin
is pulled low (see Figure 5 and Figure 6 on page 10). If not used, tie the pin to VOUT or VTPU.
TP2 and TP4 are set normally to low (NL). They are connected externally through a highimpedance resistor or a closed switch to VSS. A tamper condition will be detected when the
input pin is pulled high (see Figure 7 and Figure 8 on page 10). If not used, tie the pin to
VSS.
4.2
Supply voltage
The internally switched supply voltage, VINT (either VCC input or VBAT input) is continuously
monitored. If VINT should exceed the over voltage trip point, VHV (set at 4.2V, typical), or
should go below the under voltage trip point, VLV (set at 2.0v, typical). SAL will be driven
active-low. Once the tamper condition no longer exists, the SAL pin will return to its normal
high state.
4.3
Temperature
The STM1404 has a built-in, bandgap-based sensor to monitor the temperature. If a preset
(customer-selectable, factory-programmed) over-temperature trip point (TH) or undertemperature trip point (TL) is exceeded, the SAL is asserted low.
When no tamper condition exists, SAL is normally high (see Section 2: Pin descriptions on
page 11).
When a tamper is detected, the SAL is activated (driven low), independent of the part type.
VOUT can be driven to one of three states, depending on which variant of STM1404 is being
used (see Table 1 on page 1):
Note:
●
ON
●
High-Z or
●
Ground (VSS)
The STM1404 must be initially powered above VRST to enable the tamper detection alarms.
For example, if the battery is on while VCC = 0 V, no alarm condition can be detected until
VCC rises above VRST (and trec expires). From this point on, alarms can be detected either
on battery or VCC. This is done to avoid false alarms when the device goes from no power to
its operational state.
17/36
Typical operating characteristics
STM1404
5
Typical operating characteristics
Note:
Typical values are at TA = 25°C.
VBAT - to - VOUT ON-RESISTANCE [Ω]
Figure 11. VBAT -to-VOUt on-resistance vs. temperature
220
VCC = 0V
200
VBAT = 2V
180
VBAT = 3V
160
VBAT = 3.3V
140
120
100
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE [°C]
140
AI09691
Figure 12. Supply current vs. temperature (no load)
30
Supply Current [µA]
25
20
2.5V
3.3V
15
3.6V
10
5
0
–50
–40
–30
–20
–10
0
10
20
30
40
TEMPERATURE [°C]
18/36
50
60
70
80
90
100
AI09692
STM1404
Typical operating characteristics
Figure 13. VPFI threshold vs. temperature
VPFI THRESHOLD [V]
1.255
1.250
1.245
VCC = 3.3V
1.240
1.235
VCC = 2.5V
1.230
VBAT = 3.0V
1.225
–50
–30
–10
10
30
50
70
90
110
TEMPERATURE [°C]
130
AI09693
PROPAGATION DELAY [µs]
Figure 14. Reset comparator propagation delay vs. temperature
24
22
VBAT = 3.0V
100mV OVERDRIVE
20
18
16
14
12
10
–60
–40
–20
0
20
40
60
80
TEMPERATURE [°C]
100
AI09143
Figure 15. Power-up trec vs. temperature
PROPAGATION DELAY [µs]
215
22
210
trec [ms]
24
VBAT = 3.0V
100mV OVERDRIVE
20
18
205
16
14
200
12
10
195 –60
–50
–40
–20
–30
–10
0
10
20
40
30
50
TEMPERATURE
[°C]
60
70
80
90
100
110
130
AI09143
TEMPERATURE [°C]
NORMALIZED RESET THRESHOLD
[V]
Figure 16. Normalized reset threshold vs. temperature
1.002
1.000
0.998
0.996
VBAT = 3.0V
0.994
–60
–40
–20
0
20
40
60
TEMPERATURE [°C]
80
100
120
140
AI09145
19/36
Typical operating characteristics
STM1404
Figure 17. PFI to PFO propagation delay vs. temperature
9
PROPAGATION DELAY [µs]
8
7
6
5
4
3
2
1
0
–60
–40
–20
0
20
40
60
80
100
120
TEMPERATURE [°C]
140
AI09148
Figure 18. RST output voltage vs. supply voltage
3.5
RST OUTPUT VOLTAGE [V]
3.0
2.5
VCC
2.0
VRST
1.5
1.0
0.5
0
500 ms/div
AI09149b
Figure 19. RST response time (assertion)
4.0
VCC LEVEL [V]
3.0
VCC
2.0
VRST
1.0
0.0
2 µs/div
20/36
AI09151b
STM1404
Typical operating characteristics
Figure 20. Power-fail comparator response time (assertion)
1.45
4.0
1.40
1.35
PFO
1.30
2.0
PFI
1.25
VPFI LEVEL [V]
VPFO LEVEL [V]
3.0
1.0
1.20
0.0
1.15
2µs/div
AI09153b
Figure 21. Power-fail comparator response time (de-assertion)
1.45
4.0
3.5
1.40
1.35
2.5
PFO
1.30
2.0
1.5
PFI
1.25
VPFI LEVEL (V)
VPFO LEVEL (V)
3.0
1.0
1.20
0.5
1.15
0.0
2 µs/div
AI09154
21/36
Typical operating characteristics
STM1404
Figure 22. VCC to reset propagation delay vs. temperature
PROPAGATION DELAY [µs]
60
50
40
10V/ms
30
1V/ms
0.25V/ms
20
10
0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE [°C]
AI09155
Figure 23. Maximum transient duration vs. reset threshold overdrive
TRANSIENT DURATION [µs]
250
200
150
100
50
0
1
10
100
1000
RESET COMPARATOR OVERDRIVE, VRST – VCC [mV]
22/36
10000
AI09156
STM1404
6
Maximum ratings
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 4.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
TSTG
Storage temperature (VCC off, VBAT off)
–55 to 150
°C
TSLD(1)
Lead solder temperature for 10 seconds
260
°C
–0.3 to VCC +0.3
V
VIO
Input or output voltage
VCC/VBAT
Supply voltage
–0.3 to 4.5
V
IO
Output current
20
mA
PD
Power dissipation
320
mW
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
23/36
DC and AC parameters
7
STM1404
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 5: Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 5.
Operating and AC measurement conditions
Parameter
STM1404
Unit
VCC/VBAT supply voltage
2.2 to 3.6
V
Ambient operating temperature (TA)
–40 to 85
°C
≤5
ns
Input pulse voltages
0.2 to 0.8VCC
V
Input and output timing ref. voltages
0.3 to 0.7VCC
V
Input rise and fall times
Figure 24. AC testing input/output waveforms
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI02568
Figure 25. MR timing waveform
MR
tMLRL
RST
tMLMH
trec
AI09694
24/36
STM1404
DC and AC parameters
Figure 26. STM1404 switchover diagram, condition A (VBAT < VSW)
VOUT
VCC = 3.3V
VRST
VSW = 2.4V
VBAT
VBAT – 75mV
VBAT – 35mV
AI10463
Figure 27. STM1404 switchover diagram, condition B (VBAT > VSW)
VOUT
VCC = 3.3V
VBAT
VSW = 2.4V
VSW + 40mV
AI10464
Table 6.
Sym
VCC,
VBAT(2)
DC and AC characteristics
Alternative
Description
Test condition(1)
Min
Operating voltage
TA = –40 to +85°C
2.2
VCC supply current
(STM1404A)
Typ
Max
Unit
3.6
V
50
65
µA
35
50
µA
Typ @ 3.3 V, 25°C
ICC
IBAT(3)
VOUT1
VOUT2
VTPU1
VCC supply current
(STM1404B,C)
VCC supply current in
battery backup mode
Excluding IOUT
(VBAT = 2.3 V, VCC = 2.0
V, MR = VCC)
25
35
µA
VBAT supply current in
battery backup mode
Excluding IOUT
(VBAT = 3.6 V)
5.3
8.0
µA
VOUT voltage (active)
VOUT voltage
(battery
backup)
Internal switched
supply voltage (active)
IOUT1 = 5 mA(4)
(VCC > VSW)
VCC – 0.03
VCC –
0.015
V
IOUT1 = 80 mA
(VCC > VSW)
VCC – 0.3
VCC – 0.15
V
IOUT1 = 250 µA,
VCC > VSW(4)
VCC –
0.0015
VCC –
0.0006
V
IOUT2 = 250 µA,
VBAT = 2.2 V
VBAT – 0.1
VBAT – 0.04
V
VBAT – 0.16
V
IOUT2 = 1 mA,
VBAT = 2.2 V
ISOURCE = 5 mA
(VCC > VSW)
VCC – 0.3
V
25/36
DC and AC parameters
Table 6.
STM1404
DC and AC characteristics (continued)
Alter-
Description
Test condition(1)
Internal switched
supply voltage (battery
backup)
ISOURCE = 1 mA
(VBAT = 2.2 V)
Input leakage current
(MR)
MR = 0 V; VCC = 3V
20
75
350
µA
Input leakage current
(PFI)
0 V = VIN = VCC
–25
2
+25
nA
Input leakage current
(TP1-TP4)
0 V = VIN = VCC
–1
+1
µA
ILO
Output leakage current
0 V = VIN = VCC(5)
–1
+1
µA
VIH
Input high voltage (MR)
VIL
Input low voltage (MR)
VOL
Output low voltage
(PFO, RST, Vccsw,
SAL, BLD)
Sym
VTPU2
ILI
VOL
26/36
native
Output low voltage
(RST)
VRST (max) < VCC < 3.6 V
Min
Typ
Max
VBAT – 0.10
Unit
V
0.7VCC
V
0.3VCC
V
VCC = VRST (max),
ISINK = 3.2 mA
0.3
V
IOL = 40 µA; VCC = 1.0 V;
VBAT = VCC;
TA = 0°C to 85°C
0.3
V
IOL = 200 µA;
VCC = 1.2 V; VBAT = VCC
0.3
V
STM1404
Table 6.
Sym
VOHB
DC and AC parameters
DC and AC characteristics (continued)
Alter-
Description
Test condition(1)
Min
VOH battery backup
(Vccsw)
ISOURCE = 100 µA
0.8VBAT
Pull-up supply voltage
(open drain)
RST, SAL, BLD, PFO
native
Typ
Max
Unit
V
3.6
V
1.237
1.262
V
10
20
mV
Power-fail comparator
VPFI
tPFD
PFI input threshold
PFI falling (VCC < 3.6 V)
PFI hysteresis
PFI rising (VCC < 3.6 V)
1.212
PFI to PFO
propagation delay
2
µs
VBAT > VSW
VSW
V
VBAT < VSW
VBAT
V
VBAT > VSW
VSW
V
VBAT < VSW
VBAT
V
VSW
2.4
V
Hysteresis
40
mV
Battery switchover
Powerdown
Battery backup
switchover voltage (6)(7)
VSO
Power-up
Battery low voltage detect
VDET
Battery detect
threshold
Voltage reference (option for STM1404A)
VREF
Voltage reference (see
Section 2.9: VREF,
reference voltage
output (1.237, typ) on
page 13)
IREF+
Source current
IREF–
Sink current
Vn
Output voltage noise
M
2.25
2.30
2.34
V
N
2.45
2.50
2.55
V
O
3.14
3.20
3.26
V
0°C to 85°C
1.212
1.237
1.262
V
–40° to 0°C
1.200
1.237
1.274
V
0°C to 85°C
15
25
µA
–40° to 0°C
10
15
µA
10
13
µA
10-100
µVrms
On powerup only
(8)
f = 100 Hz to 100 kH
27/36
DC and AC parameters
Table 6.
Sym
STM1404
DC and AC characteristics (continued)
Alternative
Description
Test condition(1)
Min
Typ
Max
Unit
VCC falling
3.00
3.075
3.15
V
VCC rising
3.00
3.085
3.17
V
VCC falling
2.85
2.925
3.00
V
VCC rising
2.85
2.935
3.02
V
VCC falling
2.55
2.625
2.70
V
VCC rising
2.55
2.635
2.72
V
140
200
280
ms
Reset thresholds
T
VRST(9)
Reset threshold
S
R
RST pulse width
trec
Push-button reset input
tMLMH
tMR
MR pulse width
tMLRL
tMRD
MR to RST output
delay
100
ns
60
500
ns
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VRST (max) to 3.6 V; and VBAT = 2.8 V (except where
noted); typical values are for 3.3 V and 25°C.
2. VCC supply current, logic input leakage, push-button reset functionality, PFI functionality, state of RST tested at
VBAT = 3.6 V, and VCC = 3.6 V. The state of RST and PFO is tested at VCC = VCC (min). VBAT is voltage measured at the
pin.
3. Tested at VBAT = 3.6 V, and VCC = 0 V.
4. Guaranteed by design.
5. The leakage current measured on the RST, SAL, PFO, and BLD pins are tested with the output not asserted (output high
impedance).
6. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW.
7. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV.
8. Maximum external capacitive load on VREF pin cannot exceed 1 nF.
9. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10 mV (typ) hysteresis, which prevents
internal oscillation.
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STM1404
Table 7.
DC and AC parameters
Physical and environmental tamper detection levels
Sym
Parameter
VHV
VLV
Test
conditions(1)
Min
Typ
Max
Unit
Overvoltage trip level
4.0
4.2
4.4
V
Undervoltage trip level
1.9
2.0
2.1
V
25
50
µs
SAL propagation delay time
(after over/under voltage detection)
VHV + 200 mV or
VLV – 200 mV
VHTP
Trip point for NH physical tamper
input pins (TP1 or TP3)
VOUT - 1.3(2)
VOUT - 0.3(2)
V
VLTP
Trip point for NL physical tamper
input pins (TP2 or TP4)
0.3
1.0
V
50
µs
SAL propagation delay time(3)
(after physical tamper pin
detection)
VHTP =
VOUT/VTPU;
VLTP = VSS
VDD = 3.6
30
Physical tamper input (TPX) glitch
immunity
TH
Factory-programmed
TL
THYST
Temperature hysteresis
15
IOUT = 0 mA
µs
–5
80, 85, 95
+5
°C
–5
–25, –35
+5
°C
10
°C
1. Valid for ambient operating temperature: TA = –40 to 85°C; VCC = VLV to VHV (except where noted). All physical and
environmental tamper functions are operational across the full temperature alarm range for STM1404.
2. In the case of STM1404A, physical tamper input pins (TPX) are referenced to VOUT (pin 12). In the case of STM1404B or
C, TPX are referenced to VTPU pin (pin 9).
3. VCC = VRST (max) to 3.6 V
Figure 28. Temperature hysteresis
TH
THYST(High)
Temperature
THYST(Low)
TL
SAL
AI11147b
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Package mechanical data
8
STM1404
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 29. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size, outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
E2
Ch
3
K
D2
QFN16-A
Note:
30/36
Drawing is not to scale.
STM1404
Package mechanical data
Table 8.
QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm body size mechanical
data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.25
0.18
0.30
0.010
0.007
0.012
D
3.00
2.90
3.10
0.118
0.114
0.122
D2
1.70
1.55
1.80
0.067
0.061
0.071
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
1.70
1.55
1.80
0.067
0.061
0.071
e
0.50
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
N
16
16
Figure 30. QFN16 – 16-lead, quad, flat package, no lead, 3 x 3 mm, recommended
footprint
1.60
3.55
AI09126
Note:
2.0
0.28
Substrate pad should be tied to VSS.
31/36
Part numbering
STM1404
9
Part numbering
Table 9.
Ordering information scheme (see Figure 31 on page 33 for marking information)
Example:
STM1404
A
T
M
D
Q
6
F
Device type
STM1404: over/under temperature detect
VOUT status (SAL = active-low)
A: VOUT = ON; Vccsw = normal mode
B(1): VOUT = High-Z; Vccsw = high
C: VOUT = ground; Vccsw = high
Reset threshold voltage
T: VRST = 3.00 V to 3.15 V
S: VRST = 2.85 V to 3.00 V
R: VRST = 2.55 V to 2.70 V
Battery low voltage detect threshold (VDET)
M: VDET = 2.3 V (typ)
N: VDET = 2.5 V (typ)
O: VDET = 3.2 V (typ)
Under (TL)/over (TH) temperature alarm thresholds (STM1404 only)
B: –25/+80°C
H: –35/+80°C
C: –25/+85°C
I: –35/+85°C
D: –25/+95°C
J: –35/+95°C
Package
Q = QFN16 (3 mm x 3 mm)
Temperature range
6 = –40 to 85°C
Shipping method
F = ECOPACK® package, tape & reel
1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST sales office
nearest you.
32/36
STM1404
Part numbering
Figure 31. Topside marking information
04
XXXX(1)
YWW(2)
AI12218
1. Options codes:
X = A, B, or C (for VOUT)
X = T, S, or R (for reset threshold)
X = M, N, or O (for battery low voltage detect threshold)
X = B, C, D, H, I, or J (for temperature alarm threshold)
2. Traceability codes
Y = Year
WW = Work Week
33/36
Revision history
10
STM1404
Revision history
Table 10.
34/36
Document revision history
Date
Revision
Changes
11-Oct-2004
1
26-Nov-2004
1.1
Corrected footprint dimensions; update characteristics (Figure 1, 2, 3, 4,
5, 6, 7, 8, 26, 27, 30 and Table 1, 2, 3, 6, 7).
22-Dec-2004
1.2
Update characteristics (Figure 4, Tables 6, 7, 9).
03-Feb-2005
1.3
Update characteristics (Figure 4, Tables 6, 7).
25-Feb-2005
1.4
Update temperature trip limits (Table 9)
06-May-2005
1.5
Update characteristics (Figure 3, 4, 28 and Table 6, 7).
05-Aug-2005
2
Removed STM1403 references (Figure 1, 2, 3, 4, 5, 6, 7, 8, 26, 27, 28
and Table 1, 2, 5, 6, 7, 9).
06-Jan-2006
3
Update status, characteristics, lead-free text, marking (Figure 4, 31 and
Table 6, 7, 9).
08-Feb-2007
4
Update cover page, Figure 3: Block diagram, Table 7: Physical and
environmental tamper detection levels, Figure 28: Temperature
hysteresis, and part numbering (Table 9.)
21-Aug-2008
5
Minor formatting changes; updated Table 1, 7 and Section 8.
First edition
STM1404
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