STP80NF12 N-channel 120V - 0.013Ω - 80A - TO-220 STripFET™ II Power MOSFET General features Type VDSS (@Tjmax) RDS(on) ID STP80NF12 120V <0.018Ω 80A (1) ■ Exceptional dv/dt capability ■ 100% avalanche tested ■ Application oriented characterization 3 1 2 TO-220 Description This MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced highefficiency, high-frequency isolated DC-DC converters for Telecom and Computer applications. It is also intended for any applications with low gate drive requirements. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STP80NF12 P80NF12 TO-220 Tube January 2007 Rev 4 1/12 www.st.com 12 Contents STP80NF12 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STP80NF12 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Value Symbol Parameter Unit STB_P_W80NF12 STP80NF12FP VDS VDGR VGS (1) Drain-source voltage (VGS = 0) 120 V Drain-gate voltage (RGS = 20KΩ) 120 V Gate-source voltage ± 22 V Drain current (continuous) at TC = 25°C 80 11 (2) A Drain current (continuous) at TC=100°C 60 60 (2) A IDM(3) Drain current (pulsed) 320 320 (2) A PTOT Total dissipation at TC = 25°C 300 45 W Derating factor 2.0 0.3 W/°C ID ID dv/dt(4) Peak diode recovery voltage slope VISO Insulation withstand voltage (DC) TJ Tstg 10 -- Operating junction temperature Storage temperature V/ns 2500 -55 to 175 V °C 1. Limited by Package 2. Limited only by maximum temperature allowed 3. Pulse width limited by safe operating area 4. Starting TJ = 25 oC, ID = 40A, VDD = 45V Table 2. Thermal data Value Symbol Parameter TO-247 D2PAK TO-220 Unit TO-220FP RthJC Thermal resistance junction-case Max 0.5 0.5 3.33 °C/W RthJA Thermal resistance junction-ambient Max 50 62.5 62.5 °C/W Tl Maximum lead temperature for soldering purpose 300 300 300 °C 3/12 Electrical characteristics 2 STP80NF12 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 250µA, VGS= 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ±20V VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS= 10V, ID= 40A Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd Typ. Max. 120 Unit V VDS = Max rating, IDSS Table 4. Min. VDS = Max rating @125°C 1 10 µA µA ±100 nA 2 V 0.013 0.018 Ω Dynamic Parameter Test conditions Forward transconductance VDS =15V, ID = 40A Input capacitance Output capacitance Reverse transfer capacitance VDS =25V, f=1 MHz, VGS=0 Total gate charge Gate-source charge Gate-drain charge Min. VDD = 80V, ID = 80A VGS =10V Typ. Max. Unit 80 S 4300 600 230 pF pF pF 140 23 51 189 nC nC nC Typ. Max. Unit 1. Pulsed: pulse duration=300µs, duty cycle 1.5% Table 5. Symbol td(on) tr td(off) tf 4/12 Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 50 V, ID= 40A, RG=4.7Ω, VGS=10V Figure 13 on page 8 Min. 40 145 134 115 ns ns ns ns STP80NF12 Electrical characteristics Table 6. Symbol Source drain diode Max Unit Source-drain current 80 A ISDM(1) Source-drain current (pulsed) 320 A VSD(2) Forward on voltage ISD=80A, VGS=0 1.3 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD=80A, ISD trr Qrr IRRM Parameter Test conditions di/dt = 100A/µs, VDD=35V, TJ = 150°C Min. Typ. 155 0.85 11 ns µC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/12 Electrical characteristics STP80NF12 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/12 STP80NF12 Electrical characteristics Figure 7. Gate charge vs. gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs. temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs. temperature Figure 12. Normalized BVDSS vs. temperature 7/12 Test circuit 3 STP80NF12 Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/12 STP80NF12 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STP80NF12 TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 10/12 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP80NF12 5 Revision history Revision history Table 7. Revision history Date Revision Changes 21-Jun-2004 2 Preliminary version 24-Jul-2006 3 The document has been reformatted, SOA updated 31-Jan-2007 4 Typo mistake on Table 1. 11/12 STP80NF12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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