STD25NF10L N-channel 100V - 0.030Ω - 25A - DPAK Low gate charge STripFET™ II Power MOSFET General features Type VDSS RDS(on) ID STD25NF10L 100V < 0.035Ω 25A ■ Exceptional dv/dt capability ■ 100% avalanche tested ■ Low threshold device ■ Logic level device 3 1 DPAK Description This Power MOSFET series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced highefficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STD25NF10LT4 D25NF10L DPAK Tape & reel July 2006 Rev 2 1/13 www.st.com 13 Contents STD25NF10L Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Packing mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 ................................................ 8 STD25NF10L 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Value Unit Drain-source voltage (VGS = 0) 100 V Drain-gate voltage (RGS = 20 kΩ) 100 V VGS Gate- source voltage ± 16 V ID(1) Drain current (continuous) at TC = 25°C 25 A ID Drain current (continuous) at TC = 100°C 21 A Drain current (pulsed) 100 A Total dissipation at TC = 25°C 100 W Derating Factor 0.67 W/°C Peak diode recovery avalanche energy 20 V/ns Single pulse avalanche energy 450 mJ -55 to 175 °C VDS VDGR IDM (2) Ptot dv/dt(3) EAS (4) Tstg Tj Parameter Storage temperature Max. operating junction temperature 1. Current limited by package 2. Pulse width limited by safe operating area. 3. ISD ≤25A, di/dt ≤300A/µs, VDD =V(BR)DSS, Tj ≤TJMAX 4. Starting Tj = 25 °C, ID = 12.5A VDD = 50V Table 2. Rthj-case Rthj-pcb TJ Thermal data Thermal resistance junction-case max Thermal resistance junction-pcb max (1) Maximum lead temperature for soldering purpose 1.5 °C/W 100 °C/W 275 °C 1. When Mounted on 1 inch2 FR-4 board, 2 oz of Cu. 3/13 Electrical characteristics 2 STD25NF10L Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter V(BR)DSS Drain-source breakdown voltage ID = 250µA, VGS =0 IDSS Zero gate voltage drain current (VGS = 0) VDS = Max rating VDS = Max rating, TC = 125°C IGSS Gate-body leakage current (VDS = 0) VGS = ± 16V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 12.5A VGS = 4.5V, ID = 12.5A Table 4. Symbol Test conditions Typ. Max. 100 Unit V 1 10 µA µA ±100 nA 2.5 V 0.030 0.035 0.035 0.040 Ω Ω Typ. Max. Unit 1 Dynamic Parameter Test conditions Min. gfs (1) Forward transconductance VDS = 15V, ID = 12.5A 24 S Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS = 25V, f = 1MHz, VGS = 0 1710 250 110 pF pF pF td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 50V, ID = 12.5A RG = 4.7Ω VGS = 5V (see Figure 13) 20 40 58 20 ns ns ns ns Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD = 80V, ID = 25A, VGS = 5V, RG = 4.7Ω (see Figure 14) 38 8.5 21 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 4/13 Min. 52 nC nC nC STD25NF10L Electrical characteristics Table 5. Symbol Source drain diode Parameter ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD trr Qrr IRRM Test conditions Min. Typ. ISD = 25A, VGS = 0 Reverse recovery time ISD = 25A, di/dt = 100A/µs, Reverse recovery charge VDD = 50V, Tj = 150°C Reverse recovery current (see Figure 15) 88 317 7.2 Max. Unit 25 100 A A 1.5 V ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5/13 Electrical characteristics STD25NF10L 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/13 STD25NF10L Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 12. Normalized breakdown voltage vs temperature 7/13 Test circuit 3 STD25NF10L Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/13 Figure 18. Switching time waveform STD25NF10L 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/13 Package mechanical data STD25NF10L DPAK MECHANICAL DATA mm. inch DIM. MAX. MIN. A A1 A2 B b4 MIN. 2.2 0.9 0.03 0.64 5.2 TYP 2.4 1.1 0.23 0.9 5.4 0.086 0.035 0.001 0.025 0.204 0.094 0.043 0.009 0.035 0.212 C C2 D D1 E E1 e e1 H L (L1) L2 L4 R V2 0.45 0.48 6 0.6 0.6 6.2 0.017 0.019 0.236 0.023 0.023 0.244 6.6 0.252 5.1 6.4 0.173 0.368 0.039 2.8 0.8 0.181 0.397 0.110 0.031 1 0.023 0.2 0° 0.260 0.185 0.090 4.6 10.1 0.6 MAX. 0.200 4.7 2.28 4.4 9.35 1 TYP. 0.039 0.008 8° 0° 8° 0068772-F 10/13 STD25NF10L 5 Packing mechanical data Packing mechanical data DPAK FOOTPRINT All dimensions are in millimeters TAPE AND REEL SHIPMENT REEL MECHANICAL DATA DIM. mm MIN. A B 1.5 C 12.8 D 20.2 G 16.4 N 50 T TAPE MECHANICAL DATA DIM. mm inch MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 D 1.5 D1 1.5 E 1.65 MIN. 12.1 0.476 1.6 0.059 0.063 1.85 0.065 0.073 7.4 7.6 0.291 0.299 2.55 2.75 0.100 0.108 0.153 0.161 P0 3.9 4.1 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 40 15.7 MAX. 330 12.992 13.2 0.504 0.520 18.4 0.645 0.724 0.059 0.795 1.968 22.4 0.881 BASE QTY BULK QTY 2500 2500 0.059 F R MIN. MAX. K0 W inch MAX. 1.574 16.3 0.618 0.641 11/13 Revision history 6 STD25NF10L Revision history Table 6. 12/13 Revision history Date Revision Changes 21-Jun-2004 1 Preliminary version 03-Jun-2006 2 New template, no content change STD25NF10L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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