STP40NF10 N-channel 100V - 0.025Ω - 50A TO-220 Low gate charge STripFET™ II Power MOSFET General features Type VDSS RDS(on) ID STP40NF10 100V <0.028Ω 50A ■ Exceptional dv/dt capability ■ Low gate charge at 100°C 3 ■ Application oriented characterization ■ 100% avalanche tested 1 2 TO-220 Description This MOSFET is the latest development of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STP40NF10 P40NF10 TO-220 Tube January 2007 Rev 3 1/12 www.st.com 12 Contents STP40NF10 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STP40NF10 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (vgs = 0) 100 V VGS Gate- source voltage ±20 V Drain current (continuous) at TC = 25°C 50 A Drain current (continuous) at TC = 100°C 35 A Drain current (pulsed) 200 A Total dissipation at TC = 25°C 150 W Derating factor 1 W/°C Peak diode recovery voltage slope 27 V/ns Single pulse avalanche energy 385 mj – 55 to 175 °C 1 °C/W ID (1) ID IDM (2) PTOT dv/dt(3) EAS (4) Tstg Tj Storage temperature Max. operating junction temperature 1. Limited by wire bonding 2. Pulse width limited by safe operating area 3. ISD ≤50A, di/dt ≤600A/µs, VDD ≤V(BR)DSS, Tj ≤TJMAX. 4. Starting Tj= 25°C, ID= 50A, VDD=25V Table 2. Thermal data Rthj-case Thermal resistance junction-case Max Rthj-a Thermal resistance junction-ambient Max 62.5 °C/W Tl Maximum lead temperature for soldering purpose 300 °C 3/12 Electrical characteristics 2 STP40NF10 Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter V(BR)DSS Drain-source Breakdown voltage Test conditions ID = 250 µA, VGS = 0 100 Unit V µA VDS=Max rating,TC=125°C 10 µA ±100 nA 3 4 V 0.025 0.028 Ω IGSS Gate-body leakage current (VDS = 0) VGS = ±20V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 25A gfs (1) Max. 1 Zero gate voltage Drain current (VGS = 0) Symbol Typ. VDS = Max rating IDSS Table 4. Min. 2 Dynamic Parameter Forward transconductance Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions Min. VDS = 15V, ID=28A VDS = 25V, f = 1 MHz, VGS = 0 Typ. Unit 22 S 2180 pF 298 pF 83.7 pF 57.6 VDD = 80V, ID = 50A, VGS = 10V (see Figure 14) Max. 76 nC 13.3 nC 17.5 nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5. Table 5. Symbol 4/12 Switching times Parameter Test conditions Min. Typ. Max. Unit td(on) tr Turn-on delay time Rise time VDD = 50V, ID = 25A RG = 4.7Ω VGS = 10V (see Figure 13) 21 46 ns ns td(off) tf Turn-off-delay time Fall time VDD = 27V, ID = 40A, RG = 4.7Ω, VGS = 10V (see Figure 13) 54 13 ns ns STP40NF10 Electrical characteristics Table 6. Symbol ISD Source drain diode Parameter Test conditions Min. Typ. Max Unit Source-drain current 80 A ISDM (1) Source-drain current (pulsed) 320 A VSD (2) Forward on voltage ISD = 50A, VGS = 0 1.5 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 50A, VDD = 25V di/dt = 100A/µs, Tj = 150°C (see Figure 15) trr Qrr IRRM 80 250 6.4 ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 5/12 Electrical characteristics STP40NF10 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/12 STP40NF10 Electrical characteristics Figure 7. Gate charge vs. gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs. temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs. temperature Figure 12. Normalized breakdown voltage vs. tj 7/12 Test circuit 3 STP40NF10 Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/12 Figure 18. Switching time waveform STP40NF10 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com 9/12 Package mechanical data STP40NF10 TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 10/12 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP40NF10 5 Revision history Revision history Table 7. Revision history Date Revision Changes 16-Dec-2004 1 First version. 17-Aug-2006 2 The document has been reformatted. 31-Jan-2007 3 Typo mistake on Table 1. 11/12 STP40NF10 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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