TI SN74ALS1035D

SN54ALS1035, SN74ALS1035
HEX NONINVERTING BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS243B – APRIL 1982 – REVISED AUGUST 2001
D
SN54ALS1035 . . . J OR W PACKAGE
SN74ALS1035 . . . D OR N PACKAGE
(TOP VIEW)
Noninverting Buffers With
Open-Collector Outputs
description
1A
1Y
2A
2Y
3A
3Y
GND
These devices contain six independent
noninverting buffers. They perform the Boolean
function Y = A. The open-collector outputs require
pullup resistors to perform correctly. They can be
connected to other open-collector outputs to
implement active-low wired-OR or active-high
wired-AND functions. Open-collector devices are
often used to generate higher VOH levels.
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
6Y
NC
5A
NC
5Y
3Y
GND
NC
4Y
4A
2A
NC
2Y
NC
3A
6A
1Y
1A
NC
VCC
SN54ALS1035 . . . FK PACKAGE
(TOP VIEW)
NC – No internal connection
ORDERING INFORMATION
0°C to 70°C
–55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
Tube
SN7ALS1035D
Tape and reel
SN7ALS1035DR
PDIP – N
Tube
SN74ALS1035N
SN74ALS1035N
CDIP – J
Tube
SNJ54ALS1035J
SNJ54ALS1035J
CFP – W
Tube
SNJ54ALS1035W
SNJ54ALS1035W
LCCC - FK
Tube
SNJ54ALS1035FK
SOIC – D
ALS1035
SNJ54ALS1035FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each buffer)
INPUT
A
OUTPUT
Y
H
H
L
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
SN54ALS1035, SN74ALS1035
HEX NONINVERTING BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS243B – APRIL 1982 – REVISED AUGUST 2001
logic diagram (positive logic)
1A
2A
3A
4A
5A
6A
1
2
3
4
5
6
9
8
11
10
13
12
1Y
2Y
3Y
4Y
5Y
6Y
Pin numbers shown are for the D, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
1. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
SN54ALS1035
2
SN74ALS1035
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
VOH
Low-level input voltage
0.7
0.8
High-level output voltage
5.5
5.5
V
IOL
TA
Low-level output current
12
24
mA
70
°C
High-level input voltage
2
Operating free-air temperature
– 55
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2
125
0
V
V
V
SN54ALS1035, SN74ALS1035
HEX NONINVERTING BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS243B – APRIL 1982 – REVISED AUGUST 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
SN54ALS1035
TYP†
MAX
TEST CONDITIONS
VCC = 4.5 V,
VOL
VCC = 4
4.5
5V
IOH
II
VCC = 4.5 V,
VCC = 5.5 V,
IIH
IIL
VCC = 5.5 V,
VCC = 5.5 V,
ICCH
ICCL
VCC = 5.5 V,
VCC = 5.5 V,
MIN
II = –18 mA
IOL = 12 mA
SN74ALS1035
TYP†
MAX
MIN
–1.5
0.25
IOL = 24 mA
VOH = 5.5 V
VI = 7 V
VI = 2.7 V
–1.5
0.4
0.25
0.4
0.35
0.5
UNIT
V
V
0.1
0.1
mA
0.1
0.1
mA
20
20
µA
VI = 0.4 V
VI = 4.5 V
– 0.1
mA
3
– 0.1
6
3
6
mA
VI = 0
8
14
8
14
mA
† All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 680 Ω,
TA = MIN to MAX‡
SN54ALS1035
tPLH
tPHL
A
Y
UNIT
SN74ALS1035
MIN
MAX
MIN
MAX
5
35
5
30
2
14
2
12
ns
‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
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3
SN54ALS1035, SN74ALS1035
HEX NONINVERTING BUFFERS
WITH OPEN-COLLECTOR OUTPUTS
SDAS243B – APRIL 1982 – REVISED AUGUST 2001
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7V
RL = R1 = R2
VCC
S1
RL
R1
Test
Point
From Output
Under Test
CL
(see Note A)
From Output
Under Test
RL
Test
Point
From Output
Under Test
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
LOAD CIRCUIT
FOR OPEN-COLLECTOR OUTPUTS
3.5 V
Timing
Input
Test
Point
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
R2
1.3 V
1.3 V
0.3 V
0.3 V
tsu
Data
Input
tw
th
3.5 V
1.3 V
3.5 V
Low-Level
Pulse
1.3 V
0.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
tPZL
Waveform 1
S1 Closed
(see Note B)
tPLZ
[3.5 V
3.5 V
Input
tPHZ
VOL
0.3 V
0.3 V
[0 V
1.3 V
0.3 V
tPHL
VOH
In-Phase
Output
1.3 V
1.3 V
VOL
tPLH
tPHL
VOH
1.3 V
1.3 V
tPLH
1.3 V
tPZH
Waveform 2
S1 Open
(see Note B)
1.3 V
VOH
Out-of-Phase
Output
(see Note C)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
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Copyright  2001, Texas Instruments Incorporated