TI TLC352CD

TLC352
LinCMOS DUAL DIFFERENTIAL COMPARATOR
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
D
D
D
D
D
D
D
D
D
Single- or Dual-Supply Operation
Wide Range of Supply Voltages
1.5 V to 18 V
Very Low Supply Current Drain
150 µA Typ at 5 V
65 µA Typ at 1.4 V
Built-In ESD Protection
High Input Impedance . . . 1012 Ω Typ
Extremely Low Input Bias Current 5 pA Typ
Ultrastable Low Input Offset Voltage
Input Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/ Month,
Including the First 30 Days
Common-Mode Input Voltage Range
Includes Ground
Outputs Compatible With TTL, MOS, and
CMOS
Pin-Compatible With LM393
TLC352C, TLC352I . . . D OR P PACKAGE
TLC352M . . . JG PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
GND
8
2
7
3
6
4
5
VDD
2OUT
2IN–
2IN+
TLC352M . . . FK PACKAGE
(TOP VIEW)
NC
1IN–
NC
1IN+
NC
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC
2OUT
NC
2IN–
NC
NC
GND
NC
2IN+
NC
description
This device is fabricated using LinCMOS
technology and consists of two independent
voltage comparators, each designed to operate
from a single power supply. Operation from dual
supplies is also possible if the difference between
the two supplies is 1.4 V to 18 V. Each device
features extremely high input impedance
(typically greater than 1012 Ω), which allows direct
interface to high-impedance sources. The output
are n-channel open-drain configurations and can
be connected to achieve positive-logic wired-AND
relationships. The capability of the TLC352 to
operate from 1.4-V supply makes this device ideal
for low-voltage battery applications.
1
NC
1OUT
NC
V DD
NC
D
D
NC — No Internal connection
symbol (each comparator)
IN+
OUT
IN–
The TLC352 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V
ESD rating tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling this
device as exposure to ESD may result in degradation of the device parametric performance.
The TLC352C is characterized for operation from 0°C to 70°C. The TLC352I is characterized for operation over
the industrial temperature range of – 40°C to 85°C. The TLC352M is characterized for operation over the full
military temperature range – 55°C to 125°C.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright  1990, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLC352
LinCMOS DUAL DIFFERENTIAL COMPARATOR
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
AVAILABLE OPTIONS
TA
VIO max
AT 25°C
0°C to 70°C
PACKAGE
SMALL-OUTLINE
(D)
CHIP-CARRIER
(FK)
CERAMIC DIP
(JG)
PLASTIC DIP
(P)
5 mV
TLC352CD
—
—
TLC352CP
– 40°C to 85°C
5 mV
TLC352ID
—
—
TLC352IP
– 55°C to 125°C
5 mV
—
TLC352MFK
TLC352MJG
—
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC352 CDR).
equivalent schematic (each comparator)
Common to All Channels
VDD
OUT
GND
IN+
2
POST OFFICE BOX 655303
IN–
• DALLAS, TEXAS 75265
TLC352
LinCMOS DUAL DIFFERENTIAL COMPARATOR
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V
Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA TLC352C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLC352I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
TLC352M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to the network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE TA
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
FK
JG
P
500 mW
500 mW
500 mW
500 mW
5.8 mW/°C
11.0 mW/°C
8.4 mW/°C
N/A
64°C
104°C
90°C
N/A
464 mW
500 mW
500 mW
500 mW
377 mW
500 mW
500 mW
500 mW
N/A
275 mW
210 mW
N/A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
MIN
1.4
16
0
3.5
0
0
VDD = 5 V
VDD = 10 V
Common mode input voltage,
Common-mode
voltage VIC
Operating free-air temperature, TA
TLC352M
MAX
MIN
MAX
1.4
16
1.4
16
0
3.5
0
3.5
8.5
0
8.5
0
8.5
70
– 40
85
– 55
125
UNIT
V
V
°C
electrical characteristics at specified free-air temperature, VDD = 1.4 V (unless otherwise noted)
PARAMETER
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VIO
Input offset voltage
IIO
Input offset current
IIB
Input bias current
VICR
Common-mode input voltage
range
VOL
Low level output voltage
Low-level
IOL
Low-level output current
IDD
Supply current (two comparators)
TEST CONDITIONS
VIC = VICR min
min,
See Note 4
TA†
TLC352C
MIN
25°C
TYP
2
Full range
MAX
VID = 0
0.5
5V
V,
No load
25°C
Full range
2
5
1.6
65
10
200
20
200
65
100
200
200
200
1
150
nA
nA
V
200
1.6
mV
pA
0 to
0.2
100
UNIT
pA
5
2
1
150
5
1
0 to
0.2
200
MAX
10
1
200
1
TYP
2
5
0.6
100
MIN
1
0 to
0.2
Full range
25°C
MAX
0.3
25°C
TLC352M
TYP
7
5
MAX
VOL = 0.3 V
5
1
25°C
VID = – 0.5 V,
MIN
6.5
25°C
Full range
TLC352I
MAX
1.6
65
mV
mA
150
200
µA
† All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC352C, – 40°C to 85°C for TLC352I, – 55°C to 125°C
for TLC352M. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kΩ resistor between the output and VDD. They
can be verified by applying the limit value to the input and checking for the appropriate output state.
Template Release Date: 7–11–94
Supply voltage, VDD
TLC352I
MAX
TLC352
LinCMOSTM DUAL DIFFERENTIAL COMPARATOR
TLC352C
MIN
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
4
recommended operating conditions
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
VIO
Input offset voltage
IIO
Input offset current
IIB
VICR
TA†
TEST CONDITIONS
VIC = VICR min
min,
See Note 5
TLC352C
MIN
25°C
TYP
TLC352I
MAX
1
Full range
VOL
Low-level output
voltage
VID = 1 V
V,
IOL = 4 mA
IOL
Low-level output
current
VID = – 1 V,
VOL = 1.5 V
IDD
Supply
y current
(two comparators)
VID = 1 V
V,
No load
1
1
5
5
2
25°C
0 to
VDD – 1
Full range
0 to
VDD – 1.5
0 to
VDD – 1.5
0 to
VDD – 1.5
25°C
0.1
25°C
150
Full range
25°C
25°C
0.1
1
150
700
6
16
0.15
Full range
0.1
150
700
6
0.3
16
0.15
0.4
400
700
6
16
0.3
nA
nA
1
400
nA
V
1
400
mV
pA
20
0 to
VDD – 1
UNIT
pA
10
0 to
VDD – 1
Full range
5
10
1
0.6
MAX
0.15
0.4
µA
mV
mA
0.3
0.4
mA
† All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC352C, – 40°C to 85°C for TLC352I, – 55°C to 125°C
for TLC352M. IMPORTANT: See Parameter Measurement Information.
NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and VDD. They
can be verified by applying the limit value to the input and checking for the appropriate output state.
switching characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC352C, TLC352I
TLC352M
MIN
Response time
RL connected to 5 V through 5.1 kΩ,,
CL = 15 pF‡,
See Note 6
TYP
100-mV input step with 5-mV overdrive
650
TTL-level input step
200
‡ CL includes probe and jig capacitance.
NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
UNIT
MAX
ns
5
TLC352
LinCMOSTM DUAL DIFFERENTIAL COMPARATOR
VOH = 5 V
VOH = 15 V
TYP
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VID = 1 V
5
MIN
1
5
MAX
High-level
g
output
current
1
0.3
25°C
IOH
MAX
7
1
MAX
Common-mode
input voltage range
5
TYP
6.5
25°C
Input bias current
MIN
TLC352M
TLC352
LinCMOS DUAL DIFFERENTIAL COMPARATOR
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC352 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide greater
accuracy.
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes state.
5V
1V
5.1 kΩ
5.1 kΩ
+
+
–
–
Applied VIO
Limit
VO
Applied VIO
Limit
VO
–4V
(a) VIO WITH VIC = 0
(b) VIO WITH VIC = 4 V
Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLC352
LinCMOS DUAL DIFFERENTIAL COMPARATOR
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
PARAMETER INFORMATION
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
R5
1.8 kΩ, 1%
VDD
U1b
1/4 TLC274CN
Buffer
+
C2
1 µF
U1c
1/4 TLC274CN
–
DUT
–
R1
240 kΩ
–
C1
0.1 µF
R6
5.1 kΩ
C3 0.68 µF
+
R3
100 kΩ
R7
1MΩ
R4
47 kΩ
Integrator
R8
1.8 kΩ, 1%
U1a
1/4 TLC274CN
Triangle
Generator
VIO
(X100)
+
R10
100 Ω, 1%
C4
0.1 µF
R9
10 kΩ, 1%
R2
10 kΩ
Figure 2. Circuit for Input Offset Voltage Measurement
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TLC352
LinCMOS DUAL DIFFERENTIAL COMPARATOR
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading
edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The
offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change
state.
VDD
1 µF
5.1 kΩ
Pulse Generator
DUT
50 Ω
CL
(see Note A)
1V
Input
Offset Voltage
Compensation
Adjustment
10 Ω
10 Turn
1 kΩ
0.1 mF
–1V
TEST CIRCUIT
Overdrive
Overdrive
Input
Input
100 mV
100 mV
90%
90%
50 %
Low-to-HighLevel Output
10%
High-to-LowLevel Output
tr
50%
10%
tf
tPLH
tPHL
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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Copyright  1998, Texas Instruments Incorporated