PROCESS CP316V Small Signal Transistors NPN - High Voltage Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 20 x 20 MILS Die Thickness 7.1 MILS Base Bonding Pad Area 4.0 x 4.0 MILS Emitter Bonding Pad Area 4.7 x 4.7 MILS Top Side Metalization Al - 30,000Å Back Side Metalization Au - 18,000Å GEOMETRY GROSS DIE PER 5 INCH WAFER 57,735 PRINCIPAL DEVICE TYPES CMPT5551 CXT5551 CZT5551 2N5551 R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m PROCESS CP316V Typical Electrical Characteristics R2 (22-March 2010) w w w. c e n t r a l s e m i . c o m