SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 D D D D D D D SN54LV393A . . . J OR W PACKAGE SN74LV393A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 2-V to 5.5-V VCC Operation Max tpd of 10 ns at 5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down-Mode Operation Dual 4-Bit Binary Counters With Individual Clocks Direct Clear for Each 4-Bit Counter Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1CLK 1CLR 1QA 1QB 1QC 1QD GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLK 2CLR 2QA 2QB 2QC 2QD SN54LV393A . . . FK PACKAGE (TOP VIEW) 1CLR 1CLK NC VCC 2CLK D D D 3 1QA NC 1QB NC 1QC description/ordering information 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2CLR NC 2QA NC 2QB 1QD GND NC 2QD 2QC The ’LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2-V to 5.5-V VCC operation. 4 NC – No internal connection ORDERING INFORMATION SN74LV393AD Reel of 2500 SN74LV393ADR SOP – NS Reel of 2000 SN74LV393ANSR 74LV393A SSOP – DB Reel of 2000 SN74LV393ADBR LV393A Tube of 90 SN74LV393APW Reel of 2000 SN74LV393APWR TSSOP – PW –55°C to 125°C TOP-SIDE MARKING Tube of 50 SOIC – D –40°C 40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA LV393A LV393A Reel of 250 SN74LV393APWT TVSOP – DGV Reel of 2000 SN74LV393ADGVR LV393A CDIP – J Tube of 25 SNJ54LV393AJ SNJ54LV393AJ CFP – W Tube of 150 SNJ54LV393AW SNJ54LV393AW LCCC – FK Tube of 55 SNJ54LV393AFK SNJ54LV393AFK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 description/ordering informaton (continued) These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK) input. These devices change state on the negative-going transition of the CLK pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ’LV393A devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE INPUTS FUNCTION CLK CLR ↑ L No change ↓ L Advance to next stage X H All outputs L logic diagram, each counter (positive logic) R CLR CLK Q QA Q QB Q QC Q QD T R T R T R T 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 timing diagram CLK CLR QA QB Outputs QC QD Count Up Clear absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range applied in high or low state, VO (see Notes 1 and 2) . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range applied in power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 recommended operating conditions (see Note 4) SN54LV393A VCC VIH MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V High level input voltage High-level VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7 VI VO Input voltage 0 Output voltage 0 ∆t/∆v UNIT V V 0.5 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 0 VCC –50 VCC = 2 V VCC = 2.3 V to 2.7 V VCC × 0.3 5.5 0 VCC –50 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V V V V µA –2 –6 –6 –12 –12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 12 200 200 100 100 20 20 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Input transition rise or fall rate 5.5 VCC × 0.7 VCC × 0.7 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V Low level output current Low-level 2 VCC × 0.7 VCC × 0.7 Low level input voltage Low-level IOL MAX 1.5 VCC = 2 V VCC = 2.3 V to 2.7 V High level output current High-level MIN 1.5 VIL IOH SN74LV393A MIN mA µA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS IOH = –50 µA IOH = –2 mA 2.3 V IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND VI = VCC or GND, Ioff Ci VI or VO = 0 to 5.5 V VI = VCC or GND MIN 2 V to 5.5 V IOH = –6 mA IOH = –12 mA II ICC SN54LV393A VCC IO = 0 TYP VCC–0.1 2 3V 2.48 4.5 V 3.8 MIN TYP MAX VCC–0.1 2 UNIT V 2.48 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V V 0.55 0.55 0 to 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0 5 5 µA 3.3 V 1.8 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN74LV393A MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1.8 pF SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time SN54LV393A MIN MAX SN74LV393A MIN CLK high or low 5 5 5 CLR high 5 5 5 CLR inactive before CLK↓ 6 6 6 MAX UNIT ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time SN54LV393A MIN MAX SN74LV393A MIN CLK high or low 5 5 5 CLR high 5 5 5 CLR inactive before CLK↓ 5 5 5 MAX UNIT ns ns timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration tsu Setup time FROM (INPUT) TO (OUTPUT) fmax tPHL tpd d tPHL CLK CLR CLK CLR MAX SN74LV393A MIN 5 5 5 CLR high 5 5 5 CLR inactive before CLK↓ 4 4 4 free-air TA = 25°C TYP MAX SN54LV393A CL = 15 pF 50* 90* 40* 40 CL = 50 pF 30 70 25 25 MAX MIN ns MAX 17.7* 1* 20.5* 1 20.5 8.5* 20.3* 1* 23.5* 1 23.5 10* 22.5* 1* 26* 1 26 QD 11.1* 24.2* 1* 28* 1 28 Qn 6.7* 14.8* 1* 17* 1 17 QA 9.3 21.3 1 24.5 1 24.5 10.9 23.9 1 27.5 1 27.5 12.3 26.1 1 30 1 30 QD 13.4 27.8 1 32 1 32 Qn 9.1 17.4 1 20 1 20 QB CL = 15 pF QB QC CL = 50 pF range, UNIT MHz 7.1* QC UNIT ns SN74LV393A MIN MIN MAX temperature LOAD CAPACITANCE QA tpd d MIN CLK high or low switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER SN54LV393A ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 switching characteristics over recommended operation VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d CLK free-air TA = 25°C TYP MAX temperature SN54LV393A SN74LV393A LOAD CAPACITANCE MIN CL = 15 pF 75* 130* 65* 65 CL = 50 pF 45 105 35 35 MIN MAX MIN MAX 5.1* 13.2* 1* 15.5* 1 15.5 QB 6* 15.8* 1* 18.5* 1 18.5 7* 18* 1* 21* 1 21 QD 7.7* 19.7* 1* 23* 1 23 Qn 5.1* 12.3* 1* 14.5* 1 14.5 QA 6.7 16.7 1 19 1 19 7.8 19.3 1 22 1 22 8.7 21.5 1 24.5 1 24.5 9.5 23.2 1 26.5 1 26.5 tPHL 6.8 CLR Qn * On products compliant to MIL-PRF-38535, this parameter is not production tested. 15.8 1 18 1 18 tPHL CLR tpd d CLK CL = 15 pF QB CL = 50 pF QC QD switching characteristics over recommended operating VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d CLK tPHL CLR tpd d CLK tPHL CLR LOAD CAPACITANCE free-air TA = 25°C MIN TYP MAX temperature SN54LV393A MIN MAX SN74LV393A MIN CL = 15 pF 125* 185* 105* 105 CL = 50 pF 85 150 75 75 MAX 3.7* 8.5* 1* 10* 1 10 QB 4.3* 9.8* 1* 11.5* 1 11.5 4.9* 11.2* 1* 13* 1 13 QD 5.3* 12.5* 1* 14.5* 1 14.5 Qn 3.9* 8.1* 1* 9.5* 1 9.5 QA 4.9 10.5 1 12 1 12 QB 5.6 11.8 1 13.5 1 13.5 6.2 13.2 1 15 1 15 QD 6.6 14.5 1 16.5 1 16.5 Qn 5.2 10.1 1 11.5 1 11.5 CL = 15 pF CL = 50 pF QC ns ns range, UNIT MHz QA QC UNIT MHz QA QC range, ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV393A PARAMETER MIN MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.3 0.8 V Quiet output, minimum dynamic VOL –0.2 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 2.8 High-level dynamic input voltage V 2.31 VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. POST OFFICE BOX 655303 V 0.99 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 TYP • DALLAS, TEXAS 75265 V SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 operating characteristics, TA = 25°C PARAMETER Cpd capacitance Power dissipation dissi ation ca acitance TEST CONDITIONS CL = 50 pF F, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz VCC 3.3 V TYP 5V 17.3 15.2 UNIT pF F 7 SN54LV393A, SN74LV393A DUAL 4-BIT BINARY COUNTERS SCLS457B – FEBRUARY 2001 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output 0V VOH 50% VCC VOL VOH 50% VCC VOL 50% VCC 50% VCC 0V tPLZ tPZL Output Waveform 1 S1 at VCC (see Note B) ≈VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ tPZH tPLH 50% VCC VCC Output Control 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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