TI SN74LV4040AD

SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
D
D
D
D
D
D
D
QL
QF
QE
QG
QD
QC
QB
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QK
QJ
QH
QI
CLR
CLK
QA
SN54LV4040A . . . FK PACKAGE
(TOP VIEW)
QE
QG
NC
QD
QC
NC
VCC
QK
D
SN54LV4040A . . . J OR W PACKAGE
SN74LV4040A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
QF
QL
D
EPIC  (Enhanced-Performance Implanted
CMOS) Process
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Ceramic (J) DIPs
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
QJ
QH
NC
QI
CLR
QB
GND
NC
QA
CLK
D
description
NC – No internal connection
The ’LV4040A devices are 12-bit asynchronous
binary counters with the outputs of all stages
available externally. A high level at the clear (CLR)
input asynchronously clears the counter and
resets all outputs low. The count is advanced on
a high-to-low transition at the clock (CLK) input.
Applications include time-delay circuits, counter
controls, and frequency-dividing circuits.
The SN54LV4040A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV4040A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
logic symbol†
RCTR12
9
0
7
6
5
CLR
11
3
CT=0
2
CLK
CT
10
4
13
12
14
15
1
11
QA
QB
QC
QD
QE
QF
QG
QH
QI
QJ
QK
QL
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
CLR
11
R
CLK
10
R
T
R
R
T
T
4
QF
QG
T
T
T
6
5
3
QA
QB
QC
QD
QE
R
R
T
13
12
QH
R
T
POST OFFICE BOX 655303
R
T
14
QI
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
R
7
T
2
R
9
R
T
R
• DALLAS, TEXAS 75265
QJ
T
15
QK
1
QL
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High level input voltage
High-level
Low level input voltage
Low-level
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
SN54LV4040A
SN74LV4040A
MIN
MAX
MIN
MAX
2
5.5
2
5.5
1.5
0
Output voltage
0
Low level output current
Low-level
Input transition rise or fall rate
VCC = 2 V
VCC = 2.3 V to 2.7 V
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
VCC × 0.3
5.5
V
VCC
–50
µA
VCC
–50
0
0
–2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
VCC × 0.7
0.5
Input voltage
High level output current
High-level
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
1.5
VCC × 0.7
VCC × 0.7
VCC = 2 V
VCC = 2.3 V to 2.7 V
UNIT
V
V
–2
–6
–6
–12
–12
VCC = 2 V
VCC = 2.3 V to 2.7 V
50
50
2
2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
6
6
12
mA
µA
mA
12
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
0
200
0
200
0
100
0
100
VCC = 4.5 V to 5.5 V
0
20
0
20
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
SN54LV4040A
TEST CONDITIONS
VCC
IOH = –50 µA
IOH = –2 mA
2 V to 5.5 V
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
IOL = 2 mA
IOL = 6 mA
IOL = 12 mA
II
ICC
VI = VCC or GND
VI = VCC or GND,
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
MIN
IO = 0
TYP
SN74LV4040A
MAX
MIN
2.3 V
VCC–0.1
2
VCC–0.1
2
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
UNIT
V
3.8
2 V to 5.5 V
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
0.55
0.55
5.5 V
±1
±1
µA
5.5 V
20
20
µA
0V
5
5
µA
3.3 V
1.9
1.9
5V
1.8
1.8
V
pF
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
CLK high or low
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
7
7
7
CLR high
6.5
6.5
6.5
CLR inactive before CLK↓
6.5
6.5
6.5
MAX
UNIT
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
CLK high or low
5
5
5
CLR high
5
5
5
CLR inactive before CLK↓
5
5
5
MAX
UNIT
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
MIN
MAX
SN74LV4040A
MIN
CLK high or low
5
5
5
CLR high
5
5
5
CLR inactive before CLK↓
5
5
5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
SN54LV4040A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
ns
ns
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH*
tPHL*
LOAD
CAPACITANCE
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
50
115
40
40
CL = 50 pF
40
95
35
35
MAX
UNIT
MHz
8.7
19.4
1
23
1
23
8.7
19.4
1
23
1
23
9.3
19.9
1
24
1
24
10.5
24.1
1
28
1
28
10.5
24.1
1
28
1
28
CL = 50 pF
11.7
24.5
1
28
1
28
ns
CL = 50 pF
1.7
5.9
7
ns
QA
CL = 15 pF
CLR
Any Q
CL = 15 pF
CLK
QA
CL = 50 pF
tPHL
CLR
Any Q
∆tpd
Qn
Qn+1
tPHL
TA = 25°C
TYP
MAX
CL = 15 pF*
CLK
tPHL*
tPLH
MIN
7
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH*
tPHL*
LOAD
CAPACITANCE
MIN
TA = 25°C
TYP
MAX
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
CL = 15 pF*
75
160
75
75
CL = 50 pF
55
130
50
50
MAX
UNIT
MHz
6.1
11.9
1
14
1
14
6.1
11.9
1
14
1
14
7.1
12.8
1
15
1
15
7.5
15.4
1
17.5
1
17.5
7.5
15.4
1
17.5
1
17.5
9
16.3
1
18.5
1
18.5
ns
∆tpd
Qn
CL = 50 pF
1.2
Qn+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
4.4
5
ns
tPHL*
tPLH
tPHL
tPHL
CLK
QA
CL = 15 pF
CLR
Any Q
CL = 15 pF
CLK
QA
CL = 50 pF
CLR
Any Q
CL = 50 pF
5
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH*
tPHL*
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
MAX
SN54LV4040A
MIN
MAX
SN74LV4040A
MIN
CL = 15 pF*
150
235
125
125
CL = 50 pF
95
185
80
80
MAX
UNIT
MHz
4.2
7.3
1
8.5
1
8.5
4.2
7.3
1
8.5
1
8.5
5.3
8.6
1
10
1
10
5.3
9.3
1
10.5
1
10.5
5.3
9.3
1
10.5
1
10.5
6.8
10.6
1
12
1
12
ns
∆tpd
Qn
CL = 50 pF
0.8
Qn+1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
3.1
3.5
ns
tPHL*
tPLH
tPHL
tPHL
CLK
QA
CL = 15 pF
CLR
Any Q
CL = 15 pF
CLK
QA
CL = 50 pF
CLR
Any Q
CL = 50 pF
3.5
ns
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV4040A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.5
0.8
V
Quiet output, minimum dynamic VOL
–0.5
–0.8
V
VIH(D)
VIL(D)
High-level dynamic input voltage
2.31
V
Low-level dynamic input voltage
0.99
V
VCC
3.3 V
TYP
UNIT
5V
13.1
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
Cpd
6
Power dissipation
dissi ation ca
capacitance
acitance
TEST CONDITIONS
CL = 50 pF
F,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 10 MHz
11.9
pF
F
SN54LV4040A, SN74LV4040A
12-BIT ASYNCHRONOUS BINARY COUNTERS
SCES226A – APRIL 1999 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
50% VCC
Input
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  1999, Texas Instruments Incorporated