TI THS4508RGTT

THS4508
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Differential Architecture
Common-Mode Input Range Includes the
Negative Rail
Minimum Gain of 2 V/V (6 dB)
Bandwidth: 2 GHz
Slew Rate: 6400 V/µs
0.1% Settling Time: 2 ns
HD2: –72 dBc at 100 MHz
HD3: –79 dBc at 100 MHz
OIP2: 78 dBm at 70 MHz
OIP3: 42 dBm at 70 MHz
Input Voltage Noise: 2.3 nV/√Hz (f > 10 MHz)
Noise Figure: 19.2 dB (G = 10 dB)
Output Common-Mode Control
5-V Power Supply Current: 39.2 mA
Power-Down Capability: 0.65 mA
APPLICATIONS
•
•
•
•
•
5-V Data-Acquisition Systems
High Linearity ADC Amplifier
Wireless Communication
Medical Imaging
Test and Measurement
To allow for dc coupling to ADCs, its unique output
common-mode control circuit maintains the output
common-mode voltage within 5-mV offset (typical)
from the set voltage, when set within 0.5 V of
mid-supply. The common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source.
The THS4508 is a high-performance amplifier that
has been optimized for use in high performance, 5-V
single supply data acquisition systems. The output
has been optimized for best performance with its
common-mode voltages set to mid supply, and the
input has been optimized for best performance with
its common-mode voltage set to 0.7 V. High
performance at a low power-supply voltage makes for
high-performance single-supply 5-V data-acquisition
systems with a minimum parts count. The combined
performance of the THS4508 in a gain of 10-dB
driving the ADS5500 ADC, sampling at 125 MSPS, is
82-dBc SFDR, and 68.3-dBc SNR with a –1-dBFS
signal at 70 MHz.
The THS4508 is offered in a Quad 16-pin leadless
QFN package (RGT), and is characterized for
operation over the full industrial temperature range
from –40°C to 85°C.
RS = 75 W
VSignal
VIN
348 W
175 W
130 W
VS+ = 5 V
RO
DESCRIPTION
The THS4508 is a wideband, fully-differential
operational amplifier designed for single-supply 5-V
data-acquisition systems. It has very low noise at 2.3
nV/√Hz, and extremely low harmonic distortion of –72
dBc HD2 and –79 dBc HD3 at 100 MHz with 2 VPP,
G = 10 dB, and 1-kΩ load. Slew rate is very high at
6400 Vµs and with settling time of 2 ns to 0.1% (2 V
step) it is ideal for pulsed applications. It is designed
for minimum gain of 6 dB, but is optimized for gain of
10 dB.
VOUTTHS4508
175 W
75 W
130 W
VS-
RO
VCM
VOUT+
348 W
Figure 1. Video Buffer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
THS4508
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VSS
Supply voltage
VS– to VS+
VI
Input voltage
VID
Differential input voltage
IO
Output current
5.5 V
±VS
4V
200 mA
Continuous power dissipation
See Dissipation Rating Table
temperature (2)
TJ
Maximum junction
TJ
Maximum junction temperature, continuous operation, long term reliability (3)
150°C
TA
Operating free-air temperature range
–40°C to 85°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings
(1)
(2)
(3)
125°C
300°C
HBM
2000
CDM
1500
MM
100
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
The maximum junction temperature for continuous operation is limited by the package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device. The THS4508 incorporates a (QFN) exposed thermal pad on the underside
of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so
may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief
SLMA002 and SLMA004 for more information about utilizing the QFN thermally enhanced package.
DISSIPATION RATINGS TABLE PER PACKAGE
(1)
2
PACKAGE (1)
θJC
θJA
RGT (16)
2.4°C/W
39.5°C/W
POWER RATING
TA ≤ 25°C
TA = 85°C
2.3 W
225 mW
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
DEVICE INFORMATION
THS4508
(RGT PACKAGE)
(TOP VIEW)
VS-
16
15
14
13
NC
1
12
PD
VIN-
2
11
VIN+
VOUT+
3
10
VOUT-
CM
4
9
5
6
7
CM
8
VS+
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE)
NO.
DESCRIPTION
NAME
1
NC
No internal connection
2
VIN–
Inverting amplifier input
3
VOUT+
Noninverted amplifier output
4,9
CM
Common-mode voltage input
5,6,7,8
VS+
Positive amplifier power supply input
10
VOUT–
Inverted amplifier output
11
VIN+
Noninverting amplifier input
12
PD
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation
13,14,15,16
VS–
Negative amplifier power supply input
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS; VS+– VS– = 5 V:
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 10 dB, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, T = 25°C Single-Ended Input, Differential Output, Input Referenced to Ground, and Output Referenced to
Mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
AC PERFORMANCE (Figure 44)
Small-Signal Bandwidth
G = 6 dB, VO = 100 mVPP
2
G = 10 dB, VO = 100 mVPP
1.7
GHz
G = 14 dB, VO = 100 mVPP
600
MHz
G = 20 dB, VO = 100 mVPP
300
MHz
Gain-Bandwidth Product
G = 20 dB
Bandwidth for 0.1dB flatness
Large-Signal Bandwidth
3
GHz
G = 10 dB, VO = 2 VPP
400
MHz
G = 10 dB, VO = 2 VPP
1.5
GHz
6400
V/µs
0.5
ns
0.5
ns
2
ns
Slew Rate (Differential)
Rise Time
VO = 2-V Step
Fall Time
Settling Time to 0.1%
2nd Order Harmonic Distortion
3rd Order Harmonic Distortion
GHz
f = 10 MHz
–104
f = 50 MHz
–82
f = 100 MHz
–69
f = 10 MHz
–105
f = 50 MHz
–92
f = 100 MHz
2nd Order Intermodulation Distortion
200 kHz tone spacing,
RL = 499 Ω
3rd Order Intermodulation Distortion
2nd Order Output Intercept Point
200 kHz tone spacing,
RL = 100 Ω
3rd Order Output Intercept Point
dBc
C
–81
fC = 70 MHz
–78
fC = 140 MHz
–64
fC = 70 MHz
–95
fC = 140 MHz
–78
fC = 70 MHz
78
fC = 140 MHz
58
fC = 70 MHz
42
fC = 140 MHz
dBc
dBm
35
fC = 70 MHz
12.2
fC = 140 MHz
10.8
Noise Figure
50-Ω system, 10 MHz
19.2
dB
Input Voltage Noise
f > 10 MHz
2.3
nV/√Hz
Input Current Noise
f > 10 MHz
2.9
pA/√Hz
1-dB Compression Point (2)
dBm
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
Input Offset Voltage
68
TA = 25°C
1
4
TA = -40°C to 85°C
1
5
Average Offset Voltage Drift
Input Bias Current
2.3
TA = 25°C
TA = -40°C to 85°C
Average Bias Current Drift
Input Offset Current
(2)
4
8
15.5
8
18.5
20
TA = 25°C
0.5
3.6
TA = -40°C to 85°C
0.5
7
Average Offset Current Drift
(1)
1.75
7
dB
C
mV
A
µA/°C
B
µA
A
nA/°C
B
µA
A
nA/°C
B
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
The 1-dB compression point is measured at the load with 50-Ω double termination. Add 3 dB to refer to amplifier output.
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
ELECTRICAL CHARACTERISTICS; VS+– VS– = 5 V: (continued)
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 10 dB, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, T = 25°C Single-Ended Input, Differential Output, Input Referenced to Ground, and Output Referenced to
Mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL (1)
V
B
dB
B
INPUT
Common-Mode Input Range High
2.3
Common-Mode Input Range Low
-0.3
Common-Mode Rejection Ratio
90
OUTPUT
Maximum Output Voltage High
Each output with 100 Ω
to mid-supply
Minimum Output Voltage Low
Differential Output Voltage Swing
TA = 25°C
3.7
3.8
TA = -40°C to 85°C
3.6
3.8
TA = 25°C
TA = -40°C to 85°C
V
1.2
1.3
1.2
1.4
TA = 25°C
4.8
5.2
TA = -40°C to 85°C
4.4
5.2
A
V
A
Differential Output Current Drive
RL = 10 Ω
96
mA
C
Output Balance Error
VO = 100 mV, f = 1 MHz
-43
dB
C
Closed-Loop Output Impedance
f = 1 MHz
0.3
Ω
C
Small-Signal Bandwidth
700
MHz
Slew Rate
110
V/µs
1
V/V
OUTPUT COMMON-MODE VOLTAGE CONTROL
Gain
Output Common-Mode Offset from CM input
1.25 V < CM < 3.5 V
5
mV
CM Input Bias Current
1.25 V < CM < 3.5 V
±40
µA
CM Input Voltage Range
1.25 to
3.75
V
CM Input Impedance
32 || 1.5
kΩ || pF
2.5
V
CM Default Voltage
C
POWER SUPPLY
3.75 (3)
Specified Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
5
5.25
TA = 25°C
39.2
42.5
TA = -40°C to 85°C
39.2
43.5
TA = 25°C
TA = -40°C to 85°C
35.9
39.2
35
39.2
Power Supply Rejection (±PSRR)
To differential output
POWERDOWN
Referenced to Vs-
Enable Voltage Threshold
Device assured on above 2.1 V
> 2.1
Disable Voltage Threshold
Device assured off below 0.7 V
< 0.7
TA = 25°C
0.65
0.9
TA = -40°C to 85°C
0.65
1
Powerdown Quiescent Current
Input Bias Current
PD = VS–
Input Impedance
90
V
C
mA
A
dB
C
V
C
mA
A
100
µA
50 || 2
kΩ || pF
Turn-on Time Delay
Measured to output on
55
ns
Turn-off Time Delay
Measured to output off
10
µs
(3)
C
See the Application Information section of this data sheet for device operation with full supply voltages less than 5 V.
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+– VS– = 5 V
Test conditions unless otherwise noted: VS+ = 5 V, VS– = 0 V, G = 10 dB, CM = open, VO = 2 VPP, RF = 349 Ω, RL = 200 Ω
Differential, Single-Ended Input, Input Referenced to Ground and Output Referenced to Midrail
Small-Signal Frequency Response
Figure 2
Large Signal Frequency Response
Figure 3
HD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 4
HD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 5
HD2, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 6
HD3, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 7
HD2, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 8
HD3, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 9
HD2, G = 10 dB
vs Output voltage
Figure 10
HD3, G = 10 dB
vs Output voltage
Figure 11
HD2, G = 10 dB
vs CM input voltage
Figure 12
HD3, G = 10 dB
vs CM input voltage
Figure 13
IMD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 14
IMD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 15
IMD2, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 16
IMD3, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 17
IMD2, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 18
IMD3, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 19
OIP2
vs Frequency
Figure 20
OIP3
vs Frequency
Figure 21
S-Parameters
vs Frequency
Figure 22
Transition Rate
vs Output Voltage
Figure 23
Harmonic
Distortion
Intermodulation
Distortion
Output Intercept Point
Transient Response
Figure 24
Settling Time
Figure 25
0.1 dB Flatness
Figure 26
Rejection Ratio
vs Frequency
Figure 27
Output Impedance
vs Frequency
Figure 28
Overdrive Recovery
Output Voltage Swing
Figure 29
vs Load Resistance
Turn-Off Time
Figure 30
Figure 31
Turn-On Time
Figure 32
Input Offset Voltage
vs Input Common-Mode Voltage
Figure 33
Open Loop Gain
vs Frequency
Figure 34
Input Referred Noise
vs Frequency
Figure 35
Noise Figure
vs Frequency
Figure 36
Quiescent Current
vs Supply Voltage
Figure 37
Output Balance Error
vs Frequency
Figure 38
CM Input Impedance
vs Frequency
Figure 39
CM Small-Signal Frequency Response
Figure 40
CM Input Bias Current
vs CM Input Voltage
Figure 41
Differential Output Offset Voltage
vs CM Input Voltage
Figure 42
Output Common-Mode Offset
vs CM Input Voltage
Figure 43
6
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
22
G = 20 dB
20
20
18
18
16
Small Signal Gain - dB
Small Signal Gain - dB
22
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
G = 20 dB
16
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
4
4
VO = 100 mVPP
2
VOD = 2 VPP
2
0
0
100 k
10 M
100 M
f - Frequency - Hz
1M
1G
100 k
10 G
10 M
100 M
f - Frequency - Hz
1M
Figure 2.
10 G
Figure 3.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
-60
-50
G = 6 dB,
VOD = 2 VPP
-60
-70
-70
G = 6 dB,
VOD = 2 VPP
-80
-80
HD3 - dBc
HD2 - dBc
1G
RL = 100 W
-90
R L = 1 kW
RL = 200 W
-90
-100
RL = 499 W
RL = 100 W
-100
-110
-110
R L = 1 kW
RL = 499 W
-120
1M
10 M
100 M
-120
1M
1G
10 M
Figure 4.
1G
Figure 5.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
-60
-60
G = 10 dB,
VOD = 2 VPP
-70
HD3 - dBc
RL = 100 W
-90
RL = 200 W
R L = 1 kW
-90
RL = 100 W
-100
-100
RL = 499 W
R L = 1 kW
10 M
RL = 200 W
-110
RL = 499 W
-110
-120
1M
G = 10 dB,
VOD = 2 VPP
-80
-80
HD2 - dBc
100 M
f - Frequency - Hz
f - Frequency - Hz
-70
RL = 200 W
100 M
1G
-120
1M
10 M
100 M
1G
f - Frequency - Hz
f - Frequency - Hz
Figure 6.
Figure 7.
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HD2 vs FREQUENCY
HD3 vs FREQUENCY
-60
-50
G = 14 dB,
VOD = 2 VPP
G = 14 dB,
VOD = 2 VPP
-60
-70
-70
RL = 100 W
-80
-90
HD3 - dBc
HD2 - dBc
RL = 200 W
-90
-100
RL = 499 W
R L = 1 kW
-80
RL = 499 W
RL = 100 W
-100
-110
RL = 200 W
R L = 1 kW
-120
1M
10 M
100 M
-110
1M
1G
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 8.
HD2 vs OUTPUT VOLTAGE
HD3 vs OUTPUT VOLTAGE
-40
-50
f = 100 MHz
f = 100 MHz
-60
-60
f = 64 MHz
HD3 - dBc
f = 64 MHz
-70
HD2 - dBc
f = 150 MHz
G = 10 dB,
VOD = 2 VPP
f = 150 MHz
G = 10 dB,
VOD = 2 VPP
-50
f = 32 MHz
-80
-90
-70
f = 32 MHz
-80
-90
f = 8 MHz
-100
-100
f = 16 MHz
-110
-110
-120
-120
0
1
3
2
4
f = 16 MHz
f = 8 MHz
0
5
1
Figure 10.
HD2 vs CM OUTPUT VOLTAGE
HD3 vs CM OUTPUT VOLTAGE
0
VCM = 1.2 V to 3.8 V
VOD = 2 VPP
VCM = 1.2 V to 3.8 V
VOD = 2 VPP
-20
150 MHz
150 MHz
100 MHz
-40
HD3 - dBc
-30
-50
-70
64 MHz
100 MHz
-60
-80
64 MHz
-90
16 MHz
-100
-110
1 MHz
1.2
1 MHz
16 MHz
4 MHz
-130
1.6
2
2.4
5
4
Figure 11.
10
-10
3
2
VO - Output Voltage -VPP
VO - Output Voltage -VPP
8
1G
Figure 9.
-40
HD2 - dBc
100 M
2.8
4 MHz
-120
3.6 3.8
3.2
1.2
1.6
2
2.4
2.8
3.2
CM - Common Mode Input Voltage - V
CM - Common Mode Input Voltage - V
Figure 12.
Figure 13.
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IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
-50
−30
G = 6 dB,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
−40
-60
RL = 200 W
RL = 100 W
−50
RL = 100 W
-70
IMD3- dBc
IMD2 − dBc
G = 6 dB,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
−60
−70
-90
RL = 499 W
−80
R L = 1 kW
RL = 1 kW
−90
RL = 200 W
-80
-100
RL = 499 W
-110
−100
0
50
100
150
0
200
50
100
f − Frequency − MHz
Figure 14.
IMD3 vs FREQUENCY
-60
G = 10 dB,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
-40
RL = 100 W
G = 10 dB,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
-65
RL = 200 W
RL = 100 W
-70
IMD3 - dBc
-50
IMD2 - dBc
200
Figure 15.
IMD2 vs FREQUENCY
-30
150
f - Frequency - MHz
-60
-70
RL = 499 W
-80
-75
RL = 200 W
-80
-85
R L = 1 kW
-90
R L = 1 kW
-90
-95
-100
-100
RL = 499 W
0
50
100
150
200
0
50
100
200
f - Frequency - MHz
f - Frequency - MHz
Figure 16.
Figure 17.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
-60
-40
RL = 100 W
RL = 100 W
-65
-50
-70
RL = 200 W
RL = 200 W
-75
IMD3 - dBc
-60
IMD2 - dBc
150
R L = 1 kW
-70
RL = 499 W
-80
-80
-85
R L = 1 kW
-90
-95
-100
G = 14 dB,
VOD = 2 VPP Envelope,
-90
RL = 499 W
-105
200 kHz Tone Spacing
G = 14 dB,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
-110
-100
0
50
100
150
200
0
f - Frequency - MHz
50
100
150
200
f - Frequency - MHz
Figure 18.
Figure 19.
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OIP2 vs FREQUENCY
90
OIP3 vs FREQUENCY
50
G = 10 dB
85
80
45
G = 14 dB
G = 10 dB
70
65
G = 6 dB
60
G = 6 dB
40
OIP3 - dBm
OIP2 - dBm
75
G = 14 dB
35
55
RL = 100 W,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
50
45
40
0
50
RL = 100 W,
VOD = 2 VPP Envelope,
200 kHz Tone Spacing
30
100
150
25
200
0
50
f - Frequency - MHz
150
Figure 21.
S-PARAMETERS vs FREQUENCY
TRANSITION RATE vs OUTPUT VOLTAGE
20
8000
7000
S21
0
-20
Transition Rate - V/ms
-10
S11
-30
-40
S22
-50
-60
S12
-70
Rising
Gain = 10 dB,
RL = 200 W
20 % - 80%
10
6000
Falling
5000
4000
3000
2000
1000
-80
-90
100 k
1M
10 M
100 M
1G
0
10 G
0
f - Frequency - Hz
0.5
1
1.5
2
3
3.5
Figure 23.
TRANSIENT RESPONSE
SETTLING TIME
4
0.5
3.75
VOD = 2 V step
3.5
0.3
3.25
3
Gain = 10 dB,
RL = 200 W,
VOD = 2 VPP
2.75
2.5
2.25
2
1.75
1.5
Percent of Final Value - %
VOD - Differential Output Voltage - V
2.5
VO - Output Voltage - V
Figure 22.
0.1
-0.1
-0.3
1.25
-0.5
1
t - Time - (250 psec/div)
t - Time - 1 ns/div
Figure 24.
10
200
f - Frequency - MHz
Figure 20.
s-Parameters - dB
100
Figure 25.
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0.1-dB FLATNESS
REJECTION RATIO vs FREQUENCY
10.5
90
VOD = 100 mVPP
Rejection Ratio - dB
Signal Gain - dB
PSRR+
80
10.3
10.2
10.1
10
9.9
9.8
70
CMRR
60
50
40
30
20
9.7
VCM = VS / 2,
RL = 200 W
10
9.6
100 k
0
1M
10 M
100 M
1G
10 k
100 k
1M
f - Frequency - Hz
Figure 26.
100 M
OUTPUT IMPEDANCE vs FREQUENCY
OVERDRIVE RECOVERY
5.75
2
4.75
Input
1.5
VO - Output Voltage - V
3.75
10
1
2.75
1
Output
1.75
0.5
0.75
-0.25
0
-1.25
-0.5
-2.25
Gain = 10 dB,
RL = 200 W
-3.25
-4.25
0.1
100 k
-1
-1.5
-5.25
1M
10 M
1G
Figure 27.
100
ZO - Output Impedance - W
10 M
f - Frequency - Hz
100 M
VI - Input Voltage - V
10.4
100
t - Time - 100 ns/div
1G
f - Frequency - Hz
Figure 28.
Figure 29.
6
5
4
3
2
1
0
10
100
1000
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Output
PD Input
Gain = 10 dB,
RL = 200 W
6.4
6
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
Powerdown Input - V
TURN-OFF TIME
3.2
VO - Output Voltage - V
VOD - Differential Output Voltage Swing - V
VOD SWING vs LOAD RESISTANCE
7
0.4
0
t - Time - (2.5 ms/div)
RL - Load Resistance - kW
Figure 30.
Figure 31.
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INPUT OFFSET VOLTAGE vs CM INPUT VOLTAGE
PD Input
Output
Gain = 10 dB,
RL = 200 W
10
9
VOS - Input Offset Voltage - mV
6.4
6
5.6
5.2
4.8
4.4
4
3.6
3.2
2.8
2.4
2
1.6
1.2
0.8
0.4
0
Powerdown Input - V
VO - Output Voltage - V
TURN-ON TIME
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-0.2
8
7
6
5
4
3
2
1
0
-0.5
t - Time - (2.5 ms/div)
0.5
0
1
2
1.5
3
2.5
VIC - Commom-Mode Input Voltage - V
Figure 32.
Figure 33.
OPEN LOOP GAIN AND PHASE vs FREQUENCY
INPUT REFERRED NOISE vs FREQUENCY
100
50
90
−50
50
40
−100
30
20
−150
10
−200
In - Current Noise - pAÖHz
Open Loop Gain − dB
Phase
Gain
60
Vn - Voltage Noise - nVÖHz
0
70
Open Loop Phase − degrees
80
10
In
Vn
0
−10
100
1
10 k
1M
100 M
10 G
1
−250
0.01
0.1
f − Frequency − Hz
f - Frequency - Hz
Figure 34.
Figure 35.
NOISE FIGURE vs FREQUENCY
QUIESCENT CURRENT vs SUPPLY VOLTAGE
22
44
21
G = 6 dB
IQ - Quiescent Current - mA
Noise Figure - dB
19
G = 10 dB
18
17
G = 14 dB
50-W System
16
15
14
TA = 25oC
42
20
G = 20 dB
TA = 85oC
40
38
36
TA = -40oC
34
32
30
13
12
0
20
40
60
80 100 120 140
160 180
200
28
3.75
4
4.25
4.5
4.75
VS - Supply Voltage - V
f - Frequency - MHz
Figure 36.
12
10
1
Figure 37.
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OUTPUT BALANCE ERROR vs FREQUENCY
CM INPUT IMPEDANCE vs FREQUENCY
0
100 k
Output Balance Error - dB
Common-Mode Input Impedance - W
Gain = 10 dB,
VCOM = VS / 2,
-10
RL = 200 W,
VOD = 2 VPP
-20
-30
-40
-50
-60
100 k
10 M
1M
100 M
10 k
1k
100
10
1G
100 k
Figure 39.
CM SMALL SIGNAL FREQUENCY RESPONSE
CM BIAS CURRENT vs CM INPUT VOLTAGE
5
Common-Mode Input-Bias Current - mA
200
0
-5
Gain - dB
1G
f - Frequency - Hz
Figure 38.
-10
-15
-20
-25
-30
100 k
1M
100 M
10 M
100
0
-100
-200
-300
1G
0
0.5
f - Frequency - Hz
1
1.5
2
2.5
3
3.5
4
5
4.5
VIC - Common-Mode Input Voltage - V
Figure 41.
VOD OFFSET VOLTAGE vs CM INPUT VOLTAGE
VOC OFFSET VOLTAGE vs CM INPUT VOLTAGE
4
3
2
1
0
-1
0
0.5
1
1.5
2
2.5
3
3.5
4.5
4
VIC - Common-Mode Input Voltage - V
5
VOC - Common-Mode Output Offset Voltage - mV
Figure 40.
5
Differential Output Offset Voltage - mV
100 M
10 M
1M
f - Frequency - Hz
50
40
30
20
10
0
-10
-20
-30
-40
-50
0
Figure 42.
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIC - Common-Mode Input Voltage - V
Figure 43.
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TEST CIRCUITS
The THS4508 is tested with the following test circuits
built on the EVM. For simplicity, the power supply
decoupling is not shown – see the layout in the
application information section for recommendations.
Depending on the test conditions, component values
are changed per the following tables, or as otherwise
noted. The signal generators used are ac coupled
50-Ω sources and a 0.22-µF capacitor and a 49.9-Ω
resistor to ground are inserted across RIT on the
alternate input to balance the circuit.
The output is probed using a high-impedance
differential probe across the 100-Ω resistor. The gain
is referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
From
50 W
Source
VIN
RF
RG
RIT
5V
49.9 W
RG
0.22 mF
THS4508
49.9 W
CM
RIT
RF
GAIN
RF
RG
RIT
6 dB
348 Ω
165 Ω
61.9 Ω
10 dB
348 Ω
100 Ω
69.8 Ω
14 dB
348 Ω
56.2 Ω
88.7 Ω
Distortion and 1 db Compression
20 dB
348 Ω
16.5 Ω
287 Ω
The circuit shown in Figure 45 is used to measure
harmonic distortion, intermodulation distortion, and
1-db compression point of the amplifier.
Note the gain setting includes 50-Ω source
impedance. Components are chosen to achieve
gain and 50-Ω input termination.
Table 2. Load Component Values
RL
RO
ROT
Atten.
100 Ω
25 Ω
open
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1k Ω
487 Ω
52.3 Ω
31.8 dB
Note the total load includes 50-Ω termination by
the test equipment. Components are chosen to
achieve load and 50-Ω line termination through a
1:1 transformer.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column Atten in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output as shown in
Figure 45, the signal will see slightly more loss, and
these numbers will be approximate.
Figure 44. Frequency Response Test Circuit
A signal generator is used as the signal source and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
a 0.22-µF capacitor and 49.9-Ω resistor to ground are
inserted across RIT on the alternate input.
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1 MHZ.
From
50 W
Source
VIN
RF
RG
RIT
5V
RO
Frequency Response
The circuit shown in Figure 44 is used to measure the
frequency response of the circuit.
A network analyzer is used as the signal source and
as the measurement device. The output impedance
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-µF
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
14
Output Measured
Here With High
Impedance
Differential Probe
Open
0.22 mF
49.9 W
Table 1. Gain Component Values
100 W
RG
0.22 mF
RIT
THS4508
CM
49.9 W
RO
1:1
VOUT
ROT
To 50 W
Test
Equipment
Open
0.22 mF
RF
Figure 45. Distortion Test Circuit
The 1-dB compression point is measured with a
spectrum analyzer with 50-Ω double termination or
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100-Ω termination as shown in Table 2. The input
power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
the power delivered to the spectrum analyzer input.
Add 3 dB to refer to the amplifier output.
S-Parameter, Slew Rate, Transient Response,
Settling Time, Output Impedance, Overdrive,
Output Voltage, and Turn-On/Off Time
The circuit shown in Figure 46 is used to measure
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the
amplifier. For output impedance, the signal is injected
at VOUT with VIN left open and the drop across the
49.9 Ω resistor is used to calculate the impedance
seen looking into the amplifier’s output.
Because S21 is measured single-ended at the load
with 50-Ω double termination, add 12 dB to refer to
the amplifier’s output as a differential signal.
From V IN
50-W
Source
RG
R IT
RF
5V
at VOUT+ or VOUT– with the input injected at VIN, RCM =
0 Ω and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
RF
RG
0.22 mF
RIT
5V
49.9 W
49.9 W
VOUT–
RG
0.22 mF
THS4508
VOUT+
CM
RIT
VOUT+
THS4508
49.9 W
VOUT-
0.22 mF
R IT
CM
49.9 W
To 50-W
Test
Equipment
Open
0.22 mF
VIN
Figure 46. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-on/off Test Circuit
RCMT
RF
From
50-W
source
Figure 47. CM Input Test Circuit
CMRR and PSRR
The circuit shown in Figure 48 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being
performed.
348 W
VS+
PSRR+
From VIN
50 W
CMRR
Source
5V
49.9 W
100 W
100 W
PSRRVS-
RF
RCM
49.9 W
49.9 W
RG
49.9 W
To
50-W
Test
Equipment
THS4508
CM
69.8 W
49.9 W
100 W
Open
0.22 mF
Output
Measured
Here
With High
Impedance
Differential
Probe
348 W
Figure 48. CMRR and PSRR Test Circuit
CM Input
The circuit shown in Figure 47 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single-ended
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APPLICATION INFORMATION
APPLICATIONS
Single-Ended
Input
The following circuits show application information for
the THS4508. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. For
more detail on the use and operation of fully
differential operational amplifiers, refer to application
report Fully-Differential Amplifiers (SLOA054) .
RG
RF
Differential
5V
Output
+
RG
–
VOUT–
THS4508
–
+
VOUT+
Differential Input to Differential Output Amplifier
The THS4508 is a fully differential operational
amplifier, and can be used to amplify differential input
signals to differential output signals. A basic block
diagram of the circuit is shown in Figure 49 (CM input
not shown). The gain of the circuit is set by RF
divided by RG.
RF
Differential
Input
5V
RG
+
V IN+
VIN–
Differential
Output
–
– +
VOUT+
RF
Figure 49. Differential Input to Differential Output
Amplifier
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
Single-Ended
Amplifier
Input
to
Differential
Output
The THS4508 can be used to amplify and convert
single-ended input signals to differential output
signals. A basic block diagram of the circuit is shown
in Figure 50 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
16
Figure 50. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
The input common-model voltage of a fully differential
operational amplifier is the voltage at the (+) and (–)
input pins of the operational amplifier.
It is important to not violate the input common-mode
voltage range (VICR) of the operational amplifier.
Assuming the operational amplifier is in linear
operation the voltage across the input pins is only a
few millivolts at most. So finding the voltage at one
input pin determines the input common-mode voltage
of the operational amplifier.
VOUT–
THS4508
RG
RF
Treating the negative input as a summing node, the
voltage is given by Equation 1:
ö
æ
ö æ
RG
RF
÷
÷ + ç VIN- ´
VIC = çç VOUT + ´
ç
÷
R G + R F ÷ø
R G + RF ø è
è
(1)
To determine the VICR of the operational amplifier, the
voltage at the negative input is evaluated at the
extremes of VOUT+.
As the gain of the operational amplifier increases, the
input common-mode voltage becomes closer and
closer to the input common-mode voltage of the
source.
Setting the Output Common-Mode Voltage
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 5-mV offset (typical) from the set
voltage, when set within 0.5 V of mid-supply. If left
unconnected, the common-mode set point is set to
mid-supply by internal circuitry, which may be
over-driven from an external source. Figure 51 is
representative of the CM input. The internal CM
circuit has about 700 MHz of –3-dB bandwidth, which
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is required for best performance, but it is intended to
be a dc-bias input pin. Bypass capacitors are
recommended on this pin to reduce noise at the
output. The external current required to overdrive the
internal resistor divider is given by Equation 2:
IEXT =
2VCM - (VS + - VS - )
50 kW
RS
RG
VSignal
RIT
RF
RPD
VS+ = 3.75 V to 5 V
RO
THS4508
RG
(2)
RO
VOUTVOUT+
CM
RS
RIT
where VCM is the voltage applied to the CM pin, and
VS+ ranges from 3.75 V to 5 V, and VS- is 0 V
(ground).
RPD
VS–
VCM
RF
Figure 52. THS4508 DC Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
To Set VIC
VS+
50 kW
to internal
CM circuit
I EXT
CM
Note that in Figure 52, the source is referenced to
ground as is the input termination resistor RIT. The
proper value of resistance to add can be calculated
from Equation 3:
50 kW
RPD =
V S–
Figure 51. CM Input Circuit
1
é
1 ê
1 .6
ê
R F ê V S + - 1 .6
êë 2
ù
ú
1
ú R
I
ú
úû
Device Operation with Single Power Supplies
Less than 5 V
The THS4508 is optimized to work in systems using a
5-V single supply, and the characterization data
presented in this data sheet was taken with 5-V
single-supply inputs. For ac-coupled systems or
dc-coupled systems operating with supplies less than
5 V and greater than 3.75 V, the amplifier input
common-mode range is maximized by adding
pull-down resistors at the device inputs. The
pull-down resistors provide additional loading at the
input, and lower the common-mode voltage that is fed
back into the device input through resistor RF.
Figure 52 shows the circuit configuration for this
mode of operation where RPD is added to the
dc-coupled circuit to avoid violating the VICR of the
operational amplifier. Note RS and RIT are added to
the alternate input from the signal input to balance
the amplifier. One resistor that is equal to the
combined value RI = RG + RS||RIT can be placed at
the alternate input.
(3)
where RI = RG + RS||RIT.
VS+ is the power-supply voltage, RF is the feedback
resistance, RG is the gain-setting resistance, RS is the
signal source resistance, and RIT is the termination
resistance.
Table 3 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, a dc-coupled
50-Ω source impedance, and setting the output
common-mode voltage to mid-supply.
Table 3. RPD Values for Various Gains,
VS+ = 3.75 V, DC-coupled Signal Source
Gain
RF
RG
RIT
RPD
6 dB
348 Ω
169 Ω
64.9 Ω
86.6 Ω
10 dB
348 Ω
102 Ω
78.7 Ω
110 Ω
14 dB
348 Ω
61.9 Ω
115 Ω
158 Ω
20 dB
348 Ω
40.2 Ω
221 Ω
226 Ω
If the signal originates from an ac-coupled 50-Ω
source (see Figure 53), the equivalent dc-source
resistance is an open circuit and RI = RG + RIT.
Table 4 is a modification of Table 1 to add the proper
values with RPD assuming VS+ = 3.75 V, an
ac-coupled 50-Ω source impedance, and setting the
output common-mode voltage to mid-supply.
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Table 4. RPD Values for Various Gains,
VS+ = 3.75 V, AC-coupled Signal Source
RF
RG
RIT
RPD
6 dB
348 Ω
169 Ω
64.9 Ω
80.6 Ω
10 dB
348 Ω
102 Ω
78.7 Ω
90.9 Ω
14 dB
348 Ω
61.9 Ω
115 Ω
90.9 Ω
20 dB
348 Ω
40.2 Ω
221 Ω
77.6 Ω
C
RS
V Signal
0.4
RF
RG
RIT
0.6
Voltage - V
Gain
0.8
RPD
0.2
0
-0.2
VS+ = 3.75 V to 5 V
-0.4
0
RO
5
V OUTTHS4508
RIT
RS
RO
V OUT+
C
RPD
V S-
CM
Figure 53. THS4508 AC Coupled Single-Source
Supply Range From 3.75 V to 5 V With RPD Used
To Set VIC
Video Buffer
Figure 54 shows a possible application of the
THS4508 as a dc-coupled video buffer with a gain of
2. Figure 55 shows a plot of the Y' signal originating
from a HDTV 720p video system. The input signal
includes a 3-level sync (minimum level at -0.3 V), and
the portion of the video signal with maximum
amplitude of 0.7 V. Although the buffer draws its
power from a 5-V single-ended power supply, internal
level shifters allow the buffer to support input signals
which are as much as -0.3 V below ground. This
allows maximum design flexibility while maintaining a
minimum parts count. Figure 56 shows the differential
output of the buffer. Note that the dc-coupled
amplifier can introduce a dc offset on a signal applied
at its input
Video
Source
VSignal
VIN
348 W
175 W
130 W
VS+ = 5 V
RO
THS4508
175 W
75 W
130 W
VS-
RO
VOD
VCM
348 W
Figure 54. Single-Supply Video Buffer, Gain = 2
18
20
1.5
RF
RS = 75 W
15
Figure 55. Y' Signal With 3-Level Sync and Video
Signal
VOD - Video Buffer Output - V
RG
10
t - Time - ms
1
0.5
0
-0.5
-1
0
5
10
15
20
t - Time - ms
Figure 56. Video Buffer Differential Output Signal
THS4508 + ADS5500 Combined Performance
The THS4508 is designed to be a high performance
drive amplifier for high performance data converters
like the ADS5500 14-bit 125-MSPS ADC. Figure 57
shows a circuit combining the two devices, and
Figure 58 shows the combined SNR and SFDR
performance versus frequency with –1 dBFS input
signal level sampling at 125 MSPS. The THS4508
amplifier circuit provides 10 dB of gain, and converts
the single-ended input signal to a differential output
signal. The default common-mode output of the
THS4508 (2.5 V) is not compatible with the required
common-mode input of the ADS5500 (1.55 V), so
dc-blocking capacitors are added (0.22 µF). Note that
a biasing circuit (not shown in Figure 57) is needed to
provide the required common-mode, dc-input for the
ADS5500. The 100-Ω resistors and 2.7-pF capacitor
between the THS4508 outputs and ADS5500 inputs
along with the input capacitance of the ADS5500 limit
the bandwidth of the signal to 115 MHz (–3 dB). For
testing, a signal generator is used for the signal
source. The generator is an ac-coupled 50-Ω source.
A band-pass filter is inserted in series with the input
to reduce harmonics and noise from the signal
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source. Input termination is accomplished via the
69.8-Ω resistor and 0.22-µF capacitor to ground in
conjunction with the input impedance of the amplifier
circuit. A 0.22-µF capacitor and 49.9-Ω resistor is
inserted to ground across the 69.8-Ω resistor and
0.22-µF capacitor on the alternate input to balance
the circuit. Gain is a function of the source
impedance, termination, and 348-Ω feedback resistor.
See Table 1 for component values to set proper 50-Ω
termination for other common gains.
From
50-W
source
VIN
100 W
When the THS4508 is operated from a single power
supply with VS+ = 5 V and VS- = ground, the 2.5-V
output common-mode voltage is compatible with the
recommended value of the ADS5424 input
common-mode voltage (2.4 V).
From
50-W
source
348 W
5V
69.8 W
The 225-Ω resistors and 2.7-pF capacitor between
the THS4508 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100 MHz (-3 dB).
0.22 mF
V IN
69 .8 W
49.9 W
5V
14-bit,
125 MSPS
100 W
225 W
A IN +
THS4508
100 W
348 W
100 W
100
ADS5500
2.7 pF
THS4508
A IN - CM
CM
69.8 W
0.22 mF
49 .9 W
100 W
225 W
CM
69 .8 W
49.9 W
0.22 mF
0.22 mF
2 .7 pF
0.1 mF
0.1 mF
348 W
348 W
14-bit,
105 MSPS
A IN+
ADS5424
A IN– VBG
0.1 mF
Figure 59. THS4508 + ADS5424 Circuit
Figure 57. THS4508 + ADS5500 Circuit
95
95
SFDR
90
90
85
85
SFDR
80
80
75
75
SNR
70
SNR
70
65
60
10
65
20
30
40
50
60
70
80
90
100
110
10
20
30
40
50
60
Input Frequency - MHz
Input Frequency - MHz
Figure 58. THS4508 + ADS5500 SFDR and SNR
Performance versus Frequency
Figure 60. THS4508 + ADS5424 SFDR and SNR
Performance vs Frequency
THS4508 + ADS5424 Combined Performance
Figure 59 shows the THS4508 driving the ADS5424
ADC, and Figure 60 shows their combined SNR and
SFDR performance versus frequency with –1 dBFS
input signal level and sampling at 80 MSPS.
As before, the THS4508 amplifier provides 10 dB of
gain, converts the single-ended input to differential,
and sets the proper input common-mode voltage to
the ADS5424. Input termination and circuit testing is
the same as described above for the THS4508 +
ADS5500 circuit.
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
Layout Recommendations
It is recommended to follow the layout of the external
components near the amplifier, ground plane
construction, and power routing of the EVM as
closely as possible. General guidelines are:
1. Signal routing should be direct and as short as
possible into and out of the operational amplifier
circuit.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
4. An output resistor is recommended on each
output, as near to the output pin as possible.
5. Two 10-µF and two 0.1-µF power-supply
decoupling capacitors should be placed as near
to the power-supply pins as possible.
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a solid
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
20
and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
9. The THS4508 recommended PCB footprint is
shown in Figure 61.
0.144
0.049
0.012
Pin 1
0.0095
0.015
0.144
0.0195 0.0705
0.010
vias
0.032
0.030
0.0245
Top View
Figure 61. QFN Etch and Via Pattern
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
THS4508 EVM
Figure 62 is the THS4508 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown in Figure 63 through
Figure 66 , and Table 5 is the bill of material for the EVM as supplied from TI.
GND
VS+
J5
J6
VCC
10 mF
TP1
348 W
R1
69.8 W
R3
C15
R12
49.9 W
2
3
VO+
+
R4
100 W
R2
69.8 W
TP2
C14
0.1 mF
VOPwrPad 10
4
R7
86.6 W
R8
86.6 W
J3
T1
R11
69.8 W
6
5
4
15 13
14 16
R10
open
R6
C1
open
1
3
XFMR_ADT1-1WT
Vocm
9
C13
R9
open
7
PD
U1 11
0.22 mF
J2
5
12
0.1 mF
C12
VCC
VCC
8
6
100 W
0.1 mF
C5
J8
R5
J1
10 mF
C3
C8
open
C7
open
C2
open
J7
348 W
TP3
C11
0.1 mF
Figure 62. THS4508 EVAL1 EVM Schematic
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THS4508
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
Table 5. THS4508RGT EVM Bill of Materials
ITEM
(1)
22
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER (1)
1
CAP, 10.0 µF, Ceramic, X5R, 6.3V
0805
C3, C5
2
(AVX) 08056D106KAT2A
2
CAP, 0.1 µF, Ceramic, X5R, 10V
0402
C11, C12, C13, C14
4
(AVX) 0402ZD104KAT2A
3
CAP, 0.22 µF, Ceramic, X5R, 6.3V
0402
C15
1
(AVX) 04026D224KAT2A
4
OPEN
0402
C1, C2, C7, C8, C9, C10
6
5
OPEN
0402
R9, R10
2
6
Resistor, 49.9 Ω, 1/16W, 1%
0402
R12
1
(KOA) RK73H1ETTP49R9F
8
Resistor, 69.8 Ω, 1/16W, 1%
0402
R1, R2, R11
3
(KOA) RK73H1ETTP69R8F
9
Resistor, 86.6 Ω, 1/16W, 1%
0402
R7, R8
2
(KOA) RK73H1ETTP86R6F
10
Resistor, 100 Ω, 1/16W, 1%
0402
R3, R4
2
(KOA) RK73H1ETTP1000F
11
Resistor, 348 Ω, 1/16W, 1%
0402
R5, R6
2
(KOA) RK73H1ETTP3480F
12
Resistor, 0 Ω, 5%
0805
C4, C6
2
(KOA) RK73Z2ATTD
13
Transformer, RF
T1
1
(MINI-CIRCUITS) ADT1-1WT
14
Jack, banana receptance, 0.25" diameter
hole
J5, J6
15
OPEN
J1, J7, J8
3
16
Connector, edge, SMA PCB Jack
J2, J3
2
(JOHNSON) 142-0701-801
17
Test point, Red
TP1, TP2, TP3
3
(KEYSTONE) 5000
18
IC, THS4508
U1
1
(TI) THS4508RGT
19
Standoff, 4-40 HEX, 0.625" length
4
(KEYSTONE) 1808
20
SCREW, PHILLIPS, 4-40, 0.250"
4
SHR-0440-016-SN
21
Printed circuit board
1
(TI) EDGE# 6468901
The manufacturer's part numbers were used for tesr purposes only.
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(HH SMITH) 101
THS4508
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
Figure 63. THS4508 EVM Top Layer
Figure 64. THS4508 EVM Layer 1
Figure 65. THS4508 EVM Layer 2
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SLAS459A – SEPTEMBER 2005 – REVISED FEBRUARY 2006
Figure 66. THS4508 EVM Bottom Layer
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the table provided
below.
Input Range, VS+ to VS-
3.0 V to 6.0 V
Input Range, VI
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS-
Output Range, VO
3.0 V to 6.0 V NOT TO EXCEED VS+ or VS-
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
24
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4508RGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4508RGTRG4
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4508RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4508RGTTG4
ACTIVE
QFN
RGT
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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