TI OPA699M

OPA699M
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SGLS289A – MAY 2005 – REVISED MARCH 2006
GAIN +4 STABLE WIDEBAND VOLTAGE LIMITING AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Linearity Near Limiting
Fast Recovery from Overdrive: 1 ns
Limiting Voltage Accuracy: ±15 mV
–3-dB Bandwidth (G = +6): 260 MHz
Stable for G ≥ +4
Slew Rate: 1400 V/µs
±5-V and 5-V Supply Operation
High Gain Version of the OPA698
Low Prop Delay Comparator
Non-Linear Analog Signal Processing
Difference Amplifier
IF Limiting Amplifier
OPA689M Replacement
•
Transimpedance With Fast Overdrive
Recovery
Fast Limiting ADC Input Buffers
JD PACKAGE
(TOP VIEW)
NC
INVERTING INPUT
NONINVERTING INPUT
-V S
1
8
2
7
3
6
4
5
VH
+VS
OUTPUT
VL
NC - No internal connection
P0013-01
DESCRIPTION
The OPA699 is a wideband, voltage feedback op amp that offers bipolar output voltage limiting, and is stable for
gains ≥ +4. Two buffered limiting voltages take control of the output when it attempts to drive beyond these limits.
This new output limiting architecture holds the limiter offset error to ±15 mV. The op amp operates linearly to
within 30 mV of the limits.
The combination of narrow nonlinear range and low limiting offset allows the limiting voltages to be set within 100
mV of the desired linear output range 1-ns recovery from limiting ensures that overdrive signals will be
transparent to the signal channel. Implementing the limiting function at the output, as opposed to the input, gives
the specified limiting accuracy for any gain and allows the OPA699 to be used in all standard op amp
applications.
Non-linear analog signal processing circuits will benefit from the ability of the OPA699 to sharply transition from
linear operation to output limiting. The quick recovery time supports high speed applications.
The OPA699M is available in an industry-standard pinout in a CDIP-8 package. For lower gain applications
requiring output limiting with fast recovery, consider the OPA698M.
ORDERING INFORMATION (1)
TA
-55°C to 125°C
(1)
PACKAGE
CDIP – JD
Tube
ORDERABLE PART NUMBER
TOP-SIDE MARKING
OPA699MJD
OPA699MJD
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
OPA699M
www.ti.com
SGLS289A – MAY 2005 – REVISED MARCH 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Power supply
±6.5 V
VICM
Common-mode input voltage
±VS
VID
Differential input voltage
±VS
Limiter voltage range
±(VS - 0.7 V)
TA
Operating free-air temperature range
–55°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300°C
Case temperature for 10 seconds
260°C
TJ
Junction temperature
θJC
Package thermal impedance (2) (JD Package)
(1)
(2)
150°C
14.5°C/W
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The package thermal impedance is measured per MIL-STD-883, Method 1012.1.
RECOMMENDED OPERATING CONDITIONS
MIN
Operating voltage
Split-rail operation
Single-supply operation
Operating free-air temperature
2
–55
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NOM
MAX
±5
±6
5
12
125
UNIT
V
°C
OPA699M
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SGLS289A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS
VS = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (see Figure 47)
VO < 0.5 Vp-p, G = +6
Small signal bandwidth
260
VO < 0.5 Vp-p, G = +12
86
VO < 0.5 Vp-p, G = –6
269
MHz
Gain bandwidth product (G ≥ +20)
VO < 0.5 Vp-p
Gain peaking
VO = 0.5 V, G = +4
7.5
dB
Bandwidth for 0.1-dB gain flatness
VO = 0.5 V
30
MHz
Large signal bandwidth
VO = 2 Vp-p
290
MHz
Slew rate
VO = 2 V step
1400
V/µs
Rise and falll time
VO = 0.5 V step
Settling time to 0.05%
VO = 2 V step
1000
MHz
1.6
ns
8
ns
Even
67
Odd
87
Spurious free dynamic range
VO = 2 Vp-p, f = 5 MHz
dB
Differential gain
RL = 500 Ω, NTSC, PAL
0.012%
Differential phase
RL = 500 Ω, NTSC, PAL
0.008
Input noise, voltage noise density
f ≥ 1 MHz
4.1
nV/√Hz
Input noise, current noise density
f ≥ 1 MHz
2
pA/√Hz
°
DC PERFORMANCE
Open-loop voltage gain (AVOL)
VO = ±0.5 V
TA = 25°C
54
TA = Full range
47
TA = 25°C
Input offset voltage (VIO)
62
±1.5
TA = Full range
3
TA = Full range
±10
±18
TA = 25°C
Input offset current (IIO)
±8
±12
TA = 25°C
Input bias current (IIB) (2)
dB
±0.3
TA = Full range
±3
±4
mV
µA
µA
INPUT
Common-mode rejection ratio (CMRR)
VICM = ±0.5 V,
Input referred
Common-mode input voltage range (VICR) (3)
TA = 25°C
54
TA = Full range
50
TA = 25°C
±3.2
TA = Full range
±3.1
Input impedance, differential mode
Input impedance, common mode
62
±3.3
dB
V
0.32
1
MΩ
pF
3.5
1
MΩ
pF
OUTPUT
Output voltage range (VOH, VOL)
VH = 4.3 V, VL = -4.3 V,
RL≥ 500 Ω
TA = 25°C
±3.9
TA = Full range
±3.7
Current output, sourcing (IOH)
VH = 4.3 V, VL = -4.3 V,
RL = 20 Ω
TA = 25°C
110
TA = Full range
100
Current output, sinking (IOL)
VH = 4.3 V, VL = -4.3 V,
RL = 20 Ω
TA = 25°C
–90
TA = Full range
–80
Closed-loop output impedance
G = +4, f < 100 kHz
(1)
(2)
(3)
±4.1
165
–130
0.8
V
mA
mA
Ω
All typical limits are at TA = 25°C unless otherwise specified.
Current is considered positive out of node.
CMIR tested as <3-dB degradation from minimum CMRR at specified limits.
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SGLS289A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = ±5 V, VICM = 0 V, RL = 500 Ω, limiter pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±5
±6
15
15.5
16
UNIT
POWER SUPPLY
Operating voltage (VS)
TA = 25°C
Quiescent current (IS)
ower supply rejection ratio (PSRR)
TA = Full range
Input referred,
VS = ±4.5 V to ±5.5 V
13.5
TA = 25°C
65
TA = Full range
60
18
76
V
mA
dB
OUTPUT VOLTAGE LIMITERS (PINS 5 AND 8)
Default output limited voltage
Limiter pins open
Limiter output offset voltage
(VO– VH) or (VO– VL)
Limiter input bias current magnitude (4)
VO = 0 V
TA = 25°C
TA = Full range
±3.3
TA = Full range
TA = 25°C
40
TA = Full range
35
±15
±50
55
65
70
f = 5 MHz
400
Op amp bias current shift(2)
Limter slew rate (6)
V
mV
3
VI = ±2 V, VO < 0.02 Vp-p
µA
dB
±4.3
Minimum limiter voltage separation
mV
MΩ
pF
–60
Maximum limiter voltage
Limiter small signal bandwidth
V
3.4
1
Limiter input impedance
Limiter feedthrough (5)
±3.6
±3
µA
600
MHz
125
V/µs
mV
Limiter step response, overshoot
VI = ±2 V
250
Limiter step response, recovery time
VI = ±2 V
1
ns
Linearity guardband (7)
VO = 2 Vp-p, f = 5 MHz
30
mV
(4)
(5)
(6)
(7)
4
IVH (VH bias current) is positive and IVL (VL bias current) is negative, under these conditions. See Note 2, Figure 47, and Figure 58.
Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
VH slew rate conditions are: VIN = +0.7 V, G = +6, VL = -2 V, VH = step between 2 V and 0 V. VL slew rate conditions are similar.
Linearity Guardband is defined for an output sinusoid (f = 1 MHz, VO = 2 Vp-p) centered between the limiter levels (VH and VL). It is the
difference between the limiter level and the peak output voltage where SFDR decreases by 3 dB (see Figure 59).
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SGLS289A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS
VS = 5 V, VICM = 2.5 V, RL = 500 Ω, limiter pins open (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (see Figure 48)
VO < 0.5 Vp-p, G = +6
Small signal bandwidth
234
VO < 0.5 Vp-p, G = +12
83
VO < 0.5 Vp-p, G = –6
242
Gain bandwidth product
VO < 0.5 Vp-p, G ≥ +20
880
Gain peaking
VO < 0.5 V, G = +4
Bandwidth for 0.1-dB gain flatness
VO = 0.5 Vp-p
Large signal bandwidth
VO = 2 Vp-p
Slew rate
Rise and falll time
Settling time to 0.05%
2 V step
MHz
MHz
8
dB
30
MHz
250
MHz
VO = 2 V step
1050
V/µs
VO = 0.5 V step
1.75
ns
8
ns
Even
64
Odd
70
Spurious free dynamic range
VO = 2 Vp-p, f = 5 MHz
dB
Input noise, voltage noise density
f ≥ 1 MHz
4.2
nV/√Hz
Input noise, current noise density
f ≥ 1 MHz
2.1
pA/√Hz
DC PERFORMANCE
Open-loop voltage gain (AVOL)
VO = ±0.4 V
TA = 25°C
54
TA = Full range
47
TA = 25°C
Input offset voltage (VIO)
61
±2
TA = Full range
±3
TA = Full range
±10
±15
TA = 25°C
Input offset current (IIO)
±8
±12
TA = 25°C
Input bias current (IIB) (2)
dB
±0.4
TA = Full range
±3
±4
mV
µA
µA
INPUT
VICM = ±0.5 V,
Input referred
Common-mode rejection ratio (CMRR)
TA = 25°C
52
TA = Full range
48
TA = 25°C
VICM
±0.7V
TA = Full range
VICM
±0.6V
) (3)
Common-mode input voltage range (VICR
Input impedance, differential mode
Input impedance, common mode
60
VICM
±0.8V
dB
V
0.32
1
MΩ
pF
1
1
MΩ
pF
OUTPUT
Output voltage range (VOH, VOL)
VH = VICM + 1.8 V,
VL = VICM – 1.8 V,
RL ≥ 500 Ω
Current output, sourcing (IOH)
VS = ±2.5 V, RL = 20 Ω
Current output, sinking (IOL)
VS = ±2.5 V, RL = 20 Ω
Closed-loop output impedance
G = +4, f < 100 kHz
(1)
(2)
(3)
TA = 25°C
VICM
±1.4V
TA = Full range
VICM
±1.3V
TA = 25°C
70
TA = Full range
60
TA = 25°C
–60
TA = Full range
–50
VICM
±1.6V
100
–90
0.2
V
mA
mA
Ω
All typical limits are at TA = 25°C unless otherwise specified.
Current is considered positive out of node.
CMIR tested as <3-dB degradation from minimum CMRR at specified limits.
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SGLS289A – MAY 2005 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
VS = 5 V, VICM = 2.5 V, RL = 500 Ω, limiter pins open (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5
12
13.5
14.3
15
UNIT
POWER SUPPLY
Operating voltage (VS)
TA = 25°C
Quiescent current (IS)
Power supply rejection ratio (PSRR)
TA = Full range
Input referred,
VS = 4 V to 6 V
12
16.5
58
74
TA = 25°C
VICM
±0.8V
VICM
±1.1V
TA = Full range
VICM
±0.6V
TA = Full range
V
mA
dB
OUTPUT VOLTAGE LIMITERS (PINS 5 AND 8)
Default output limited voltage
Limiter output offset voltage
Limiter input bias current magnitude (4)
Limiter pins open
(VO – VH) or (VO – VL)
VO = 2.5 V
TA = Full range
TA = 25°C
40
TA = Full range
35
V
±15
±50
50
65
70
mV
µA
Limiter input bias current drift
30
nA/°C
Limiter input impedance
3.4
1
MΩ
pF
Limiter feedthrough (5)
f = 5 MHz
–60
Maximum limiter voltage
Minimum limiter voltage separation
400
Output bias current shift(2)
Limiter small signal bandwidth
dB
VICM
±1.8V
mV
5
VI = VICM ±0.4 V, VO < 0.02 Vp-p
Limter slew rate (6)
V
µA
450
MHz
100
V/µs
mV
Limiter step response, overshoot
VI = VICM ±0.4 V
55
Limiter step response, recovery time
VI = VICM ±0.4 V
3
ns
Linearity guardband (7)
VO = 2 Vp-p, f = 5 MHz
30
mV
(4)
(5)
(6)
(7)
6
IVH (VH bias current) is positive and IVL (VL bias current) is negative, under these conditions. See Note 2, Figure 47, and Figure 58.
Limiter feedthrough is the ratio of the output magnitude to the sinewave added to VH (or VL) when VIN = 0.
VH slew rate conditions are: VIN = 0.7 V, G = +6, VL = -2 V, VH = stepped between 2 V and 0 V. VL slew rate conditions are similar.
Linearity Guardband is defined for an output sinusoid (f = 1 MHz, VO = 2 Vp-p) centered between the limiter levels (VH and VL). It is the
difference between the limiter level and the peak output voltage where SFDR decreases by 3 dB (see Figure 59).
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SGLS289A – MAY 2005 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = ±5 V
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
9
6
G = +6
3
0
-3
G = +12
-6
-9
G = -4
VO = 0.5VPP
3
Normalized Gain (dB)
Normalized Gain (dB)
G = +4
VO = 0.5VPP
G = -6
0
-3
G = -12
-6
-9
-12
G = +20
-15
-12
See Figure 47
-18
-15
1M
10M
100M
1M
1G
Frequency (Hz)
1G
G001
G002
Figure 2.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
18
VO = 1VPP
15
15
VO = 2VPP
Gain (dB)
VO = 4VPP
12
VO = 7VPP
9
VO = 1VPP
G = -6
6
VO = 2VPP
VO = 4VPP
12
VO = 7VPP
9
6
See Figure 47
See Figure 49
3
3
1M
10M
100M
1M
1G
Frequency (Hz)
10M
100M
1G
Frequency (Hz)
G003
Figure 3.
Figure 4.
VH–LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
VL–LIMITER SMALL-SIGNAL
FREQUENCY RESPONSE
G004
3
3
VO = 0.02VPP
VO = 0.02VPP
0
Limiter Gain (dB)
0
Limiter Gain (dB)
100M
Figure 1.
G = +6
0.02VPP + 2.0VDC
-3
10M
Frequency (Hz)
18
Gain (dB)
See Figure 49
0.7VDC 125Ω
VH
VO
OPA699
VL
-3
VH
VO
OPA699
VL
0.02VPP + 2.0VDC
-6
Open
-6
Open
0.7VDC 125Ω
150Ω 750Ω
150Ω 750Ω
-9
-9
1M
10M
100M
Frequency (Hz)
1M
1G
G005
Figure 5.
10M
100M
Frequency (Hz)
1G
G006
Figure 6.
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
0.4
2.5
VO = 0.5VPP
VO = 4VPP
VH = -VL = 2.5V
2.0
0.3
1.5
0.2
1.0
VOUT (V)
VOUT (V)
0.1
0
-0.1
0.5
0
-0.5
-1.0
-0.2
-1.5
-0.3
-2.0
See Figure 47
-0.4
See Figure 47
-2.5
Time (5ns/div)
Time (5ns/div)
G007
G008
Figure 7.
Figure 8.
VH–LIMITED PULSE RESPONSE
VL–LIMITED PULSE RESPONSE
2.5
2.5
VOUT
1.5
1.0
VIN
0.5
0
-0.5
-1.0
-1.5
-2.0
G=+6
VL = −2V
VIN = 0→−0.7V
2.0
Input and Output Voltage (V)
Input and Output Voltage (V)
2.0
G = +6
VH = +2V
VIN = 0 → 0.7V
1.5
1.0
0.5
0
VIN
−0.5
−1.0
−1.5
VOUT
−2.0
−2.5
-2.5
Time (5ns/div)
Time (5ns/div)
G010
G009
Figure 9.
Figure 10.
LIMITED OUTPUT RESPONSES
DETAIL OF LIMITED OUTPUT RESPONSE
2.10
2.5
G = +6
VH = 2V
VL = -2V
1.5
2.05
2.00
Output Voltage (V)
Input and Output Voltage (V)
2.0
1.0
0.5
0
VIN
-0.5
-1.0
-1.5
-2.0
VOUT
1.95
1.90
1.85
1.80
1.75
1.70
VOUT
1.65
1.60
-2.5
Time (50ns/div)
Time (200ns/div)
G012
G011
Figure 11.
8
Figure 12.
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
HARMONIC DISTORTION
vs
LOAD RESISTANCE
5 MHz HARMONIC DISTORTION
vs
SUPPLY VOLTAGE
-60
-55
2nd-Harmonic
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-60
-65
-70
-75
3rd-Harmonic
-80
-85
-70
-75
-80
3rd-Harmonic
-85
-90
1k
100
Load Resistance (Ω)
2.5
G013
5.0
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
-55
2nd-Harmonic
Harmonic Distortion (dBc)
-70
-75
-80
-85
-90
3rd-Harmonic
-105
1
10
Frequency (MHz)
5.5
6.0
G014
RL = 500Ω
VH = -VL = VOPP /2 + 0.5V
f = 5MHz
-60
2nd-Harmonic
-65
-70
3rd-Harmonic
-75
-80
-85
See Figure 47
See Figure 47
0.5
4.5
HARMONIC DISTORTION
vs
FREQUENCY
-65
-100
4.0
Figure 14.
-50
-95
3.5
Figure 13.
VO = 2VPP
RL = 500Ω
-60
3.0
± Supply Voltage (V)
-55
Harmonic Distortion (dBc)
-65
See Figure 47
See Figure 47
-90
VO = 2VPP
RL = 500Ω
2nd-Harmonic
VO = 2VPP
f = 5MHz
-90
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
20
G015
Figure 15.
Output Voltage (VPP)
G016
Figure 16.
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
HARMONIC DISTORTION
vs
NONINVERTING GAIN
-60
Harmonic Distortion (dBc)
-55
VO = 2VPP
RL = 500Ω
f = 5MHz
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
-90
-95
-90
4
8
12
20
16
Gain (V/V)
-4
-8
-12
-20
-16
Gain (V/V)
G017
G018
Figure 17.
Figure 18.
HARMONIC DISTORTION NEAR
LIMITING VOLTAGES
2-TONE, 3rd-ORDER
INTERMODULATION INTERCEPT
-40
38
VO = 0VDC ± 1VP
f = 5MHz
RL = 500Ω
-50
G = +6V/V
36
Intercept Point (+dBm)
Harmonic Distortion (dBc)
VO = 2VPP
RL = 500Ω
f = 5MHz
-60
Harmonic Distortion (dBc)
-55
HARMONIC DISTORTION
vs
INVERTING GAIN
-60
2nd-Harmonic
-70
3rd-Harmonic
-80
34
32
Open
PI
30
VH
PO
OPA699
28
500Ω
VL
Open
26
24
150Ω
750Ω
22
-90
20
0.9 1.0 1.1
1.2
1.3 1.4
1.5
1.6
± Limit Voltage (V)
1.7 1.8 1.9
0
2.0
G019
Figure 19.
10
10
20
30
Frequency (MHz)
Figure 20.
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50
G020
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
RECOMMENDED R8
vs
CAPACITIVE LOAD
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
140
18
Gain to Capacitive Load (dB)
Resistance (Ω)
120
100
80
60
40
20
CL = Open
15
CL = 10pF
CL = 1000pF
12
VO = 0.5VPP
G = +6
9
CL = 100pF
VIN
RS
6
OPA699
CL
1kΩ(1)
750Ω
3
150Ω
Note: (1) 1kΩ(1) is optional.
0
0
10
100
1000
Capacitive Load (pF)
1M
100M
1G
Frequency (Hz)
G021
G022
Figure 21.
Figure 22.
INPUT VOLTAGE AND
CURRENT NOISE DENSITY
OPEN-LOOP GAIN AND PHASE
100
70
0
Gain
60
Open-Loop Gain (dB)
Voltage Noise Density (nV/√Hz)
Current Noise Density (pA/√Hz)
10M
10
Voltage Noise (4.1nV/√Hz)
Current Noise (2pA/√Hz)
-30
VO = 0.5VPP
50
-60
40
-90
30
-120
Phase
20
-150
10
-180
0
-210
-10
1
100
1k
10k
100k
Frequency (Hz)
1M
10M
Open-Loop Phase (°)
1
-240
10k
100k
1M
10M
Frequency (Hz)
G023
Figure 23.
100M
1G
G024
Figure 24.
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
VOLTAGE RANGES
vs
TEMPERATURE
LIMITED VOLTAGE RANGE
vs
TEMPERATURE
4.0
5.0
VH and VL left open
Internal Default Limited Voltage
3.9
3.8
4.5
VH
3.7
Voltage (V)
±Voltage Ranges (V)
VH = -VL = 4.3V
Output Voltage Range
4.0
3.6
VL
3.5
3.4
3.3
3.5
3.2
Common-Mode Input Range
3.1
3.0
3.0
-50
-25
0
25
50
100
75
Ambient Temperature (°C)
-50
25
50
75
100
G026
Figure 25.
Figure 26.
LIMITED INPUT BIAS CURRENT
vs
BIAS VOLTAGE
SUPPLY AND OUTPUT CURRENTS
vs
TEMPERATURE
20
100
Output Current, Sinking
75
18
Supply Current (mA)
Minimum Over Temperature
25
0
-25
-50
Limiter Headroom = +VS - VH
= VL - (-VS)
Current = IVH or -IVL
-75
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Limiter Headroom (V)
4.0
4.5
98
Output Current, Sourcing
16
96
Supply Current
14
94
12
92
10
-50
5.0
Output Currents (mA)
Maximum Over Temperature
50
-100
-25
0
25
50
Ambient Temperature (°C)
G027
Figure 27.
12
0
Ambient Temperature (°C)
100
Limiter Input Bias Current (µA)
-25
G025
Figure 28.
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90
100
G028
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
TYPICAL DRIFT OVER TEMPERATURE
80
-PSRR
CMRR
60
Input Bias Current (∝A)
CMRR and PSRR (dB)
70
+PSRR
50
40
30
20
4.5
1
4.0
0.9
3.5
0.8
3.0
2.5
0.5
1.5
0.5
0
Frequency (Hz)
0
−25
0
25
50
75
100
Ambient Temperature (C)
G030
G029
Figure 29.
Figure 30.
LIMITER FEEDTHROUGH
CLOSSED-LOOP OUTPUT IMPEDANCE
-45
100
G = +4
VO = 0.5VPP
-50
-60
Output Impedance (Ω)
-55
Feedthrough (dB)
0.2
0.1
100M
10M
0.3
Input Offset Current (I OS)
−0.5
−50
1M
0.4
Input Offset Voltage (V OS)
1.0
0
100k
0.6
2.0
10
10k
0.7
Input Bias Current (I B)
InputOffset
OffsetVoltage
Voltage(mV)
(mA)
Input
Input
InputOffset
OffsetCurrent
Current(µA)
(∝A)
CMRR AND POWER-SUPPLY REJECTION
vs
FREQUENCY
0.02VPP + 2VDC
-65
125Ω
VH
VO
-70
OPA699
-75
VL
-80
Open
-85
150Ω
10
1
0.1
750Ω
-90
0.01
-95
1
10
Frequency (MHz)
100
1M
G031
Figure 31.
10M
100M
Frequency (Hz)
1G
G032
Figure 32.
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TYPICAL CHARACTERISTICS: VS = ±5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω, VH = –VL = 2 V, unless otherwise noted
CMRR AND PSRR(±)
vs
TEMPERATURE
OUTPUT VOLTAGE AND
CURRENT LIMITATIONS
100
5
90
VH = -VL = 4.3V
1W Internal
Power Limit
3
Output Voltage (V)
CMRR and PSRR (dB)
4
+PSRR
80
70
-PSRR
60
2
1
0
RL = 25Ω
-1
RL = 50Ω
-2
RL = 100Ω
-3
CMRR
-50
-25
0
1W Internal
Power Limit
-4
50
25
50
75
-5
-400
100
Ambient Temperature (°C)
-300
-200
-100
0
100
200
300
400
Output Current (mA)
G033
Figure 33.
G034
Figure 34.
TYPICAL CHARACTERISTICS VS = +5 V
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω to VCM = +2.5 V, VL = VCM– 1.2 V, VH = VCM + 1.2 V, unless otherwise noted
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
9
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
6
VO = 0.5VPP
3
3
Normalized Gain (dB)
Normalized Gain (dB)
6
G = +6
0
-3
-6
G = +20
-9
G = +12
0
G = -6
-3
G = -12
-6
-9
-12
-12
See Figure 49
See Figure 48
-15
-15
1M
10M
100M
Frequency (Hz)
1G
1M
G035
Figure 35.
14
G = -4
VO = 0.5VPP
G = +4
10M
100M
Frequency (Hz)
Figure 36.
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TYPICAL CHARACTERISTICS VS = +5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω to VCM = +2.5 V, VL = VCM– 1.2 V, VH = VCM + 1.2 V, unless otherwise noted
LARGE-SIGNAL FREQUENCY RESPONSE
18
0.4
VO = 1VPP,
VLIM = VCM
±1.2V
15
G = +6
0.3
VO = 3VPP,
VLIM = VCM ±1.2V
12
0.2
0.1
VO = 2VPP,
VLIM = VCM ±1.5V
9
VOUT (V)
Gain (dB)
SMALL-SIGNAL PULSE RESPONSE
6
VLIM = VH = −VL
0
-0.1
-0.2
3
-0.3
See Figure 48
See Figure 48
0
-0.4
0.1
10M
100M
1G
Frequency (Hz)
Time (5ns/div)
G037
G038
Figure 37.
Figure 38.
LARGE-SIGNAL PULSE RESPONSE
VH AND VL– LIMITED PULSE RESPONSE
2.5
1.5
G = +6
2.0
Input and Output Voltage (V)
1.0
VOUT (V)
0.5
0
-0.5
-1.0
VOUT
1.5
1.0
0.5
VIN
0
-0.5
-1.0
-1.5
-2.0
See Figure 48
-1.5
-2.5
Time (20ns/div)
Time (5ns/div)
G040
G039
Figure 40.
HARMONIC DISTORTION
vs
LOAD RESISTANCE
HARMONIC DISTORTION
vs
FREQUENCY
-50
VO = 2VPP
f = 5MHz
VO = 2VPP
RL = 500Ω
-55
-55
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-50
Figure 39.
2nd-Harmonic
-60
-65
3rd-Harmonic
-70
-75
-60
2nd-Harmonic
-65
-70
-75
3rd-Harmonic
-80
-85
See Figure 48
See Figure 48
-80
-90
1k
100
Load Resistance (Ω)
0.5
G041
Figure 41.
1
10
Frequency (MHz)
20
G042
Figure 42.
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TYPICAL CHARACTERISTICS VS = +5 V (continued)
TA = 25°C, G = +6, RF = 750 Ω, and RL = 500 Ω to VCM = +2.5 V, VL = VCM– 1.2 V, VH = VCM + 1.2 V, unless otherwise noted
2-TONE, 3rd-ORDER
INTERMODULATION INTERCEPT
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
-60
38
36
-65
Intercept Point (+dBM)
Harmonic Distortion (dBc)
2nd-Harmonic
-70
3rd-Harmonic
-75
RL = 500Ω to VS/2
f = 5MHz
VH = VCM + VOPP/2 + 0.5V
VL = VCM + VOPP/2 + 0.5V
-80
See Figure 48
32
Open
30
PI
VH
PO
28
OPA699
26
VL
Open
500Ω
24
750Ω
150Ω
22
20
-85
0.5
1.0
1.5
0
2.5
2.0
Output Voltage Swing (VPP)
20
30
G043
LIMITER INPUT BIAS CURRENT
vs
BIAS VOLTAGE
100
Limiter Input Bias Current (µA)
-50
-55
-60
2nd-Harmonic
-65
-70
3rd-Harmonic
-75
75
Maximum Over Temperature
50
25
Minimum
Over Temperature
0
-25
-50
Limiter Headroom = +VS - VH
= VL - (-VS)
Current = IVH or -IVL
-75
-100
-80
1.0
1.1
1.2
1.3
1.4
1.5
Limit Voltages - 2.5V
1.6
1.7
50
G044
HARMONIC DISTORTION
NEAR LIMITING VOLTAGES
VO = VCM ±1VP
f = 5MHz
RL = 500Ω
0.9
40
Frequency (MHz)
Figure 44.
-45
1.8
0
G045
Figure 45.
16
10
Figure 43.
-40
Harmonic Distortion (dBc)
34
0.5
1.0
1.5
Limiter Headroom (V)
Figure 46.
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APPLICATION INFORMATION
DUAL-SUPPLY, NON-INVERTING AMPLIFIER
The OPA699 is a +4 V/V minimum gain voltage-feedback amplifier that combines features of a wideband, high
slew rate amplifier with output voltage limiters. Its output can swing up to 1 V from each rail and can deliver up to
120 mA. These capabilities make it an ideal interface to drive an ADC while adding overdrive protection for the
ADC inputs.
Figure 47 shows the ac-coupled, gain of +6 V/V, dual power-supply circuit configuration used as the basis of the
±5-V Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50 Ω
with a resistor to ground and the output is set to 500 Ω. Voltage swings reported in the specifications are taken
directly at the input and output pins. For the circuit of Figure 47, the total output load will be 500 Ω || 900 Ω =
321 Ω. The voltage limiting pins are set to ±2 V through a voltage divider network between +VS and ground for
VH and between –VS and ground for VL. These limiter voltages are adequately bypassed with a 0.1-µF ceramic
capacitor to ground. The limiter voltages (VH and VL) and the respective bias currents (IVH and IVL) have the
polarities shown. One additional component is included in Figure 47. An additional resistor (100 Ω) is included in
series with the noninverting input. Combined with the 25-Ω dc source resistance looking back towards the signal
generator, this gives an input bias current-canceling resistance that matches the 125-Ω source resistance seen
at the inverting input (see the dc accuracy and offset control section). The power-supply bypass for each supply
consists of two capacitors: one electrolytic 2.2 µF and one ceramic 0.1 µF. The power-supply bypass capacitors
are shown explicitly in Figure 47 and Figure 48, but will be assumed in the other figures. An additional 0.01-µF
power-supply decoupling capacitor (not shown here) can be included between the two power-supply pins. In
practical PC board layouts, this optional, added capacitor typically improves the 2nd harmonic distortion
performance by 3 dB to 6 dB.
3.01kΩ
1.91kΩ
+VS = +5V
+
2.2µF
0.1µF
0.1µF
VH = +2V
100Ω
7
3
VIN
8
49.9Ω
OPA699
2
RG
150Ω
RF
750Ω
0.1µF
5
IVH
6
IVL
VO
500Ω
4
0.1µF
VL = -2V
+
2.2µF
3.01kΩ
1.91kΩ
-VS = -5V
S0035-02
Figure 47. DC-Coupled, Dual Supply Amplifier
SINGLE-SUPPLY, NON-INVERTING AMPLIFIER
Figure 48 shows an ac-coupled, noninverting gain amplifier for single +5-V supply operation. This circuit was
used for ac characterization of the OPA699, with a 50-Ω source (which it matches) and a 500-Ω load. The
mid-point reference on the noninverting input is set by two 1.5-kΩ resistors. This gives an input bias
current-canceling resistance that matches the 750-Ω dc source resistance seen at the inverting input (see the dc
accuracy and offset control section). The power-supply bypass for the supply consists of two capacitors: one
electrolytic 2.2 µF and one ceramic 0.1 µF. The power-supply bypass capacitors are shown explicitly in Figure 47
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APPLICATION INFORMATION (continued)
and Figure 48, but will be assumed in the other figures. The limiter voltages (VH and VL) and the respective bias
currents (IVH and IVL) have the polarities shown. These limiter voltages are adequately bypassed with a 0.1-µF
ceramic capacitor to ground. Notice that the single-supply circuit can use three resistors to set VH and VL, where
the dual-supply circuit usually uses four to reference the limit voltages to ground. While this circuit shows +5-V
operation, the same circuit may be used for single supplies up to +12 V.
VS = +5V
+
0.1µF
2.2µF
523Ω
0.1µF
VH = 3.7V
1.5kΩ
0.1µF
3
IVH
7
VIN
8
53.6Ω
1.5kΩ
0.1µF
6
OPA699
2
976Ω
VO
5
500Ω
IVL
4
RF
750Ω
0.1µF
RG
150Ω
VL = 1.3V
523Ω
0.1µF
S0036-02
Figure 48. AC-Coupled, Single Supply Amplifier
WIDEBAND INVERTING OPERATION
Operating the OPA699 as an inverting amplifier has several benefits and is particularly useful when a matched
50-Ω source and input impedance are required. Figure 49 shows the inverting gain of –4 V/V circuit used as the
basis of the inverting mode typical characteristics.
+5V
0.1µF
RT
169Ω
+2V
VH
OPA699
VO
VL
500Ω
-5V
50Ω Source
RG
187Ω
-2V
RF
750Ω
VI
RM
68.1Ω
S0037-02
Figure 49. Inverting G = –4 Specifications and Test Circuit
In the inverting case, only the feedback resistor appears as part of the total output load in parallel with the actual
load. For a 500-Ω load used in the typical characteristics, this gives a total load of 329 Ω in this inverting
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APPLICATION INFORMATION (continued)
configuration. The gain resistor is set to get the desired gain (in this case, 187 Ω for a gain of –4) while an
additional input resistor (RM) can be used to set the total input impedance equal to the source, if desired. In this
case, RM = 68.1 Ω in parallel with the 187-Ω gain setting resistor gives a matched input impedance of 50 Ω. This
matching is only needed when the input needs to be matched to a source impedance, as in the characterization
testing done using the circuit of Figure 49.
For bias current-cancellation matching, the noninverting input requires a 169-Ω resistor to ground. The
calculation for this resistor includes a dc-coupled 50-Ω source impedance along with RG and RM. Although this
resistor provides cancellation for the bias current, it must be well-decoupled (0.1 µF in Figure 49) to filter the
noise contribution of the resistor and the input current noise.
As the required RG resistor approaches 50 Ω at higher gains, the bandwidth for the circuit in Figure 49 far
exceeds the bandwidth at that same gain magnitude for the noninverting circuit of Figure 47. This occurs due to
the lower noise gain for the circuit of Figure 49 when the 50-Ω source impedance is included in the analysis. For
instance, at a signal gain of –15 (RG = 50 Ω, RM = open, RF = 750 Ω) the noise gain for the circuit of Figure 49
will be 1 + 750 Ω/(50 Ω + 50 Ω) = 8.5 due to the addition of the 50-Ω source in the noise gain equation. This
approach gives considerably higher bandwidth than the noninverting gain of +15. Using the 1-GHz gain
bandwidth product for the OPA699, an inverting gain of –15 from a 50-Ω source to a 50-Ω RG gives 140-MHz
bandwidth, whereas the noninverting gain of +6 gives 55 MHz, as shown in the measured results of Figure 50.
24
G = -15
Gain (dB)
21
18
G = +15
15
12
9
1M
10M
100M
Frequency (Hz)
1G
G047
Figure 50. G = +15 and -15 Frequency Response
LOW-GAIN COMPENSATION FOR IMPROVED SFDR
Where a low gain is desired and inverting operation is acceptable, a new external compensation technique can
be used to retain the full slew rate and noise benefits of the OPA699, while giving increased loop gain and the
associated distortion improvements offered by a non-unity-gain stable op amp. This technique shapes the loop
gain for good stability, while giving an easily controlled 2nd-order low-pass frequency response. To set the
compensation capacitors (CS and CF), consider the half-circuit of Figure 51, where the 50-Ω source is used.
Considering only the noise gain for the circuit of Figure 51, the low-frequency noise gain (NG1) is set by the
resistor ratio, while the high-frequency noise gain (NG2) is set by the capacitor ratio. The capacitor values set
both the transition frequencies and the high-frequency noise gain. If the high-frequency noise gain, determined
by NG2 = 1 + CS/CF, is set to a value greater than the recommended minimum stable gain for the op amp, and
the noise gain pole (set by 1/RFCF) is placed correctly, a well controlled 2nd-order low-pass frequency response
results.
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APPLICATION INFORMATION (continued)
+5V
VH
200Ω
OPA699
VO
VL
RG
402Ω
RF
402Ω
VI
CS
13pF
CF
2.8pF
-5V
S0052-01
Figure 51. Broadband, Low-Inverting Gain External Compensation
To choose the values for both CS and CF, two parameters and only three equations need to be solved. The first
parameter is the target high-frequency noise gain (NG2), which should be greater than the minimum stable gain
for the OPA699. Here, a target of NG2 = 26 is used. The second parameter is the desired low-frequency signal
gain, which also sets the low-frequency noise gain (NG1). To simplify this discussion, we target a maximally flat
2nd-order low-pass Butterworth frequency response (Q = 0.707). The signal gain shown in Figure 51 sets the
low-frequency noise gain to NG1 = 1 + RF/RG (= 2 in this example). Then, using only these two gains and the gain
bandwidth product for the OPA699 (1000 MHz), the key frequency in the compensation is set by Equation 1.
Z
GBP2
O
NG 1
N
1 G1
N
G2
N
G2 N
12
G1
(1)
Physically, this ZO (22.3 MHz for the values shown above) is set by 1/[2πRF(CF + CS)] and is the frequency at
which the rising portion of the noise gain would intersect the unity gain if projected back to a 0 dB gain. The
actual zero in the noise gain occurs at NG1 × ZO and the pole in the noise gain occurs at NG2 × ZO. That pole is
physically set by 1/(RFCF). Since GBP is expressed in Hz, multiply ZO by 2π and use to get CF by solving
Equation 2.
1
C ( 3 pF)
F
2R Z N
F O G2
(2)
Finally, since CS and CF set the high-frequency noise gain, determine CS using Equation 3 (solving for CS by
using NG2 = 6):
C N
1 C
S
G2
F
(3)
which gives CS = 15 pF.
Both of these calculated values have been reduced slightly in Figure 51 to account for parasitics. The resulting
closed-loop bandwidth is approximately equal to Equation 4.
f
3dB
ZO GBP
(4)
For the values shown in Figure 51, f–3 dB is approximately 149 MHz. This is less than that predicted by simply
dividing the GBP product by NG1. The compensation network controls the bandwidth to a lower value, while
providing the full slew rate at the output and an improved distortion performance due to increased loop gain at
frequencies below NG1 × ZO.
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APPLICATION INFORMATION (continued)
LOW DISTORTION, LIMITED OUTPUT, ADC INPUT DRIVER
Figure 52 shows a simple ADC driver that operates on a single supply, and gives excellent distortion
performance. The limit voltages track the input range of the converter, completely protecting against input
overdrive. Note that the limiting voltages have been set 100 mV above/below the corresponding reference
voltage from the converter. This circuit also implements an improved distortion for an inverting gain of –2 using
external compensation.
VS = +5V
562Ω
VH = +3.6V
0.1µF
1.4kΩ
VS = +5V
102Ω
+3.5V
VS = +5V
RSEL
REFT
0.1µF
3
7
8
OPA699
6
24.9Ω
5
2
1.4kΩ
ADS822
10-Bit
40MSPS
IN
100pF
750Ω
INT/EXT GND
+1.5V
VIN
18pF
10-Bit
Data
4
REFB
1000pF 374Ω
+VS
102Ω
4pF
VL = +1.4V
0.1µF
562Ω
S0038-02
Figure 52. Single Supply, Limiting ADC Input Driver
LIMITED OUTPUT, DIFFERENTIAL ADC INPUT DRIVER
Figure 53 shows a differential ADC driver that takes advantage of the OPA699 limiters to protect the input of the
ADC. Two OPA699s are used. The first one is an inverting configuration at a gain of –2. The second one is in a
noninverting configuration at a gain of +2. See the Low Gain Compensation for Improved SFDR section for a
discussion of stability issues of the OPA699 operating at a gain less than four. Each amplifier is swinging 2 VPP
providing a 4-VPP differential signal to drive the input of the ADC. Limiters have been set 100 mV away from the
magnitude of each amplifier maximum signal to provide input protection for the ADC, while maintaining an
acceptable distortion level.
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SGLS289A – MAY 2005 – REVISED MARCH 2006
APPLICATION INFORMATION (continued)
+5V
+1.1V
OPA699
-1.1V
-5V
1kΩ
100Ω
10pF
24.9Ω 0.01µF
IN
1kΩ
+5V
VCM
4VPP
+1.1V
VIN = 200mVPP
ADC
24.9Ω 0.01µF
1kΩ
IN
OPA699
100Ω
10pF
-1.1V
-5V
900Ω
100Ω
S0040-02
Figure 53. Single to Differential AC-Coupled, High Gain Output Limited ADC Driver
PRECISION HALF-WAVE RECTIFIER
Figure 54 shows a half-wave rectifier with outstanding precision and speed. VH (pin 8) defaults to 3.5 V typically if
left open, while the negative limit is set to ground.
The gain for the circuit in Figure 54 is set at +6. Figure 55 shows input and output for ±0.5 V 100-MHz input.
+VS = +5V
50Ω
Source
75Ω
2
7
VO = Open
VIN
8
OPA699
6
VO
5
3
4
150Ω
750Ω
-VS = -5V
S0039-02
Figure 54. Precision Half-Wave Rectifier
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APPLICATION INFORMATION (continued)
3.5
Output
Input and Output Voltage (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.5
Input
-1.0
Time (5ns/div)
G048
Figure 55. 100-MHz Sinewave Rectified
HIGH-SPEED Schmitt TRIGGER
Figure 56 shows a high-speed Schmitt Trigger. The output levels are precisely defined and the switching time is
exceptional. The output voltage swings between VH and VL.
R2
402Ω
R1
200Ω
+2V
VREF
R3
200Ω
VH
OPA699
VOUT
VL
VIN
-2V
S0044-02
Figure 56. High-Speed Schmitt Trigger
The circuit operates as follows. When the input voltage is less than VHL then the output is limiting at VH. When
the input is greater than VHH, then the output is limiting at VL, with VHL and VHH defined as in Equation 5.
V
HL,HH
R1 R2 R3
R1 R2 R3
V
V
ref
OUT
R1
R2
(5)
Due to the inverting function realized by the Schmitt Trigger, VHL corresponds to VOUT = VH, and VHH corresponds
to VOUT = VL.
Figure 57 shows the Schmitt Trigger operating with VREF = +5 V. This gives us VHH = 2.4 V and VHL = 1.6 V. The
propagation delay for the OPA699 in a Schmitt Trigger configuration is 4 ns from high-to-low and 4 ns from
low-to-high.
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APPLICATION INFORMATION (continued)
Input and Output Voltage (V)
4
3
2
1
0
VOUT
-1
VIN
-2
-3
-4
Time (10ns/div)
G049
Figure 57. Schmitt Trigger Time Domain Response for a 10-MHz Sinewave
DESIGN-IN TOOLS
Applications Support
The Texas Instruments Applications Department is available for design assistance at 1-972-644-5580. The Texas
Instruments web site (www.ti.com) has the latest product data sheets and other design tools.
Demonstration Boards
A PC board is available to assist in the initial evaluation of circuit performance of the OPA699ID. It is available as
an unpopulated PCB with descriptive documentation, and can be requested through the Texas Instruments web
site. See the demonstration board literature for more information. The summary information for this board is
shown in Table 1.
Table 1. Evaluation Module Ordering Information
PRODUCT
PACKAGE
BOARD PART NUMBER
LITERATURE NUMBER
OPA699ID
SO-8
DEM-OPA-SO-1A
SBOU009
OPERATING SUGGESTIONS
Theory of Operation
The OPA699 is a voltage-feedback, gain of +4 V/V stable op amp. The output voltage is limited to a range set by
the voltage on the limiter pins (5 and 8). When the input tries to overdrive the output, the limiters take control of
the output buffer. This action from the limiters avoids saturating any part of the signal path, giving quick overdrive
recovery and excellent limiter accuracy at any signal gain. The limiters have a sharp transition from the linear
region of operation to output limiting. This transition allows the limiter voltages to be set near (< 100 mV) the
desired signal range. The distortion performance is also good near the limiter voltages.
Output Limiters
The output voltage is linearly dependent on the input(s) when it is between the limiter voltages VH (pin 8) and VL
(pin 5). When the output tries to exceed VH or VL, the corresponding limiter buffer takes control of the output
voltage and holds it at VH or VL. Because the limiters act on the output, their accuracy does not change with the
gain. The transition from the linear region of operation to output limiting is sharp—the desired output signal can
safely come to within 30 mV of VH or VL with no onset of non-linearity. The limiter voltages can be set to within
0.7 V of the supplies (VL = –VS + 0.7 V, VH = +VS– 0.7 V). They must also be at least 400 mV apart (VH– VL =
0.4 V). When pins 5 and 8 are left open, VH and VL go to the default voltage limit; the minimum values are given
in the electrical specifications. Looking at Figure 58 for the zero bias current case shows the expected range of
(VS– default limit voltages) = headroom.
24
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Limiter Input Bias Current (µA)
100
75
Maximum Over Temperature
50
Minimum Over Temperature
25
0
-25
-50
Limiter Headroom = +VS - VH
= VL - (-VS)
Current = IVH or -IVL
-75
-100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Limiter Headroom (V)
G027
Figure 58. Limit Bias Current vs Bias Voltage
When the limiter voltages are more than 2.1 V from the supplies (VL = –VS + 2.1 V or VH = +VS– 2.1 V), you can
use simple resistor dividers to set VH and VL (see Figure 47). Make sure to include the limiter input bias currents
(see Figure 54) in the calculations (that is, IVL = 50 µA into pin 5, and IVH = +50 µA out of pin 8). For good limiter
voltage accuracy, run a minimum 1-mA quiescent bias current through these resistors. When the limiter voltages
need to be within 2.1 V of the supplies (VL = –VS + 2.1 V or VH = +VS– 2.1 V), consider using low impedance
buffers to set VH and VL to minimize errors due to bias current uncertainty. This condition typically is the case for
single-supply operation (VS = +5 V). Figure 48 runs 2.5 mA through the resistive divider that sets VH and VL. This
limits errors due to IVH and IVL < ±1% of the target limit voltages. The limiters' dc accuracy depends on attention
to detail. The two dominant error sources can be improved as follows:
• Power supplies, when used to drive resistive dividers that set VH and VL, can contribute large errors (for
example, ±5%). Using a more accurate source and bypassing pins 5 and 8 with good capacitors, improves
limiter PSRR.
• The resistor tolerances in the resistive divider can also dominate. Use 1% resistors. Other error sources also
contribute, but should have little impact on the limiters' dc accuracy.
• Reduce offsets caused by the limiter input bias currents. Select the resistors in the resistive divider(s) as
described above.
• Consider the signal path dc errors as contributing to uncertainty in the useable output swing.
• The limiter offset voltage only slightly degrades limiter accuracy. Figure 59 shows how the limiters affect
distortion performance. Virtually no degradation in linearity is observed for output voltage swinging right up to
the limiter voltages. In this plot a fixed ±1-V output swing is driven while the limiter voltages are reduced
symmetrically. Until the limiters are reduced to ±1.1 V, little distortion degradation is observed.
Harmonic Distortion (dBc)
-40
VO = 0VDC ± 1VP
f = 5MHz
RL = 500Ω
-50
-60
2nd-Harmonic
-70
3rd-Harmonic
-80
-90
0.9 1.0 1.1
1.2
1.3 1.4
1.5
1.6
1.7 1.8 1.9
± Limit Voltage (V)
2.0
G019
Figure 59. Harmonic Distortion Near Limit Voltages
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Output Drive
The OPA699 has been optimized to drive 500-Ω loads, such as ADCs. It still performs well driving 100-Ω loads;
the specifications are shown for the 500-Ω load. This makes the OPA699 an ideal choice for a wide range of
high-frequency applications.
Many high-speed applications, such as driving ADCs, require op amps with low output impedance. As shown in
the typical performance curve Output Impedance vs Frequency, the OPA699 maintains low closed-loop output
impedance over frequency. Closed-loop output impedance increases with frequency, since loop gain decreases
with frequency.
Thermal Considerations
The OPA699 does not require heat sinking under most operating conditions. Maximum desired junction
temperature sets a maximum allowed internal power dissipation as described below. In no case should the
maximum junction temperature be allowed to exceed 150°C.
The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and the additional power dissipated
in the output stage (PDL), while delivering load power. PDQ is simply the specified no-load supply current times
the total supply voltage across the part. PDL depends on the required output signals and loads. For a grounded
resistive load, and equal bipolar supplies, it is at maximum when the output is at 1/2 either supply voltage. In this
condition, PDL = VS2/(4RL) where RL includes the feedback network loading. Note that it is the power in the output
stage and not in the load, that determines internal power dissipation.
The operating junction temperature is: TJ = TA + PD × θJA, where TA is the ambient temperature. For example, the
maximum TJ for a OPA699ID with G = +6, RF = 750 Ω, RL = 500 Ω, and ±VS = ±5 V at the maximum TA = 85°C
is calculated as:
P
(10 V 15.5 mA) 155 mW
DQ
(5V)2
P
19.4 mW
DL
4 (500 900 )
P
D
155 mW 19.4 mW 174.4 mW
T 85oC 174.4 mW 125 oCW 107 oC
J
(6)
This would be the maximum TJ from VO = ±2.5 VDC. Most applications will be at a lower output stage power and
have a lower TJ. Care must be taken when operating at higher ambient temperatures.
Capacitive Loads
Capacitive loads, such as the input to ADCs, decreases the amplifier phase margin, which may cause
high-frequency peaking or oscillations. Capacitive loads ≥2 pF should be isolated by connecting a small resistor
in series with the output, as shown in Figure 60. Increasing the gain from +2 improves the capacitive drive
capabilities due to increased phase margin.
RG
RF
RS
VO
OPA699
RL
RT
CL
RL is optional
S0048-02
Figure 60. Driving Capacitive Loads
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In general, capacitive loads should be minimized for optimum high-frequency performance. The capacitance of
coax cable (29 pF/ft for RG-58) does not load the amplifier when the coaxial cable or transmission line is
terminated in its characteristic impedance.
Frequency Response Compensation
The OPA699 is internally compensated to be +4 gain stable and has a nominal phase margin of 60° at a gain of
+6. Phase margin and peaking improve at higher gains. Recall that an inverting gain of –5 is equivalent to a gain
of +6 for bandwidth purposes (that is, noise gain = 6). Standard external compensation techniques work with this
device. For example, in the inverting configuration, the bandwidth may be limited without modifying the inverting
gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise
gain at high frequencies, which limits the bandwidth.
For unity-gain stable amplifier applications, the OPA698 is recommended.
In applications where a large feedback resistor is required, such as a photodiode transimpedance amplifier, the
parasitic capacitance from the inverting input to ground causes peaking or oscillations. To compensate for this
effect, connect a small capacitor in parallel with the feedback resistor. The bandwidth is limited by the pole that
the feedback resistor and this capacitor create. In other high-gain applications, use a three-resistor Tee network
to reduce the RC time constants set by the parasitic capacitances.
Pulse Settling Time
The OPA699 is capable of an extremely fast settling time in response to a pulse input. Frequency response
flatness and phase linearity are needed to obtain the best settling times. For capacitive loads, such as an ADC,
use the recommended RS in the typical performance curve Recommended RS vs Capacitive Load. Extremely
fine-scale settling (0.01%) requires close attention to ground return current in the supply decoupling capacitors.
The pulse settling characteristics, when recovering from overdrive, are extremely good as shown in the typical
characteristics.
Distortion
The OPA699's distortion performance is specified for a 500-Ω load, such as an ADC. Driving loads with smaller
resistance increases the distortion as illustrated in Figure 61. Remember to include the feedback network in the
load resistance calculations.
-55
2nd-Harmonic
Harmonic Distortion (dBc)
-60
VO = 2VPP
f = 5MHz
-65
-70
-75
3rd-Harmonic
-80
-85
-90
See Figure 47
1k
100
Load Resistance (Ω)
G013
Figure 61. 5-MHz Harmonic Distortion vs Load Resistance
Noise Performance
High slew rate, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise
voltage. The 4.1-nV/√Hz input voltage noise for the OPA699, however, is much lower than comparable
amplifiers. The input-referred voltage noise and the two input-referred current noise terms, combine to give low
output noise under a wide variety of operating conditions. Figure 62 shows the op amp noise analysis model with
all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms
in either nV/√Hz or pA/√Hz.
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ENI
EO
OPA699
RS
IBN
ERS
RF
4kTRS
4kT
RG
4kTRF
IBI
RG
4kT = 1.6E -20J
at 290 K
S0049-02
Figure 62. Op Amp Noise Analysis Model
The total output spot noise voltage can be computed as the square root of the sum of all squared output noise
voltage contributors. Equation 7 shows the general form for the output noise voltage using the terms shown in
Figure 62.
E
O
E
2
NI
BNRS
2
I
4kTR
S
BIRF
2
NG 2 I
4kTR NG
F
(7)
Dividing this expression by the noise gain [NG = (1+RF/RG)] gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in Equation 8.
E
N
E
2
NI
BNRS
I
2
4kTR S
I R
BI F
NG
2
4kTR
F
NG
(8)
Evaluating these two equations for the OPA699 circuit and component values (see Figure 47) gives a total output
spot noise voltage of 27.4 nV/√Hz and a total equivalent input spot noise voltage of 4.6 nV/√Hz. This total
input-referred spot noise voltage is only slightly higher than the 4.1-nV/√Hz specification for the op amp voltage
noise alone. This is the case as long as the impedances appearing at each op amp input are limited to a
maximum value of 300 Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 300 Ω
satisfies both noise and frequency response flatness considerations. Since the resistor-induced noise is
negligible, additional capacitive decoupling across the bias current cancellation resistor (RT) for the inverting op
amp configuration of Figure 49 is not required, but is still desirable.
DC-Accurracy and Offset Control
The balanced input stage of a wideband voltage feedback op amp allows good output dc accuracy in a large
variety of applications. The power-supply current trim for the OPA699 gives even tighter control than comparable
products. Although the high-speed input stage does require relatively high input bias current (typically 3 µA at
each input terminal), the close matching between them may be used to reduce the output dc error caused by this
current. The total output offset voltage may be considerably reduced by matching the dc source resistances
appearing at the two inputs. This reduces the output dc error due to the input bias currents to the offset current
times the feedback resistor. Evaluating the configuration of Figure 47, using worst-case +25°C input offset
voltage and current specifications, gives a worst-case output offset voltage, with NG = noninverting signal gain,
equal to:
±[NG × VIO(MAX)] ± [RF × IIO(MAX)]
= ±(2 × 8 mV) ± (750 Ω × 3 µA)
= ±18.3 mV
28
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A fine-scale output offset null or dc operating point adjustment, is often required. Numerous techniques are
available for introducing dc-offset control into an op amp circuit. Most of these techniques eventually reduce to
adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is
the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the
offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the
signal path is intended to be inverting, applying the offset control to the noninverting input may be considered.
However, the dc offset voltage on the summing junction sets up a dc current back into the source which must be
considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and
frequency response flatness. For a dc-coupled inverting amplifier, Figure 63 shows one example of an offset
adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting
current is brought into the inverting input node through resistor values that are much larger than the signal path
resistors. This insures that the adjustment circuit has minimal effect on the loop gain as well as the frequency
response.
+5V
Supply Decoupling
Not Shown
0.1µF
328Ω
OPA699
VO
-5V
RG
150Ω
+5V
5kΩ
RF
750Ω
VI
20kΩ
±200mV Output Adjustment
10kΩ
0.1µF
5kΩ
VO
VI
=-
RF
RG
= -5
S0050-02
-5V
Figure 63. DC-Coupled, Inverting Gain of –5, With Offset Adjustment
Board Layout Guidelines
Achieving optimum performance with the high-frequency OPA699 requires careful attention to layout design and
component selection. Recommended PCB layout techniques and component selection criteria are:
1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Open a window in the
ground and power planes around the signal I/O pins, and leave the ground and power planes unbroken
elsewhere.
2. Provide a high quality power supply. Use linear regulators, ground plane and power planes to provide
power. Place high frequency 0.1-µF decoupling capacitors < 0.2" away from each power-supply pin. Use
wide, short traces to connect to these capacitors to the ground and power planes. Also use larger (2.2 µF to
6.8 µF) high-frequency decoupling capacitors to bypass lower frequencies. They may be somewhat further
from the device and be shared among several adjacent devices.
3. Place external components close to the OPA699. This minimizes inductance, ground loops, transmission
line effects and propagation delay problems. Be extra careful with the feedback (RF), input and output
resistors.
4. Use high-frequency components to minimize parasitic elements. Resistors should be a low reactance type.
Surface-mount resistors work best and allow a tighter layout. Metal film or carbon composition axially-leaded
resistors can also provide good performance when their leads are as short as possible. Never use
wirewound resistors for high-frequency applications. Remember that most potentiometers have large
parasitic capacitances and inductances. Multilayer ceramic chip capacitors work best and take up little
space. Monolithic ceramic capacitors also work well. Use RF type capacitors with low ESR and ESL. The
large power pin bypass capacitors (2.2 µF to 6.8 µF) should be tantalum for better high frequency and pulse
performance.
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5. Choose low resistor values to minimize the time constant set by the resistor and its parasitic parallel
capacitance. Good metal film or surface mount resistors have approximately 0.2-pF parasitic parallel
capacitance. For resistors > 1.5 kΩ, this adds a pole and/or zero below 500 MHz. Make sure that the output
loading is not too heavy. The recommended 750-Ω feedback resistor is a good starting point in most
designs.
6. Use short direct traces to other wideband devices on the board. Short traces act as a lumped capacitive
load. Wide traces (50 to 100 mils) should be used. Estimate the total capacitive load at the output and use
the series isolation resistor recommended in the typical performance curve, Recommended RS vs Capacitive
Load. Parasitic loads < 2 pF may not need the isolation resistor.
7. When long traces are necessary, use transmission line design techniques (consult an ECL design
handbook for microstrip and stripline layout techniques). A 50-Ω transmission line is not required on
board—a higher characteristic impedance helps reduce output loading. Use a matching series resistor at the
output of the op amp to drive a transmission line and a matched load resistor at the other end to make the
line appear as a resistor. If the 6 dB of attenuation that the matched load produces is not acceptable, and the
line is not too long, use the series resistor at the source only. This isolates the source from the reactive load
presented by the line, but the frequency response will be degraded. Multiple destination devices are best
handled as separate transmission lines, each with its own series source and shunt load terminations. Any
parasitic impedances acting on the terminating resistors alters the transmission line match and can cause
unwanted signal reflections and reactive loading.
8. Do not use sockets for high-speed parts like the OPA699. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely troublesome parasitic network. Best results are
obtained by soldering the part onto the board.
Power Supplies
The OPA699 is nominally specified for operation using either ±5-V supplies or a single +5-V supply. The
maximum specified total supply voltage of 12 V allows reasonable tolerances on the supplies. Higher supply
voltages can break down internal junctions, possibly leading to catastrophic failure. Single-supply operation is
possible as long as common mode voltage constraints are observed. The common-mode input and output
voltage specifications can be interpreted as required headroom to the supply voltage. Observing this input and
output headroom requirement allows a design of non-standard or single-supply operation circuits. Figure 48
shows one approach to single-supply operation.
input and ESD protection
The OPA699 is built using a high-speed complementary bipolar process. The internal junction breakdown
voltages are relatively low for these small geometry devices. These breakdowns are reflected in the Absolute
Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies,
as shown in Figure 64.
These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection
diodes can typically support 30-mA continuous current. Where higher currents are possible (e.g., in systems with
±15-V supply parts driving into the OPA699), current limiting series resistors should be added into the two inputs.
Keep these resistor values as low as possible, since high values degrade both noise performance and frequency
response.
+V S
External
Pin
Internal
Circuitry
-V S
S0051-01
Figure 64. I/O Pin ESD Protection
30
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
OPA699MJD
ACTIVE
CDIP SB
JD
Pins Package Eco Plan (2)
Qty
8
1
TBD
Lead/Ball Finish
MSL Peak Temp (3)
POST-PLATE N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA699M :
• Catalog: OPA699
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
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TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
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