Freescale Semiconductor Advance Information Document Number: MC33883 Rev 10.0, 10/2012 H-Bridge Gate Driver IC The 33883 is an H-bridge gate driver (also known as a full-bridge pre-driver) IC with integrated charge pump and independent high and low side gate driver channels. The gate driver channels are independently controlled by four separate input pins, thus allowing the device to be optionally configured as two independent high side gate drivers and two independent low side gate drivers. The low side channels are referenced to ground. The high side channels are floating. The gate driver outputs can source and sink up to 1.0 A peak current pulses, permitting large gate-charge MOSFETs to be driven and/or high pulse- width modulation (PWM) frequencies to be utilized. A linear regulator is incorporated, providing a 15 V typical gate supply to the low side gate drivers. 33883 H-BRIDGE GATE DRIVER IC EG SUFFIX (PB-FREE) 98ASB42343B 20-PIN SOICW Features • • • • • • • • • VCC operating voltage range from 5.5 V up to 55 V VCC2 operating voltage range from 5.5 V up to 28 V CMOS / LSTTL compatible I / O 1.0 A peak gate driver current Built-in high side charge pump Under-voltage lockout (UVLO) Over-voltage lockout (OVLO) Global enable with <10 A Sleep mode Supports PWM up to 100 kHz ORDERING INFORMATION Device (Add R2 Suffix for Tape and Reel) Temperature Range (TA) Package MC33883HEG - 40 °C to 125 °C 20 SOICW VBAT VBOOST 33883 VCC CP_OUT VCC2 G_EN LR_OUT C1 C2 MCU GATE_HS1 SRC_HS1 GATE_LS1 GATE_HS2 SRC_HS2 IN_HS1 GATE_LS2 IN_LS1 IN_HS2 /2 IN_LS2 GND_A GND Figure 1. 33883 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2007-2012. All rights reserved. DC Motor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM C2 C1 VCC, VCC2 Undervoltage/Overvoltage VCC2 VCC VCC VDD Charge Pump EN VCC C2 VPOS GND G_EN VCC2 C1 CP_OUT GND2 VCC2 VCC VDD CP_OUT VCC2 +5.0 V EN Linear GND Reg +14.5 V LR_OUT GND_A GND2 HIGH- AND LOW-SIDE CONTROL WITH CHARGE PUMP VCC BRG_EN IN_HS1 TSD1 Control and Logic VDD / VPOS Level Shift BRG_EN TSD1 Control and Logic TSD1 Thermal Shutdown TSD2 VDD / VCC Level Shift IN Output Pulse Generator VDD / VPOS Level Shift TSD2 Control and Logic GND GATE_LS1 CP_OUT IN Output OU Driver TSD2 Thermal Shutdown GATE_HS SRC_HS2 LR_OUT VDD / VCC Level Shift IN Output Pulse Generator OU Driver GATE_LS2 GND2 LOW-SIDE CHANNEL GND SRC_HS1 GND1 Pulse Generator BRG_EN OU Driver VCC HIGH-SIDE CHANNEL IN_LS2 GATE_HS LR_OUT BRG_EN Control and Logic OU Driver LOW-SIDE CHANNEL IN_HS2 CP_OUT IN Output Pulse Generator HIGH-SIDE CHANNEL IN_LS1 LR_OUT GND_ Figure 2. 33883 Simplified Internal Block Diagram 33883 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VCC 1 20 G_EN C2 2 19 CP_OUT SRC_HS1 3 18 4 17 GATE_HS1 IN_HS1 IN_LS1 GATE_LS1 5 16 6 15 SRC_HS2 GATE_HS2 IN_HS2 IN_LS2 GATE_LS2 7 14 8 13 GND1 LR_OUT 9 12 10 11 GND2 C1 GND_A VCC2 Figure 3. 33883 20-SOICW Pin Connections A functional description of each pin can be found in the Functional Pin Description section beginning on page 10. Table 1. 20-SOICW Pin Definitions Pin Pin Name Formal Name Definition 1 VCC Supply Voltage 1 Device power supply 1. 2 C2 Charge Pump Capacitor External capacitor for internal charge pump. 3 CP_OUT Charge Pump Out External reservoir capacitor for internal charge pump. 4 SRC_HS1 Source 1 Output High Side Source of high-side 1 MOSFET 5 GATE_HS 1 Gate 1 Output High Side Gate of high-side 1 MOSFET. 6 IN_HS1 Input High Side 1 Logic input control of high-side 1 gate (i.e., IN_HS1 logic HIGH = GATE_HS1 HIGH). 7 IN_LS1 Input Low Side 1 Logic input control of low-side 1 gate (i.e., IN_LS1 logic HIGH = GATE_LS1 HIGH). 8 GATE_LS1 Gate 1 Output Low Side Gate of low-side 1 MOSFET. 9 GND1 Ground 1 Device ground 1. 10 LR_OUT Linear Regulator Output Output of internal linear regulator. 11 VCC2 Supply Voltage 2 Device power supply 2. 12 GND_A Analog Ground Device analog ground. 13 C1 Charge Pump Capacitor External capacitor for internal charge pump. 14 GND2 Ground 2 Device ground 2. 15 GATE_LS2 Gate 2 Output Low Side Gate of low-side 2 MOSFET. 16 IN_LS2 Input Low Side 2 Logic input control of low-side 2 gate (i.e., IN_LS2 logic HIGH = GATE_LS2 HIGH). 17 IN_HS2 Input High Side 2 Logic input control of high-side 2 gate (i.e., IN_HS2 logic HIGH = GATE_HS2 HIGH). 18 GATE_HS 2 Gate 2 Output High Side Gate of high-side 2 MOSFET. 19 SRC_HS2 Source 2 Output High Side Source of high-side 2 MOSFET. 20 G_EN Global Enable Logic input Enable control of device (i.e., G_EN logic HIGH = Full Operation, G_EN logic LOW = Sleep Mode). 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit Supply Voltage 1 VCC -0.3 to 65 V Supply Voltage 2 (1) VCC2 -0.3 to 35 V Linear Regulator Output Voltage VLR_OUT -0.3 to 18 V High-Side Floating Supply Absolute Voltage VCP_OUT -0.3 to 65 V High-Side Floating Source Voltage VSRC_HS -2.0 to 65 V IS 250 mA VGATE_HS -0.3 to 65 V VGATE_HS VSRC_HS -0.3 to 20 V High-Side Floating Supply Gate Voltage VCP_OUT VGATE_HS -0.3 to 65 V Low-Side Gate Voltage VGATE_LS -0.3 to 17 V VG_EN -0.3 to 35 V Logic Input Voltage VIN -0.3 to 10 V Charge Pump Capacitor Voltage VC1 -0.3 to VLR_OUT V Charge Pump Capacitor Voltage VC2 -0.3 to 65 V ELECTRICAL RATINGS High-Side Source Current from CP_OUT in Switch ON State High-Side Gate Voltage High-Side Gate Source Voltage (2) Wake-Up Voltage ESD Voltage (3) V Human Body Model on All Pins (VCC and VCC2 as Two Power Supplies) VESD1 ±1500 Machine Model VESD2 ±130 Notes 1. VCC2 can sustain load dump pulse of 40 V, 400 ms, 2.0 . 2. 3. In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed as shown in Figure 14. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 33883 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Value Unit PD 1.25 W RJA 100 °C / W TJ -40 to 150 °C TSTG -65 to 150 °C TPPRT Note 5 °C Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ 25°C Thermal Resistance (Junction to Ambient) Operating Junction Temperature Storage Temperature Peak Package Reflow Temperature During Reflow (4), (5) Notes 4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Supply Voltage 1 for Output High-Side Driver and Charge Pump VCC 5.5 – 55 V Supply Voltage 2 for Linear Regulation VCC2 5.5 – 28 V VCP_OUT VCC+4 – VCC + 11 but < 65 V Logic 1 Input Voltage (IN_LS and IN_HS) VIH 2.0 – 10 V Logic 0 Input Voltage (IN_LS and IN_HS) VIL – – 0.8 V Logic 1 Input Current IIN+ OPERATING CONDITIONS High-Side Floating Supply Absolute Voltage LOGIC VIN = 5.0 V Wake-Up Input Voltage (G_EN) VG_EN Wake-Up Input Current (G_EN) IG_EN VG_EN = 14 V Wake-Up Input Current (G_EN) A 200 – 1000 4.5 5.0 VCC2 A – 200 500 – – 1.5 mA IG_EN2 VG_EN = 28 V V LINEAR REGULATOR Linear Regulator VLR_OUT VLR_OUT @ VCC2 from 15 V to 28 V, ILOAD from 0 mA to 20 mA V 12.5 – 16.5 VCC2 - 1.5 – – 4.0 – – VCC = 12 V, ILOAD = 0 mA, CCP_OUT = 1.0 F 7.5 – – VCC = 12 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F 7.0 – – VCC2 = VCC = 5.5 V, ILOAD = 0 mA, CCP_OUT = 1.0 F 2.3 – – VCC2 = VCC = 5.5 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F 1.8 – – 7.5 – – 7.0 – – -2.0 – 2.0 -1.5 – – VLR_OUT @ ILOAD = 20 mA VLR_OUT @ ILOAD = 20 mA, VCC2 =5.5V, VCC 5.5V CHARGE PUMP Charge Pump Output Voltage, Reference to VCC VCP_OUT VCC = 55 V, ILOAD = 0 mA, CCP_OUT = 1.0 F VCC = 55 V, ILOAD = 7.0 mA, CCP_OUT = 1.0 F Peak Current Through Pin C1 Under Rapidly Changing VCC Voltages (see Figure 13, page 17) IC1 Minimum Peak Voltage at Pin C1 Under Rapidly Changing VCC Voltages (see Figure 13, page 17) VC1MIN V A V 33883 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SUPPLY VOLTAGE Quiescent VCC Supply Current A IVCCSLEEP VG_EN = 0 V and VCC = 55 V – – 10 VG_EN = 0 V and VCC = 12 V – – 10 VCC = 55 V and VCC2 = 28 V – 2.2 – VCC = 12 V and VCC2 = 12 V – 0.7 – – – 5.0 Operating VCC Supply Current (6) Additional Operating VCC Supply Current for Each Logic Input Pin Active IVCCOP mA IVCCLOG VCC = 55 V and VCC2 = 28 V (7) Quiescent VCC2 Supply Current mA A IVCC2SLEEP VG_EN = 0 V and VCC = 12 V – – 5.0 VG_EN = 0 V and VCC = 28 V – – 5.0 VCC = 55 V and VCC2 = 28 V – – 12 VCC = 12 V and VCC2 = 12 V – – 9.0 Operating VCC2 Supply Current (6) Additional Operating VCC2 Supply Current for Each Logic Input Pin Active IVCC2OP mA IVCC2LOG mA VCC = 55 V and VCC2 = 28 V (7) – – 5.0 UV 4.0 5.0 5.5 V UV2 4.0 5.0 5.5 V Overvoltage Shutdown VCC OV 57 61 65 V Overvoltage Shutdown VCC2 OV2 29.5 31 35 V – – 22 – – 22 – 100 200 Undervoltage Shutdown VCC Undervoltage Shutdown VCC2 (8) OUTPUT Output Sink Resistance (Turned Off) Output Source Resistance (Turned On) Maximum Voltage (VGATE_HS - VSRC_HS) INH = Logic 1, ISmax = 5.0 mA RDS Icharge HSS = 50 mA, VCP_OUT = 20 V (8) Charge Current of the External High-Side MOSFET Through GATE_HSn Pin (9) RDS Idischarge LSS = 50 mA , VSRC_HS = 0 V (8) ICHARGE HSS mA VMAX V – – 18 Notes 6. Logic input pin inactive (high impedance). 7. 8. 9. High-frequency PWM-ing (» 20 kHz) of the logic inputs will result in greater power dissipation within the device. Care must be taken to remain within the package power handling rating. The device may exhibit predictable behavior between 4.0 V and 5.5 V. See Figure 5, page 12, for a description of charge current. 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V VSUP 18 V, -40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max – 200 300 – 80 180 Unit TIMING CHARACTERISTICS Propagation Delay High Side and Low Side CLOAD = 5.0 nF, Between 50% Input to 50% Output (10) (11) , (see Figure 4) ns tF Turn-Off Fall Time CLOAD = 5.0 nF, 10% to 90% (see Figure 4) ns tR Turn-On Rise Time CLOAD = 5.0 nF, 10% to 90% tPD (10) (10) (11) , (see Figure 4) ns – 80 180 10. CLOAD corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side. 11. Rise time is given by time needed to change the gate from 1.0 V to 10 V (vice versa for fall time). 33883 8 Analog Integrated Circuit Device Data Freescale Semiconductor TIMING DIAGRAMS TIMING DIAGRAMS 50% 50% IN_HS or IN_LS GATE_HS or GATE_LS t pd t pd 50% 50% tf 10% 90% tr 90% 10% Figure 4. Timing Characteristics 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 9 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33883 is an H-bridge gate driver (or full-bridge predriver) with integrated charge pump and independent highand low-side driver channels. It has the capability to drive large gate-charge MOSFETs and supports high PWM frequency. In sleep mode its supply current is very low. FUNCTIONAL PIN DESCRIPTION SUPPLY VOLTAGE PINS (VCC AND VCC2) The VCC and VCC2 pins are the power supply inputs to the device. VCC is used for the output high-side drivers and the charge pump. VCC2 is used for the linear regulation. They can be connected together or independent with different voltage values. The device can operate with VCC up to 55 V and VCC2 up to 28 V. The VCC and VCC2 pins have undervoltage (UV) and overvoltage (OV) shutdown. If one of the supply voltage drops below the undervoltage threshold or rises above the overvoltage threshold, the gate outputs are switched LOW in order to switch off the external MOSFETs. When the supply returns to a level that is above the UV threshold or below the OV threshold, the device resumes normal operation according to the established condition of the input pins. INPUT HIGH- AND LOW-SIDE PINS (IN_HS1, IN_HS2, AND IN_LS1, IN_LS2) The IN_HSn and IN_LSn pins are input control pins used to control the gate outputs. These pins are 5.0 V CMOScompatible inputs with hysteresis. IN_HSn and IN_LSn independently control GATE_HSn and GATE_LSn, respectively. is in sleep mode. The device is enabled and fully operational when the G_EN pin voltage is logic HIGH, typically 5.0 V. CHARGE PUMP OUT (CP_OUT) The CP_OUT pin is used to connect an external reservoir capacitor for the charge pump. CHARGE PUMP CAPACITOR PINS (C1 AND C2) The C1 and C2 pins are used to connect an external capacitor for the charge pump. LINEAR REGULATOR OUTPUT (LR_OUT) The LR_OUT pin is the output of the internal regulator. It is used to connect an external capacitor. GROUND PINS (GND_A, GND1 AND GND2) These pins are the ground pins of the device. They should be connected together with a very low impedance connection. During wake-up, the logic is supplied from the G_EN pin. There is no internal circuit to prevent the external high-side and low-side MOSFETs from conducting at the same time. SOURCE OUTPUT HIGH-SIDE PINS (SRC_HS1 AND SRC_HS2) The SRC_HSn pins are the sources of the external highside MOSFETs. The external high-side MOSFETs are controlled using the IN_HSn inputs. GATE HIGH- AND LOW-SIDE PINS (GATE_HS1, GATE_HS2, AND GATE_LS1, GATE_LS2) The GATE_HSn and GATE_LSn pins are the gates of the external high- and low-side MOSFETs. The external highand low-side MOSFETs are controlled using the IN_HSn and IN_LSn inputs. GLOBAL ENABLE (G_EN) The G_EN pin is used to place the device in a sleep mode. When the G_EN pin voltage is a logic LOW state, the device 33883 10 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Table 5. Functional Truth Table Conditions G_EN IN_HSn IN_LSn Gate_HSn Gate_LSn Comments Sleep 0 x x 0 0 Device is in Sleep mode. The gates are at low state. Normal 1 1 1 1 1 Normal mode. The gates are controlled independently. Normal 1 0 0 0 0 Normal mode. The gates are controlled independently. Undervoltage 1 x x 0 0 The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. Overvoltage 1 x x 0 0 The device is currently in fault mode. The gates are at low state. Once the fault is removed, the 33883 recovers its normal mode. Overtemperature on High-Side Gate Driver 1 1 x 0 x The device is currently in fault mode. The high-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode. Overtemperature on Low-Side Gate Driver 1 x 1 x 0 The device is currently in fault mode. The low-side gate is at low state. Once the fault is removed, the 33883 recovers its normal mode. x = Don’t care. 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DEVICE OPERATION FUNCTIONAL DEVICE OPERATION DRIVER CHARACTERISTICS Figure 5 represents the external circuit of the high-side gate driver. In the schematic, HSS represents the switch that is used to charge the external high-side MOSFET through the GATE_HS pin. LSS represents the switch that is used to discharge the external high-side MOSFET through the GATE_HS pin. A 180K internal typical passive discharge resistance and a 18 V typical protection zener are in parallel with LSS. The same schematic can be applied to the external low-side MOSFET driver simply by replacing pin CP_OUT with pin LR_OUT, pin GATE_HS with pin GATE_LS, and pin SRC_HS with GND. The different voltages and current of the high-side gate driver are illustrated in Figure 6. The output driver sources a peak current of up to 1.0 A for 200 ns to turn on the gate. After 200 ns, 100 mA is continuously provided to maintain the gate charged. The output driver sinks a high current to turn off the gate. This current can be up to 1.0 A peak for a 100 nF load. IN_HS1 0 HSSpulse_IN 0 CP_OUT HSS DC_IN HSS 0 IGATE_HS HSSDC_IN Icharge HSS GATE_HS1 LSS_IN Idischarge LSS IN_HS1 HSSpulse_IN LSS Icharge HSS 180 k 100 mA Typical 0 18V LSS_IN 1.0 A Peak SRC_HS1 Idischarge LSS 1.0 A Peak 0 Figure 5. High-Side Gate Driver Functional Schematic IGATE_HS 1.0 A Peak 100 mA Typical 0 -1.0 A Peak Note GATE_HS is loaded with a 100 nF capacitor in the chronograms. A smaller load will give lower peak and DC charge or discharge currents. Figure 6. High-Side Gate Driver Chronograms 33883 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES OPERATIONAL MODES TURN-ON TURN-OFF For turn-on, the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: The peak current for turn-off can be obtained in the same way as for turn-on, with the exception that peak current for fall time, tf, is substituted for tr: I P = Qg / t r = 80 nC / 80 ns 1.0 A I P = Qg /t f = 80 nC / 80 ns 1.0 A Where Q g is power MOSFET gate charge and t r is peak current for rise time. Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Causes increased uncontrolled turn-on of low-side MOSFET. Crss In addition to the dynamic current required to turn off or on the MOSFET, various application-related switching scenarios must be considered. These scenarios are presented in Figure 7. In order to withstand high dV/dt spikes, a low resistive path between gate and source is implemented during the OFF-state. Flyback spike pulls down high-side source VGS. Delays turn-off of highside MOSFET. VBAT Crss VBAT Flyback spike charges lowside gate via Crss charge current Irss up to 2.0 A. Delays turn-off of low-side MOSFET. Crss VBAT OFF OFF Ciss GATE_HS ILOAD L1 Ciss GATE_HS ILOAD L1 Ciss Crss Crss Crss GATE_HS Irss Flyback spike pulls down high-side source VGS. Causes increased uncontrolled turn-on of high-side Crss VBAT VGATE -VDRN GATE_HS ILOAD L1 Ciss L1 ILOAD Crss VGATE GATE_LS OFF Ciss GATE_LS Driver Requirement: Low Resistive GateSource Path During OFF-State OFF Ciss Driver Requirement: Low Resistive GateSource Path During OFF-State. High Peak Sink Current Capability GATE_LS Ciss Driver Requirement: High Peak Sink Current Capability GATE_LS Ciss Driver Requirement: Low Resistive GateSource Path During OFF-State Figure 7. OFF-State Driver Requirement 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES LOW-DROP LINEAR REGULATOR The low-drop linear regulator is supplied by VCC2. If VCC2 exceeds 15.0 V, the output is limited to 14.5 V (typical). capacitor CCP_OUT provides peak current to the high-side MOSFET through HSS during turn-on (3). VLR_OUT VLR-OUT The low-drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT, and the +14.5 V for the charge pump, which generates the CP_OUT The low-drop linear regulator provides 4.0 mA average current per driver stage. CP_out CP_OUT Tosc2 Tosc2 Ccp CCP C1 C1 In case of the full bridge, that means approximately 16 mA — 8.0 mA for the high side and 8.0 mA for the low side. D1 D1 C2 C2 D2 D2 Tosc1 Tosc1 VVcc CC Note: The average current required to switch a gate with a frequency of 100 kHz is: ICP = Qg * f PWM = 80 nC * 100 kHz = 8.0 mA GATE_HS GATE_HS LSS CHARGE PUMP T2 The charge pump generates the high-side driver supply voltage (CP_OUT), buffered at CCP_OUT. Figure 8 shows the charge pump basic circuit without load. V LR_OUT VLR_OUT Osc. OSC. D1 D1 (3) T1 HSS In a full-bridge application only one high side and one low side switches on or off at the same time. (2) C Ccp_out CP_OUT Rg Rg HS MOSFET High-Side MOSFET SRC_HS SRC_HS LS VCP_OUT CP_OUT Low-Side MOSFET MOSFET Ccp CCP A C2 C1 CCcp_out CP_OUT Pins pins Figure 9. High-Side Gate Driver D2 D2 (1) VVbat CC Figure 8. Charge Pump Basic Circuit When the oscillator is in low state [(1) in Figure 8], CCP is charged through D2 until its voltage reaches VCC - VD2. When the oscillator is in high state (2), CCP is discharged though D1 in CCP_OUT, and final voltage of the charge pump, VCP_OUT, is Vcc + VLR_OUT - 2VD. The frequency of the 33883 oscillator is about 330 kHz. EXTERNAL CAPACITORS CHOICE External capacitors on the charge pump and on the linear regulator are necessary to supply high peak current absorbed during switching. Figure 9 represents a simplified circuitry of the high-side gate driver. Transistors Tosc1 and Tosc2 are the oscillatorswitching MOSFETs. When Tosc1 is on, the oscillator is at low level. When Tosc2 is on, the oscillator is at high level. The 33883 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES CCP CCP_OUT CCP choice depends on power MOSFET characteristics and the working switching frequency. Figure 10 contains two diagrams that depict the influence of CCP value on VCP_OUT average voltage level. The diagrams represent two different frequencies for two power MOSFETs, MTP60N06HD and MPT36N06V. Figure 11 depicts the simplified CCP_OUT current and voltage waveforms. fPWM is the working switching frequency. VCP_OUT V Cp_out rage V Cp_out Average VCP_OUT 21 in low Low in State state High Side High Side Turn On turn on V VCcp CP_OUT _ out 20 kHz 20KhZ 100 100 kHz KhZ 20.5 VVcp_out (V) CP_OUT (v) Oscillator Oscillator in high High in Oscillator State Oscillator state ICP_OUT I Cp_out 20 ffPWM PWM f=330kHz f = 330 kHz 19.5 19 18.5 18 5 25 45 65 Peak Peak Current Current 85 Figure 11. Simplified CCP_OUT Current and Voltage Waveforms C (nF) Ccp CP(nF) MTP60N06HD (Qg=50nC) MTP60N06HD (Qg = 50 nC) MTP60N06HD (Qg = 50 nC) 21.5 20 kHz 100 kHz 21 Vcp_out (V)(V) VCP_OUT As shown above, at high-side MOSFET turn-on VCP_OUT voltage decreases. This decrease can be calculated according to the CCP_OUT value as follows: VCP_OUT = 20.5 CCP_OUT Where Qg is power MOSFET gate charge. 20 19.5 CLR_OUT CLR_OUT provides peak current needed by the low-side MOSFET turn-on. VLR_OUT decrease is as follows: 19 18.5 5 Qg 25 45 65 85 CCcp (nF) CP (nF) VLR_OUT = Qg CLR_OUT MTP36N06V (Qg = 40 nC) Figure 10. VCP_OUT Versus CCP The smaller the CCP value is, the smaller the VCP_OUT value is. Moreover, for the same CCP value, when the switching frequency increases, the average VCP_OUT level decreases. For most of the applications, a typical value of 33 nF is recommended. TYPICAL VALUES OF CAPACITORS In most working cases the following typical values are recommended for a well-performing charge pump: CCP = 33 nF, CCP_OUT = 470 nF, and CLR_OUT = 470 nF These values give a typical 100 mV voltage ripple on VCP_OUT and VLR_OUT with Qg = 50 nC. 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES PROTECTION AND DIAGNOSTIC FEATURES GATE PROTECTION LOAD DUMP AND REVERSE BATTERY The low-side driver is supplied from the built-in low-drop regulator. The high-side driver is supplied from the internal charge pump buffered at CP_OUT. VCC and VCC2 can sustain load a dump pulse of 40 V and double battery of 24 V. Protection against reverse polarity is ensured by the external power MOSFET with the freewheeling diodes forming a conducting pass from ground to VCC. Additional protection is not provided within the circuit. To protect the circuit an external diode can be put on the battery line. It is not recommended putting the diode on the ground line. The low-side gate is protected by the internal linear regulator, which ensures that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump, the voltage at CP_OUT can be up to 65 V. The highside gate is clamped internally in order to avoid a VGS exceeding 18 V. Gate protection does not include a fly-back voltage clamp that protects the driver and the external MOSFET from a flyback voltage that can occur when driving inductive load. This fly-back voltage can reach high negative voltage values and needs to be clamped externally, as shown in Figure 12. LR_OUT IN OUT M1 VCC GATE_HS VGS < 14 V Under All Conditions SRC_HS L1 Dc l M2 IN Output Driver OUT There is temperature shutdown protection per each halfbridge. Temperature shutdown protects the circuitry against temperature damage by switching off the output drivers. Its typical value is 175°C with an hysteresis of 15°C. DV/DT AT VCC CP_OUT Output Driver TEMPERATURE PROTECTION Inductive Flyback Voltage Clamp GATE_LS Figure 12. Gate Protection and Flyback Voltage Clamp VCC voltage must be higher than (SRC_HS voltage minus a diode drop voltage) to avoid perturbation of the high-side driver. In some applications a large dV / dt at pin C2 owing to sudden changes at VCC can cause large peak currents flowing through pin C1, as shown in Figure 13. For positive transitions at pin C2, the absolute value of the minimum peak current, I C1min, is specified at 2.0 A for a t C1min duration of 600 ns. For negative transitions at pin C2, the maximum peak current, IC1max, is specified at 2.0 A for a t C1max duration of 600 ns. Current sourced by pin C1 during a large dV / dt will result in a negative voltage at pin C1 (Figure 13). The minimum peak voltage VC1min is specified at -1.5 V for a duration of t C1max = 600 ns. A series resistor with the charge pump capacitor (Ccp) capacitor can be added in order to limit the surge current. 33883 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES VCC IC1max t C1min I (C1+C2) 0A t C1max I C1min V(LR_OUT) V(C1) 0V VC1min Figure 13. Limits of C1 Current and Voltage with Large Values of dV/dt In the case of rapidly changing VCC voltages, the large dV/ dt may result in perturbations of the high-side driver, thereby forcing the driver into an OFF state. The addition of capacitors C3 and C4, as shown in Figure 14, reduces the dV/dt of the source line, consequently reducing driver perturbation. Typical values for R3 / R4 and C3 / C4 are 10 and 10 nF, respectively. DV/DT AT VCC2 When the external high-side MOSFET is on, in case of rapid negative change of VCC2 the voltage (VGATE_HS VSRC_HS) can be higher than the specified 18 V. In this case a resistance in the SRC line is necessary to limit the current to 5.0 mA max. It will protect the internal zener placed between GATE_HS and SRC pins. In case of high current (SRC_HS >100 mA) and high voltage (>20 V) between GATE_HSX and SRC_HS an external zener of 18 V is needed as shown in Figure 14. 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 17 TYPICAL APPLICATIONS TYPICAL APPLICATIONS VBAT VBOOST 33883 VCC VCC2 G_EN CCP 33 nF C1 C2 MCU IN_HS1 IN_LS1 IN_HS2 IN_LS2 VCC VCC2 G_EN C1 C2 IN_HS1 CCP_OUT 470 nF CP_OUT LR_OUT GATE_HS1 SRC_HS1 CLR_OUT 470 nF 18 V GATE_HS2 IN_LS1 SRC_HS2 50 M3 R2 50 R4 10 C3 10 nF C4 10 nF DC Motor 18 V IN_HS2 GATE_LS2 IN_LS2 M1 R3 10 GATE_LS1 R1 M2 50 M4 GND 50 Figure 14. Application Schematic with External Protection Circuit 33883 18 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98ASB42343B drawing number below. Dimensions shown are provided for reference ONLY. DW SUFFIX EG SUFFIX (PB-FREE) 20-PIN SOICW PLASTIC PACKAGE 98ASB42343B ISSUE J 33883 Analog Integrated Circuit Device Data Freescale Semiconductor 19 REVISION HISTORY PACKAGING DIMENSIONS REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 9.0 1/2007 • • • • • Implemented Revision History page Updated to the current Freescale format and style Added MCZ33883EG/R2 to the Ordering Information Updated the package drawing to Rev. J Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 4. Added note with instructions from www.freescale.com. 10.0 10/2012 • • • Updated orderable part number from MCZ33883EG to MC33883HEG. Updated Freescale form and style Removed MC33883DW from the ordering information 33883 20 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software Home Page: freescale.com implementers to use Freescale products. There are no express or implied copyright Web Support: freescale.com/support information in this document. licenses granted hereunder to design or fabricate any integrated circuits based on the Freescale reserves the right to make changes without further notice to any products herein. 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Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, CWare, Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Document Number: MC33883 Rev 10.0 10/2012