Freescale Semiconductor, Inc.
MC33253
Advance Information
Freescale Semiconductor, Inc...
Full Bridge Pre-Driver
The MC33253 is a full bridge driver including integrated charge
pump, two independent high and low side driver channels.
The high and low side drivers include a cross conduction suppression
circuit, which, if enabled, prevents the external power FETs from being on
at the same time.
The drive outputs are capable to source and sink 1 A pulse peak
current. The low side channel is referenced to ground, the high side
channel is floating above ground.
A linear regulator provides a maximum of 15.5V to supply the low
side gate driver stages. The high side driver stages are supplied with a
10V charge pump voltage. Such built-in feature, associated to external
capacitor provides a full floating high side drive.
An under- and over-voltage protection prevents erratic system
operation at abnormal supply voltages. Under fault, these functions force
the driver stages into off state.
The logic inputs are compatible with standard CMOS or LSTTL
outputs. The input hysteresis makes the output switching time
independent of the input transition time.
The global enable logic signal can be used to disable the charge
pump and all the bias circuit. The net advantage is the reduction of the
quiescent supply current to under 10µA. To wake up the circuit, 5 V has to
be provided at G_EN. A built-in single supply operational amplifier could
be used to feedback information from the output load to the external
MCU.
• VCC Operating Voltage Range from 5.5 V up to 55 V
• VCC2 Operating Voltage Range from 5.5 V up to 28 V
• Automotive Temperature Range -40°C to 125°C
• 1A Pulse Current Output Driver
• Fast PWM Capability
• Built-In Charge Pump
• Cross Conduction Suppression Circuit
Order Number: MC33253/D
Rev 3, 03/2001
55 VOLTS
SEMICONDUCTOR
TECHNICAL DATA
DW SUFFIX
PLASTIC PACKAGE
CASE 751F-05
PIN CONNECTIONS
(TOP VIEW)
CASE 751F-05
VCC
1
28 ISOUT
C2
2
27 G_EN
CP_OUT
3
26 /CCS
SRC_HS1 4
25 SRC_HS2
GATE_HS1 5
24 GATE_HS2
/IN_HS1
6
23 /IN_HS2
IN_HS1
7
22 IN_HS2
/IN_LS1
8
21 /IN_LS2
IN_LS1
9
20 IN_LS2
19 GATE_LS2
GATE_LS1 10
GND1
11
18 GND2
LR_OUT
12
17 IS-IN
VCC2
13
16 IS+IN
GND_A
14
15 C1
ORDERING INFORMATION
Device
PC33253DW
Temperature
Range
-40oC
to
+125oC
Package
SOIC28
This document contains information on a new product. Specifications and information herein are
subject to change without notice.
© Motorola, Inc., 2001. All rights reserved.
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Page 1/15
MC33253
Freescale
Semiconductor,
Inc.
Figure 1. Principal Building Blocks
Ccp
C1
VCC
C2
VCC2
VCC
VCC2
UV/OV
Detect
VCC
C1
RDY
VDD
EN
GND
VCC
Vpos
+13.5 V
G_EN
CCP_OUT 5.5 V...
55 V
VCC2
VCC2
VDD
+13.5 V
CP_OUT
Linear +5.0 V
EN
Reg
GND
+13.5 V
/CCS
Freescale Semiconductor, Inc...
5.5 V...
28 V
VCC
C2
Charge
Pump
CLR_OUT
BRG_EN
HIGH AND LOW SIDE
CONTROL WITH CHARGE PUMP
CCS
Vgs_ls
BRG_EN
CCS
LR_OUT
Vgs_hs
Vgs_ls
VCC
IN_HS1
VDD
VDD/VPOS
Level Shift
IN Output
Driver
Pulse
Generator
OUT
GATE_HS1
SRC_HS1
/IN_HS1
G_LOW_H
Input
&
CCS
G_LOW_LS
IN_LS1
LOGIC
VDD
VDD/VCC
Level Shift
/IN_LS1
IN Output
Driver
Pulse
Generator
OUT
GATE_LS1
HIGH AND LOW SIDE CHANNEL
WITH CROSS CONDUCTION SUPPRESSION
BRG_EN
Vgs_ls
CCS
VCC
IN_HS2
VDD
VDD/VPOS
Level Shift
Pulse
Generator
IN Output
OUT
Driver
GATE_HS2
SRC_HS2
/IN_HS2
G_LOW_H
Input
&
CCS
IN_LS2
VDD
G_LOW_LS
VDD/VCC
Level Shift
Pulse
Generator
IN
Output
Driver
OUT
GATE_LS2
/IN_LS2
HIGH AND LOW SIDE CHANNEL WITH
CROSS CONDUCTION SUPPRESSION
SENSE CURRENT AMPLIFIER
CAO
GND
MC33253
CA-
+
CA+
ISOUT
IS+IN
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IS-IN
rev3.0 - 2/15
MC33253
Freescale Semiconductor,
Inc.
ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to GND.
Rating
Symbol
Min
Max
Unit
Supply Voltage1
VCC
-0.3
65
V
Supply Voltage2 (NOTE 1)
VCC2
-0.3
35
V
VLR_out
-0.3
18
V
High Side Floating Supply Absolute Voltage
VCP_OUT
-0.3
65
V
High Side Floating Source Voltage
VSRC_HS
-0.3
65
V
High Side Gate Voltage
VGATE_HS
-0.3
65
V
High Side Gate Source Voltage
VGATE_HS
- VSRC_HS
-0.3
20
V
250
mA
Freescale Semiconductor, Inc...
Linear Regulator Output Voltage
High Side Source Current from Cpout in Switch On State
IS
VCP_OUT
- VGATE_HS
-0.3
65
V
VGATE_LS
-0.3
17
V
VG_EN
-0.3
35
V
Logic Input Voltage
VIN
-0.3
10
V
Charge Pump Capacitor Voltage
VC1
-0.3
VLR_OUT
V
Charge Pump Capacitor Voltage
VC2
-0.3
65
V
Operational Amplifier Output Voltage
VCAO
-0.3
7
V
Operational Amplifier Inverting Input Voltage
VCA-
-0.3
7
V
Operational Amplifier Non Inverting Input Voltage
VCA+
-0.3
7
V
ESD Voltage on any Pins (HBM, 100pF, 1.5kOhms)
VESD
-2.0
2.0
kV
High Side Floating Supply Gate Voltage
Low Side Output Voltage
Wake up Voltage
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation@25°C
PD
2
W
Thermal Resistance Junction-to-Air
RθJA
60
°C/W
Operating Junction Temperature
TJ
-40
+150
°C
Storage Temperature
Tstg
-65
+150
°C
Symbol
Min
Max
Unit
Supply Voltage1
VCC
5.5
55
V
Supply Voltage2
VCC2
5.5
28
V
VCP_OUT
VCC+4
VCC+11but<65
V
OPERATING CONDITIONS Typical values for TA = 25°C, Min/Max values for TA = -40°C to +125°C
Rating
High Side Floating Supply Absolute Voltage
NOTE1: VCC can sustain load dump pulse 40V, 400ms, 2Ohms
MC33253
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rev3.0 - 3/15
MC33253
Freescale Semiconductor,
Inc.
STATIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified.
Typical values for TA = 25°C, Min/Max values for TA = -40°C to +125°C, unless otherwise specified.
Characteristics
Pin #
Symbol
Min
7, 9, 20, 22
VIH
2.0
Typ
Max
Unit
10
V
0.8
V
LOGIC SECTION
Logic “1” Input Voltage (IN_LS & IN_HS)
Logic “0” Input Voltage (IN_LS & IN_HS)
VIL
Iin+
200
1000
uA
Iin-
200
1000
uA
6, 8, 21, 23,
26
VIH
2.0
10
V
0.8
V
6, 8, 21, 23,
26
Iin+
TBD
TBD
uA
Iin-
TBD
TBD
uA
Wake Up Input Voltage (G_EN)
27
VG_EN
4.5
5.0
VCC2
V
Wake Up Current (G_EN) VG_EN = 14 V
27
IG_EN
200
500
uA
12
VLR_OUT
13.5
16.5
V
12
VLR_OUT
VCC2 1.5
Logic “1” Input Current Vin=5V
7, 9, 20, 22
Logic “0” Input Current Vin=0V
Logic “0” Input Voltage (/IN_LS & /IN_HS&/CCS)
Logic “1” Input Voltage (/IN_LS & /IN_HS&/CCS)
Logic “0” Input Current Vin=5V
Freescale Semiconductor, Inc...
Logic “1” Input Current Vin=0V
VIL
LINEAR REGULATOR SECTION
Linear Regulator
VLR_OUT @ VCC2 from 16.5 to 28 V, ILOAD from
0mA to 20mA
Linear Regulator
VLR_OUT @ VCC2 =12 V, ILOAD = 20mA
VLR_OUT @ VCC2 =5.5V, ILOAD =TBD, VCC = 5.5V
12
V
TBD
V
CHARGE PUMP SECTION
Charge Pump Output Voltage, referenced to VCC
ILOAD = 0mA, CCpout=1uF
3
VCP_OUT
VLR_OUT
-2
V
Charge Pump Output Voltage, referenced to VCC
ILOAD = 7mA, CCpout=1uF
3
VCP_OUT
VLR_OUT
-3
V
Charge Pump Output Voltage, referenced to VCC
VCC2 = VCC=5.5V
ILOAD = 0mA, CCpout=1uF
3
VCP_OUT
VLR_OUT
- TBD
V
Charge Pump Output Voltage, referenced to VCC
VCC2 = VCC=5.5V
ILOAD = 7mA, CCpout=1uF
3
VCP_OUT
VLR_OUT-TBD
V
Peak current through pin 15under rapid changing
Vcc voltages (see Figure 6)
15
IC1
-2.0
Minimum peak voltage at pin 15under rapid
changing Vcc voltages (see Figure 6)
15
VC1min
-1.5
2.0
A
V
SUPPLY VOLTAGE SECTION
Quiescent Vcc Supply Current VG_EN=0V
1
TBD
uA
Operating Vcc Supply Current
(@VCC=55V and VCC2=28V)
(@VCC=12V and VCC2=12V)
1
1
TBD
TBD
mA
mA
Quiescent Vcc2 Supply Current VG_EN=0V
13
TBD
uA
MC33253
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rev3.0 - 4/15
MC33253
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Characteristics
Pin #
Symbol
Min
Typ
Max
Unit
10
8
mA
Operating Vcc2 Supply Current
(@VCC=55V and VCC2=28V)
(@VCC=12V and VCC2=12V)
Logic pin inactive (high impedance)
13
13
Under Voltage Shutdown VCC2 (Note2)
13
UV2
4.6
5.1
5.5
V
Under Voltage Shutdown VCC
1
UV
4.6
5.1
5.5
V
Over Voltage Shutdown VCC
1
OV
57
61
64
V
Over Voltage Shutdown VCC2
13
OV2
29.5
31
32.5
V
OUTPUT SECTION
Freescale Semiconductor, Inc...
Output Sink Resistance (Turned off)
VGATE_HS - VSRC_HS =1V
3, 4, 5, 10,
19, 24, 25
Output Source Resistance (Turned on)
VCP_OUT - VGATE_HS =0.1V
High Side Source Current from Cpout in Switch
On State
Max Voltage (VGATE_HS - VSRC_HS),
INH=1, ISmax=200mA
4, 25
RDS
22.0
Ohms
RDS
22.0
Ohms
ISmax
200
mA
18
V
300
V
mV
4, 5, 24, 25
SENSE CURRENT AMPLIFIER SECTION (Internal VCC supply @ 12V)
Output Dynamic Range (Isink/source = 200µA)
28
Open Loop Gain (at 25°C)
VOH
VOL
4.7
A
Input Bias Current
16, 17
50
IIB
Vio
-5.0
Input Common Mode Voltage Range
ICMR
0
Common Mode Rejection Ratio
CMRR
Input Offset Voltage (at 25°C)
5.0
2.0
dB
1.0
uA
5.0
mV
5
V
70
dB
Sink Capability (Vo>1.1V) (Note 3)
28
Isink
2.0
3.0
mA
Source Capability (Vo<5V) (Note 3)
28
Isource
2.0
3.0
mA
1.8
MHz
Gain Bandwidth Product
GBW
Operational Amplifier Output Voltage, Isink=500uA
28
VCAO
Operational Amplifier Output Voltage,
Isource=500uA
28
VCAO
0.5
5
V
V
Operational Amplifier Slew Rate (+)
SR+
1
V/us
Operational Amplifier Slew Rate (-)
SR-
1
V/us
MC33253
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rev3.0 - 5/15
MC33253
Freescale Semiconductor,
Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified.
Typical values for TA = 25°C, Min/Max values for TA = -40°C to +125°C, unless otherwise specified.
Characteristics
Prop. Delay HS and LS, Cload=5nF;
Between 50% Input to 50% Output
(see Figure 2)
Pin #
Symbol
5, 6, 7, 8, 9,
20, 21, 22, 23
Turn On Rise Time, Cload=5nF ;
10% to 90% (NOTE 4) (see Figure 2)
Turn Off Fall Time, Cload=5nF ;
10% to 90% (NOTE 4) (see Figure 2)
Min
Typ
Max
Unit
tPD
200
300
ns
tr
80
180
ns
tf
80
180
ns
5, 10, 19, 24
NOTE 2: Between 4.6V and 5.5V, the device has been a non erroneous behaviour.
NOTE 3: Input overdrive 1V
NOTE 4: Rise time is given by time needed to charge the gate from 1V to 10V (Vice versa for fall time)
Freescale Semiconductor, Inc...
NOTE : Cload corresponds to a capacitor between GATE_HS and SRC_HS for the high side and between GATE_LS and ground for low side.
N.B.
In some applications a large dV/dt at Pin 2 (C2) due to sudden changes at VCC can cause a large peak currents flowing through
Pin15 (C1).
Positive transitions at Pin2 (C2) ;mimimum peak current :
Ic1min = 2.0A
tc1min = 600ns (see for peak description)
Negative transitions at Pin2 (C2); maximum peak current :
Ic1max = 2.0A
tc1max = 600ns (see for peak description)
Current sourced by Pin 15 (C1) during a large dV/dt will result in a negative voltage at Pin 15; negative transitions at Pin2(C2);
minimum peak voltage:
Vc1min = -1.5V
tc1max = 600ns (see for peak description)
Figure 2. Limits of C1 Current&Voltage with Large ValuesdV/dt of Vcc
VCC
Ic1max
tC1min
I[C1+C2]
0A
tc1max
Ic1min
V[LR_OUT]
V[C1]
0V
Vc1min
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rev3.0 - 6/15
MC33253
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Figure 3. Dynamic Characteristics
/IN_HS
or /IN_LS
50%
50%
50%
50%
IN_HS
or IN_LS
tpd
GATE_HS
or GATE_LS
tpd
50%
50%
tr
tf
90%10%
Freescale Semiconductor, Inc...
10% 90%
Driver Characteristics
Turn-On
For turn-on the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows:
Peak Current for Rise/Fall Time (tr) and a typical PowerMosFET Gate Charge Qg. IP = Qg/tr = 75 nC/80 ns ª 1.0 A
Turn-Off
The peak current for turn-off can be obtained in the same way as for turn-on. In addition to the dynamic current, required to
turn-off or turn-on the FET, various application related switching scenarios have to be considered:
The output driver sources a peak current of up to 1A for 200 ns to turn on the gate. After 200 ns 100 mA are provided
continuously to maintain the gate charged. The output driver sinks a peak current of up to 1A for 200 ns to turn off the gate. After
200 ns 100 mA are sinked continuously to maintain the gate discharged. In order to withstand high dV/dt spikes a low resistive
path between gate and source is implemented during the off state.
Figure 4. OFF-State Driver Requirement
Flyback Spike charge LS-Gate via Crss Flyback Spike pull down HSCharge Current Irss up to 2.0 A! Uncon- Drain VGS Increase Delayed
Turn-Off of High Side FET
trolled Turn-On of Low Side FET
Crss
VBAT
Crss
Flyback Spike charge LS-Gate via
Crss Charge Current Irss up to 2.0 A!
Delayed Turn-Off of Low Side FET
VBAT
Crss
Flyback Spike pull down HSDrain VGS Increase Uncontrolled
Turn-On of High Side FET
VBAT
Crss
OFF
OFF
g_hs
g_hs
Ciss
L1
Ciss
Crss
Irss
VGATE
-VDRN
g_hs
ILOAD
L1
ILOAD
Ciss
Crss
VBAT
L1
g_hs
ILOAD
Ciss
L1
ILOAD
Crss
Crss
VGATE
g_ls
g_ls
OFF
OFF
Ciss
g_ls
Ciss
g_ls
Ciss
Ciss
Driver Requirement: Low Driver Requirement: Low Resistive Driver Requirement:
Driver Requirement: Low Resistive
Resistive Gate-Source
Gate Source Path during OFF-State. High Peak Sink Current Capab. Gate-Source Path during OFF-State
Path during OFF-State
High Peak Sink Current Capab.
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rev3.0 - 7/15
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Driver Supply
The High Side Driver is supplied from the internal charge pump buffered at CP_OUT. The low-drop regulator provides
approx. 3.5 mA (fPWM = 50kHz) per gate. In case of the full bridge that means approximately. 14 mA; 7.0 mA for the high side and
7.0 mA for the low side. (Note: The average current required to switch a gate with a frequency of 100kHz is: Average Current
(Charge Pump) for PWM Frq. (fPWM) and ICP = Qg*fPWM = 75 nC*100 kHz = 7.5mA. A full bridge application switch only one high side
and one low side at the same time.)
External capacitors on Charge Pump and on Linear Regulator are necessary to supply high peak current absorbed during
switching. The Low Side Driver is supplied from built in low drop regulator.
Gate Protection
The low side gate is protected by the internal linear regulator, which guarantees that VGATE_LS does not exceed the maximum
VGS. Especially when working with the charge pump the voltage at POS_HS can be up to 65V. The high side gate is clamped
internally, in order to avoid a VGS exceeding 14V.
The Gate protection does not include a Flyback Voltage Clamp that protects the driver and the external FET from a Flyback
voltage that can appear when driving inductive load.This Flyback voltage can reach high negative voltage values and needs to
be clamped externally.
Freescale Semiconductor, Inc...
Figure 5. Gate Protection and Flyback Voltage Clamp
Vgs_ls
Vgs_hs
VCC
M1
IN Output OUT
Driver
GATE_HS
VGS < 14 V
under all
conditions
SRC_HS
G_LOW
L1
Dcl
G_LOW
IN Output
Driver
M2
OUT
Inductive
Flyback Voltage
Clamp
GATE_LS
TMOS Failure Protection
All output driver stages are protected against TMOS failure conditions. If one of the external power FETs is destroyed (Gate
= VCC, or Gate = Gnd) the function of the remaining output driver stages is not affected. All output drivers are short circuit
protected against short circuits to ground.
Cross Conduction Suppression
The purpose of the cross conduction suppression is to avoid that high and low side FET are turned on at the same time,
which prevents the half bridge power FETs of a shoot-through condition. The CCS can be disabled / enabled by an external
signal (/CCS).
- /CCS=0, the cross conduction is not allowed.
- /CCS=1, the cross conduction is allowed.
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Figure 6. Input Logic and Cross Conduction Suppression
G_EN
EN_CP/LDO
AND
AND
“1” Enable Charge Pump and LDO
{“1” Supply is ok
UV_OV
RDY
“1” Charge Pump is Ready
/CCS
“0” Cross Conduction Suppression is Enabled
en2hs = G_LOW_LS, en2ls = G_LOW_HS
CCS
BRG_EN
IN_HS
“1” Cross Conduction Suppression is Disabled
en2hs = “1”, en2ls = “1” en1hs = “0”, en1ls = “0”
10 k
AND
AND
en1_hs
10 k
OUT_HS
“1” Turn-On FET
OR
Freescale Semiconductor, Inc...
G_LOW_H
en2_hs
/IN_HS
AND
IN_LS
“1” FET is Turned-Off
G_LOW_LS
AND
10 k
OR
en2_ls
en1_ls
AND
AND
drv_ls
“1” FET is Turned-Off
OUT_LS
“1” Turn-On FET
/IN_LS
Logic Inputs
Logic Input Voltage Range:
Absolute Max :
-0.3 V ... 10 V
Wake Up Function:
(G_EN)
4.5 V ... VCC2
During Wake-Up the logic is supplied from the G_EN pin.
Low Drop Linear Regulator
The low drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT and the +13.5 V for the
charge pump, which generates the Vgs_hs. The low drop linear regulator provides 3.5 mA average current per driver stage. If typically VCC2
exceeds 14.5V the output is limited to 14V.
Charge Pump
The charge pump generates the high side driver supply voltage ( Vgs_hs), buffered at CCP_OUT. The basic circuit (Fig 7), shows
charge pump without load:
Figure 7. Charge Pump Basic Circuit
VCP_OUT
(2)
VLR_OUT
D1
Ccp
Osc.
Ccp_out
A
D2
(1)
Vbat
When the oscillator is in low state (1), Ccp is charged through D2 until its voltage reaches Vbat-Vd2. When the oscillator is in high
state (2), Ccp is discharged though D1 in Ccp_out, and final voltage of the charge pump, Vcp_out is Vbat+VLR_OUT - 2Vd. The frequency of
the MC33253 oscillator is about 330 kHz.
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rev3.0 - 9/15
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The Figure 8 represents a simplified circuitry of the high side gate driver.
Figure 8. High Side Gate Driver
VLR-OUT
CP_out
Tosc2
Ccp
C1
D1
Ccp_out
C2
D2
Tosc1
(3)
Vcc
HS
MOSFET
GATE_HS
Rg
T2
SRC_HS
M
LS
MOSFET
pins
The transistors Tosc1 and Tosc2 are the oscillator switching MOSFETs. When Tosc1 is on, the oscillator is at low level. When
Tosc2 is on, the oscillator is at high level. The high side MOSFET predriver is composed of two transistors T1 and T2. When T1 is on
the HS MOSFET is turn on, when T2 is on the HS MOSFET is off. The capacitor Ccp_out provides peak current to the HS MOSFET
through T1 during turn on (3) as shown in figure 11.
Ccp
Ccp choice depends on Power MOSFET characteristics and the working switching frequency. The following diagrams show the
influence of Ccp value on Vcp_out average voltage level. The diagrams are given at two different frequencies for two power MOSFETs
(MTP60N06HD and MPT36N06V).
Figure 9. Vcp_out Versus Ccp
21.5
21
20kHz
20KhZ
20.5
100kHz
21
100 KhZ
20
20.5
Vcp_out (V)
Vcp_out (v)
Freescale Semiconductor, Inc...
T1
19.5
19
18.5
20
19.5
19
18
5
25
45
65
85
18.5
5
Ccp (nF)
25
45
65
85
Ccp (nF)
MTP36N06V (Qg=40nC)
MTP60N06HD (Qg=50nC)
Figure 10.
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rev3.0 - 10/15
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The smaller Ccp value is, the smaller Vcp_out value is. Moreover, for a same Ccp value, when the switching frequency
increases, the average Vcp_out level decreases. For most of the applications a typical value of 33nF is recommended.
Ccp_out
As shown in figure 11, at high side MOSFET turn on, Vcp_out voltage decreases. This decrease can be calculated according to
Ccp_out value as following :
∆VCcp _ out =
Qg
Ccp _ out
Qg : Power MosFET Gate Charge
The following figure is the simplified Ccp_out current and voltage waveforms.
fpwm : working switching frequency
Freescale Semiconductor, Inc...
Figure 11. Simplified Ccp_out Current and Voltage Waveforms
V Cp_out
average V Cp_out
I Cp_out
High Side
turn on
Oscillator
in high
state
Oscillator
in low
state
∆ VCcp _ out
fPWM
f=330kHz
Peak
Current
CLR_OUT
CLR_OUT provides peak current needed by the low side MOSFET turn on. VLR_OUT decreasing is as follow:
∆VLR _ out =
Qg
C LR _ out
Capacitors typical values
In most working cases the following typical values are advised for a good charge pump performing:
Ccp=33nF, Ccp_out=470nF and CLR_OUT=470nF.
These values give a typical 100mV voltage ripple on Vcp_out and VLR_OUT with Qg=50nC.
OP-Amp
The built-in A.O.P. available in the MC33253 allows to get a voltage image of the H-bridge current. This voltage can be
provided by a shunt resistor, as shown in figure 13.
Typically shunt resistivity is dimensioned as low as possible (25mOhm/10A). The maximum A.O.P output voltage is 5V.
Therefore a gain of 10 sets the maximum drop voltage on the sensing resistance at 500mV.
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A differential mode is advised as shown in fig 12:
Figure 12. : Differential A.O.P
R3
IS+IN
ISOUT
+
R4
_
V2
AOP
IS-IN
R1
Vout
R2
V1
Vout =
Freescale Semiconductor, Inc...
with R2=R4 and R1=R3,
A gain of 10 gives
R2
(V 2 − V 1)
R1
R2
= 10 ( a )
R1
To minimize the perturbations, impedance seen by the A.O.P inputs may be as low as possible.
Knowing the maximum output current (2mA), the minimum value of (R1+R2) can be deduced when VOUT maximum is 5V:
( R1 + R2 ) min =
5V
= 2,5k ( b )
2mA
with (a) and (b), the minimum values of R1, R2, R3 and R4 can be calculated.
R1=R3=227 Ohms and R2=R4=2.27 kOhms
Over/Under Voltage Shutdown
The under voltage protection becomes active at VCC below 5.5 V and the overvoltage protection is activated at VCC above 55 V or
at VCC2 above 28 V. If the O/UV protection is activated the outputs are driven low, in order to switch off the FETs.
Protection
A protection against double battery and load dump spikes up to 55 V is given by VCC = 55 V. A protection against reverse
polarity is given by the external power FET with the free wheeling diodes, forming a conducting pass from ground to VCC. An
additional protection is not provided within the circuit. There is a temperature shut down protection per each half bridge. It protects
the circuitry against temperature damage by blocking the output drives.
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Figure 13. DC Motor Control with Microcontroller
CLRout 470nF
VBAT
VLOGIC
VCC/VCC2
LR_OUT
/G_EN
CP_OUT
/CCS
C1
CAN
PWM1
PWM2
Freescale Semiconductor, Inc...
PWM3
PWM4
mC
CCp
33nF
IN_HS1
LS_1
IN_LS1
HS_2
IN_HS2
LS_2
IN_LS2
CURRENT FDB
ISOUT
M1
M3
CPout
C2
HS_1
470nF
GATE_HS1
SRC_HS1
FULL
BRIDGE
DRIVER
GATE_LS1
50ohms
50ohms
M
50ohms
GATE_HS2
SRC_HS2
GATE_LS2
50ohms
GND
IS+IN
M2
M4
G
G
IS-IN
SL
SL
R2
R4
R3
Rsense
R1
This application use the internal charge pump to provide the high side floating voltage. This voltage can be provided by an
external source also.
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MC33253
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MC33253
Pin
Symbol
Pin Description
1
VCC
Supply1
2
C2
Charge Pump Capacitor
3
CP_OUT
Charge Pump Out
4
SRC_HS1
Source 1 Output High Side
5
GATE_HS1
Gate 1 Output High Side
6
/IN_HS1
Neg. Input High Side 1
7
IN_HS1
Pos. Input High Side 1
8
/IN_LS1
Neg. Input Low Side 1
9
IN_LS1
Pos. Input Low Side 1
10
GATE_LS1
Gate 1 Output Low Side
11
GND1
Power Ground
12
LR_OUT
Linear Regulator Output
13
VCC2
Supply 2
14
GND_A
Analog Ground (A.O.P)
15
C1
Charge Pump Capacitor
16
IS+
Sense OpAmp Pos. Input
17
IS-
Sense OpAmp Neg. Input
18
GND2
Logic Ground 2
19
GATE_LS2
Gate 2 Output Low Side
20
IN_LS2
Pos. Input Low Side 2
21
/IN_LS2
Neg. Input Low Side 2
22
IN_HS2
Pos. Input High Side 2
23
/IN_HS2
Neg. Input High Side 2
24
GATE_HS2
Gate 2 Output High Side
25
SRC_HS2
Source 2 Output High Side
26
/CCS
Enable Cross Conduction Suppression
27
G_EN
Global Enable
28
IS_OUT
Sense Current OpAmp Output
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D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER
SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
15
0.25
E
H
M
B
M
28
1
14
PIN 1 IDENT
A1
Freescale Semiconductor, Inc...
A
B
e
B
0.025
L
0.10
C
C
M
C A
S
B
SEATING
PLANE
θ
MILLIMETERS
DIM MIN MAX
A
2.35
2.65
A1
0.13
0.29
B
0.35
0.49
C
0.23
0.32
D 17.80 18.05
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
L
0.41
0.90
θ
0°
8°
S
CASE 751F-05
ISSUE F
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