FUJITSU MB15C03

FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21349-1E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C03
■ DESCRIPTION
The Fujitsu MB15C03 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a prescaler. A 64/
65 division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C03 is suitable for mobile communications, such as paging systems.
■ FEATURES
• Frequency operation
• Separate power supply :
90 MHz @VDD = 1.0 to 1.5V
120 MHz @VDD = 1.2 to 1.5V
VDD = 1.0 to 1.5 V (for overall system)
VP = 2.0V to 3.5V (for a charge pump)
•
•
•
•
Power saving function
Pulse swallow function: 64/65
Serial input 14-bit programmable reference divider: R = 5 to 16,383
Serial input 18-bit programmable divider consisting of:
- Binary 6-bit swallow counter: 0 to 63
- Binary 12-bit programmable counter: 5 to 4,095
• Wide operating temperature: Ta = –20 to +60°C
• Plastic 16-pin SSOP package (FPT-16P-M05)
■ PACKAGE
16-pin, plastic SSOP
(FPT-16P-M05)
This device contains circuitry to protect the inputs against damage due to high static voltages or electroc fields. However, it is advised that normal precautions
be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB15C03
■ PIN ASSIGNMENT
2
VDD
1
16
VSS
Clock
2
15
OSCIN
Data
3
14
OSCOUT
LE
4
TEST
fin
TOP 13
VIEW
5
12
PS
6
11
fp
LD
7
10
fr
DO
8
9
FC
VP
MB15C03
■ PIN DESCRIPTIONS
Pin no.
Pin
name
I/O
System
1
VDD
—
1V
Power supply voltage
2
Clock
I
1V
Clock input for the shift register.
Data is shifted into the shift register on the rising edge of the clock.
3
Data
I
1V
Serial data input using binary code.
4
LE
I
1V
Load enable signal input
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
5
fin
I
1V
Prescaler input.
A bias circuit and amplifier are at input port. Connection with an external
VCO should be done by AC coupling.
6
PS
I
1V
Power saving mode control. This pin must be set at “L” at Power-ON.
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
7
LD
O
1V
Lock detector signal output.
When a PLL is locking, LD outputs “H”.
When a PLL is not locking, LD outputs “L”.
Descriptions
8
DO
O
3V
Charge pump output.
Phase of the charge pump can be reversed by FC input. The DO output
may be inverted by FC input. The relationships between the programmable reference divider output(fr) and the programmable divider output(fp)
are shown below;
fr > fp : “H” level (FC= “L”), “L” level (FC= “H”)
fr = fp : High impedance
fr < fp : “L” level (FC= “L”), “H” level (FC= “H”)
9
VP
—
3V
Power supply for the charge pump.
10
fr
O
1V
Programmable reference counter output (fr) monitoring pin.
11
fp
O
1V
Programmable counter output (fp) monitoring pin.
12
FC
I
1V
Phase comparator input select pin.
13
TEST
I
1V
Test mode select pin. (Pull down resistor)
Setting this pin to “H”, test mode becomes available. Please set this pin
to ground or open usually.
14
OSCOUT
O
1V
Oscillator output.
Connection for an external crystal.
15
OSCIN
I
1V
Programmable reference divider input.
Oscillator input.
Clock can be input to OSCIN from outside. In the case, please leave
OSCOUT pin open and make connection with OSCIN as AC coupling.
16
VSS
—
—
Ground.
3
MB15C03
■ BLOCK DIAGRAM
VDD
Crystal
Oscillator
circuit
1
Programmable
reference divider
15 OSCIN
Binary 14-bit
reference counter
fr
14 OSCOUT
Intermittent
mode control
circuit
14
13 TEST
fr
14-bit latch
Phase
comparator
Clock 2
18-bit shift register
Control
register
12 FC
fp
14
Data 3
16 VSS
11
fp
10
fr
9
VP
18
LE
18-bit latch
4
6
12
fin 5
PS
LD
7
Do 8
4
Prescaler
6
Lock detector
Binary 6-bit
swallow
counter
Binary 12-bit
programmable counter
Control Circuit
fp
Charge
pump
MB15C03
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min.
Max.
VDD
GND –0.5
+2.0
V
VP
GND –0.5
+5.0
V
VIN
GND –0.5
VDD +0.5
V
VOUT
GND –0.5
VDD +0.5
V
VOUTP
GND –0.5
VP +0.5
V
IOUT
–10
+10
mA
Operating temperature
Ta
–20
+60
°C
Storage temperature
Tstg
–40
+125
°C
Power supply voltage
Input voltage
Output voltage
Output current
Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Remark
1.5
1.5
V
For 90 MHz
For 120 MHz
—
3.5
V
GND
—
VDD
V
–20
—
+60
°C
Min.
Typ.
Max.
VDD
1.0
1.2
—
—
VP
2.0
Input voltage
VIN
Operating temperature
Ta
Power supply voltage
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
HandIing Precautions
• This device should be transported and stores in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are
properly grounded. Cover workbenches with grounded conductive mats.
• Always turn the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15C03
■ ELECTRICAL CHARACTERISTICS
(For 90 MHz: VDD = 1.0 V to 1.5 V, VP = 2.0 V to 3.5 V, Ta = –20°C to +60°C)
(For 120 MHz: VDD = 1.2 V to 1.5 V, VP = 2.0 V to 3.5 V, Ta = –20°C to +60°C)
Value
Symbol
Condition
Unit
*3
Min. Typ.*4 Max.
Parameter
(VDD = 1.0 V/ 90 MHz)
(VDD = 1.2 V/ 120 MHz)
—
—
0.5
0.7
1.0
1.4
mA
Power saving
IDDS*2
mode
(VDD = 1.0 V)
(VDD = 1.2 V)
—
—
10
15
100
120
µA
fin
fin
(VDD = 1.0 V to 1.5 V)
(VDD = 1.2 V to 1.5 V)
10
10
—
—
90
120
MHz
OSCIN
fOSC
—
5
–
20
MHz
fin
Vfin
—
–4.0
–
–
dBm
OSCIN
VOSC
—
–4.0
–
–
dBm
Supply current
Active Mode
Power saving current
Operating frequency
Input sensitivity
Input voltage
Input current
IDD*1
Except for
fin and
OSCIN
“H” level
VIH
—
VDD −
0.2
–
–
“L” level
VIL
—
–
–
0.2
Except for
fin, OSCIN
and TEST
“H” level
IIH
VIN = VDD
–
–
+1.0
“L” level
IIL
VIN = GND
–1.0
–
–
Except for
OSCOUT
“H” level
VOH
IOH = –0.3 mA
VDD –
0.2
–
–
“L” level
VOL
IOL = 0.3 mA
–
–
0.2
“H” level
VOHP
IOHP = –1.0 mA
VP –
0.2
–
–
“L” level
VOLP
IOLP = 1.0 mA
–
–
0.2
Ioff
VOUT = GND to VP
–100
–
100
Output voltage
DO
High impedance
DO
cutoff current
V
µA
V
V
nA
*1: Conditions; fin = 90MHz or 120MHz, 16.0MHz crystal between OSCIN and OSCOUT, Inputs except for fin, OSCIN
and TEST are grounded, Outputs are opened.
*2: Conditions; PS = Low, Inputs are grounded except for fin, OSCIN and TEST. Outputs are opened.
*3: Condition; Ta = 25°C
*4: Condition; Ta = –20°C to +60°C
6
MB15C03
■ FUNCTIONAL DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M x N) + A] x fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
: Preset divide ratio of binary 12-bit programmable counter (5 to 4,095)
A
: Preset divide ratio of binary 6-bit swallow counter (0 to 63)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
M
: Preset modulus of dual modulus prescaler (64)
2. Circuit Description
(1) Intermittent operation
The intermittent operation of the MB15C03 refers to the process of activating and deactivating its internal circuit
thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the power
saving state, however, the phase relation between the reference frequency (fr) and the programmable frequency
(fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may
cause the phase comparator to generate an excessively large error signal, resulting in an out-of-synth lock
frequency.
To preclude the occurrence of this problem, the MB15C03 has an intermittent mode control circuit which forces
the frequencies into phase with each other when the IC is reactivated, thus minimizing the error signal and
resultant lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting
pin PS high provides the normal operation mode and setting the pin low provides the power saving mode. The
MB15C03 behavior in the active and power saving modes is summarized below.
Active mode (PS = “H”)
All MB15C03 circuits are active and provide the normal operation.
Power saving mode (PS = “L”)
The MB15C03 stops any circuits that consume power heavily as well as cause little inconvenience when
deactivated and enters the low-power dissipation state. DO and LD pins take the same state as when the PLL
is locked. DO pin becomes a high-impedance state.
Applying the intermittent operation by alternating the active and power saving modes, and also forcing the phases
of fr and fp to synchronize when it switches from stand by to active modes, the MB15C03 can keep the power
dissipation of its entire circuitry to the minimum.
7
MB15C03
(2) Programmable divider
The fvco input through fin pin is divided by the programmable divider and then output to the phase comparator
as fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable
counter, and a controller which controls the divide ratio of the prescaler.
Divide ratio range:
Prescaler : M = 64, M + 1 = 65
Swallow counter : A = 0 to 63
Programmable counter : N = 5 to 4095
The MB15C03 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable
counters must satisfy the relationship N > A.
The total divide ratio of the programmable divider is calculated as follows:
Total divide ratio = (M+1) x A + M x (N-A) = M x N + A = 64 x N + A
When N is set within 5<N<63, the possible divide ratio A of the swallow counter can take values 0<A<N-1
because N must be greater than A. For example, 0<A<19 is allowed when N = 20 but 20<A<63 is not allowed
in that case. Consequently, N>64 must be satisfied for the total divider to be set within 0<A<63.
The fp and fin have the following relation:
fp = fin / (64 x N + A)
(3) Programmable reference divider
The programmable reference divider divides the reference oscillation frequency (fosc) from the crystal oscillator
connected between OSCIN and OSCOUT pins or from the external oscillator input taken in directly through OSCIN,
pin and then, sends the resultant fr to the phase comparator. It consists of a 14-bit binary programmable reference
counter. When the output from the external oscillator is to be input directly to OSCIN pin, the connection must
be AC coupled and OSCOUT pin is left open. Also, to prevent OSCOUT from malfunctioning, its traces on the
printed circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of any form
of load.
The following divider is used:
Programmable reference counter : R = 5 to 16383
The fr and fosc have the following relation:
fr = fosc / R
(4) Phase comparator
The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates
an error signal that is proportional to phase difference. The outputs from the phase comparator include DO which
takes on one of the three states, namely, “L” (low), “H” (high), and “Z” (high impedance), and is sent to the LPF
LD which indicates the PLL lock or unlock states.
(a) Phase comparator
The phase comparator detects the phase error between fr and fp, then generates an error signal that is
proportional to the phase error. The roles of the fr and fp supplied to the phase comparator may be reversed
by switching the logical input level of pin FC. This inverts the logical level of the DO output. The logical level
of DO output may be selected according to the characteristics of the external LPF and the VCO. (Refer to
Table 1.)
8
MB15C03
Table.1 Phass comparator inputs/output relationships
FC
“L”
“H”
fr > fp
H
L
fr = f p
Z
Z
fr < f p
L
H
(b) Phase comparator input/output waveforms
The phase comparator outputs logic levels summarized in Table 1, according to the phase error between fr
and fp.
The pulse width of the phase comparator outputs are identical and equal to the phase error between fr and
fp as shown in Figure 1.
Figure 1 Phase comparator input/output waveforms
fr
fp
When FC = “L”
DO
High Z
When FC = “H”
DO
High Z
High Z : High impedance state
9
MB15C03
(c) Lock detector
The lock detector detects the lock and unlock states of the PLL. The lock detector outputs “H” when the PLL
enters the lock state and outputs “L” when the PLL enters the unlock state as shown in Figure 2. When PS
= “L”, the lock detector outputs “H” compulsorily.
Figure 2 Phase comparator input/output waveforms (lock detector)
fr
fp
LD
10
MB15C03
3. Setting the Divide Ratio
(1) Serial data format
The format of the serial data is shown is Figure 3. The serial data is composed of control bits and divide ratio
setting data. The contorl bits select the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits
for the programmable counter) and control bits as shown in Figure 3.1. In case of the programmable reference
divider, the serial data consists of 14 bits and 2 control bits as shown in Figure 3.2.
The control bits are set to:
C0 = C1= 0
C0 = 0, C1 = 1
for the programmable divider
for the programmable reference divider.
Figure 3 Serial data format
MSB
LSB
Direction of data input
C
0
C
1
A
0
A
1
A
2
A
3
A
4
A
5
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
(=0) (=0)
Swallow counter
Programmable counter
Control bit
Figure 3.1 Divide ratio for the programmable divider
LSB
MSB
Direction of data input
C
0
C
1
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
(=0) (=1)
Programmable reference counter
Control bit
Figure 3.2 Divide ratio for the programmable reference divider
(2) The flow of serial data
Serial data is received via data pin in synchronization with the clock input and loaded into shift register which
contains the divide ratio setting data and into the control register which contains the control bit. The logical
product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the
enable input of the latches. Accordingly, when LE is set high, the latch for the divider identitied by the control bit
is enabled and the divide ratio data from the shift register is loaded into the selected counter(s).
11
MB15C03
Figure 4 The flow of serial data
Programmable
reference divider
14-bit binary programmable reference counter
14
14-bit latch
AND
14
Data
18-bit shift register
C*
Clock
LE
18
18-bit latch
AND
6
Prescaler
12
Programmable
divider
6-bit binary swallow counter 12-bit binary programmable
counter
* : Control register
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table.2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of
Table.2.2 represent the divide ratio of programmable counter. The control bit is set to 0.
Table. 2 Divide ratio for the programmable divider
Table.2.1 Swallow counter divider A
Table.2.2 Programmable counter divider N
Divide
ratio
(A)
A
0
A
1
A
2
A
3
A
4
A
5
Divide
ratio
(N)
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
0
0
0
0
0
0
0
5
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
6
0
1
1
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
63
1
1
1
1
1
1
4095
1
1
1
1
1
1
1
1
1
1
1
1
Note: Less than 5 is prohibited.
12
MB15C03
(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is
set to 1.
Table.3 Divide ratio for the programmable reference divider
Divide
ratio
(R)
R
0
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
5
1
0
1
0
0
0
0
0
0
0
0
0
0
0
6
0
1
1
0
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note: Less than 5 is prohibited.
(5) Setting data input timing
The MB15C03 uses 20 bits of serial data for the programmable divider and 16 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial
data bits are effective.
To set the divide ratio for the MB15C03 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t1 (≥ 0.5 µs): Data setup time
t2 (≥ 0 5 µs): Data hold time
t4 (≥ 0.5 µs): LE setup time to the rising edge of last clock
t3 (≥ 0.5 µs): Clock pulse width
t5 (≥ 0.5 µs): LE pulse width
13
MB15C03
Figure 5 Serial data input timing
Data
Clock
LE
t2
t3
t4
t1
t5
Since the divide rations are unpredictable when the MB15C03 is turned on, it is necessary to initialize the divide
ratio for both dividers at power-on time. As shown in Figure 6, after setting the divide ratio for one of the dividers
(e.g., programmable reference divider), set LE to “H” level before setting the divide ratio for the other divider
(e.g., programmable divider). To change the divide ratio of one of the dividers after initialization, input the serial
data only for that divider (the divide ratio for the other divider is preserved).
Figure 6 Inputting serial data (Setting divisors)
Data
Serial data for programmable
reference divider
16 clocks
C
Serial data for programmable
divider
C
20 clocks
Clock
LE
* : Control bit(2 bits)
14
MB15C03
■ TYPICAL CHARACTERISTIC CURVES
1. fin Input Sensitivity Characteristics
fin input frequency vs. Input sensitivity
0.0
Ta = +25°C
Input sensitivity (dBm)
–10.0
–20.0
–30.0
–40.0
VDD = 1.0 V
VDD = 1.2 V
VDD = 1.5 V
–50.0
–60.0
0
100
200
300
400
500
600
700
800
900
1000
fin input frequency (MHz)
2. OSCIN Input Sensitivity Characteristics
OSCIN input frequency vs. Input sensitivity
0.0
Ta = +25°C
Input sensitivity (dBm)
–10.0
–20.0
–30.0
–40.0
VDD = 1.0 V
VDD = 1.2 V
VDD = 1.5 V
–50.0
–60.0
0
50
100
150
200
250
300
350
400
450
500
OSCIN input frequency (MHz)
15
MB15C03
3. fin Power Supply Voltage Dependency
Power supply voltage vs. fin input frequency
1000
Ta = +25°C
Vfin = –4.0 (dBm)
900
fin input frequency (MHz)
800
700
600
500
400
300
200
100
0
0.9
1.0
1.1
1.2
1.3
1.5
1.4
1.6
1.7
1.8
Power supply voltage (V)
4. OSCIN Power Supply Voltage Dependency
Power supply voltage vs. OSCIN input frequency
500
Ta = +25°C
Vfin = –4.0 (dBm)
450
OSCIN input frequecy (MHz)
400
350
300
250
200
150
100
50
0
0.9
1.0
1.1
1.2
1.3
1.4
Power supply voltage (V)
16
1.5
1.6
1.7
1.8
MB15C03
5. Power Supply Current Characteristics
fin input frequency vs. Power supply current
5.0
Ta = +25°C
4.5
4.0
Power supply current (mA)
3.5
3.0
2.5
2.0
1.5
VDD = 1.0 V
VDD = 1.2 V
VDD = 1.5 V
1.0
0.5
0.0
0
100
200
300
400
600
500
800
700
900
1000
fin input frequecy (MHz)
Power supply voltage vs. Power supply current
5.0
Ta = +25°C
4.5
4.0
Power supply current (mA)
3.5
3.0
2.5
2.0
1.5
fin = 90 (MHz)
fin = 120 (MHz)
Vfin = –4.0 (dBm)
1.0
0.5
0.0
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Power supply voltage (V)
17
MB15C03
6. IDD (Lock) Power Supply Voltage Dependency
VDD — IDD
1.6
Ta = +25°C
1.4
1.2
IDD (mA)
1.0
0.8
0.6
0.4
fvco = 50 MHz
fvco = 130 MHz
0.2
0.0
0.9
1.0
1.1
1.2
1.3
1.4
VDD (V)
1.5
1.6
1.7
1.8
VDD
MB15C03
VCO
1000 p
50 Ω
LPF
18
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1000 p
50 Ω
VP
SG
OSCIN = 16.0 MHz
(0.4 VP – P)
MB15C03
7. DO (Chargepump) Power Supply Voltage Dependency
IOL (DO) — VOL (DO)
3.5
VP = 3.0 V, Ta = +25°C
3.0
VOL (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
IOL (mA)
12
14
16
18
20
IOH (DO) — VOH (DO)
3.5
VP = 3.0 V, Ta = +25°C
3.0
VOH (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
–2
–4
–6
–8
–10
IOH (mA)
–12
–14
–16
–18
–20
19
MB15C03
8. Spectrum Waveforms
ATTEN 10 dB
RL 0 dBm
∆MKR -84.50 dB
25.0 kHz
UAUG 0
10 dB/
• LOCK Frequency: 130.0 MHz
(fr = 25 kHz)
• V DD = 1.2 V, V p = 3.0 V
Ta = +25˚C
∆MKR
D 25.0 KHz
S -84.50 dB
CENTER 130.0000 MHz
* RBW 1.0 kHz
UBW 1.0 kHz
ATTEN 10 dB
RL 0 dBm
UAUG 50
10 dB/
SPAN 200.0 kHz
* SWP 1.00 s
∆MKR -68.50 dB
1.97 kHz
• LOCK Frequency: 130.0 MHz
(fr = 25 KHz)
• V DD = 1.2 V, V p = 3.0 V
Ta = +25˚C
∆MKR
D 1.97 kHz
S -68.50 dB
CENTER 130.00000 MHz
* RBW 100 Hz
UBW 100 Hz
SPAN 20.00 kHz
* SWP 3.00 s
• Mesurement circuit
DO
VT (to VCO)
1.5 kΩ
1.5 kΩ
6800 pF
20
4700 pF
68000 pF
*VCO : KV = 4.635 MHz/v
MB15C03
9. Lock-up Time
• LOCK Frequency: 131.0 MHz to 124.0 MHz
(fr = 25 kHz)
• V DD = 1.2 V, V P = 3.0 V, Ta = +25˚C
131.0 MHz → 124.0 MHz, within ±1 kHz
• LOCK Frequency: 124.0 MHz to 131.0 MHz
(fr = 25 KHz)
• V DD = 1.2 V, V P = 3.0 V, Ta = +25˚C
124.0 MHz → 131.0 MHz, within ±1 kHz
3.10 ms
3.70 ms
∆MKr x: 3.10000214 ms
y: - 6.99991 MHz
A euts N/A
∆MKr x: 3.70000010 ms
y: 7.00041 MHz
124.0050
MHz
131.0050
MHz
2.00
kHz/div
2.00
kHz/div
123.9950
MHz
130.9950
MHz
0 s
10.0000000 ms
0 s
A euts N/A
10.0000000 ms
• LOCK Frequency: 130.0 MHz (fr = 25 kHz)
• V DD = 1.2 V, V P = 3.0 V, Ta = +25˚C
PS ON → 130.0 MHz, within ±1 kHz
2.20 ms
∆MKr x: 2.19999981 ms
y: 130 Hz
A euts N/A
130.0050
MHz
2.00
kHz/div
129.9950
MHz
0
PS
s
8.0000000 ms
1V
0V
21
MB15C03
■ ORDERING INFORMATION
22
Part number
Package
MB15C03PFV
16-pin, Plastic SSOP
(FPT-16P-M05)
Remarks
MB15C03
■ PACKAGE DIMENSION
* : These dimensions do not include resin protrusion.
16-pin, plastic SSOP
(FPT-16P-M05)
+0.20
* 5.00±0.10(.197±.004)
1.25 –0.10
+.008
.049 –.004
(Mounting height)
0.10(.004)
INDEX
*4.40±0.10
(.173±.004)
0.65±0.12
(.0256±.0047)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
+0.10
0.22 –0.05
+.004
.009 –.002
5.40(.213)
NOM
6.40±0.20
(.252±.008)
"A"
+0.05
0.15 –0.02
+.002
.006 –.001
Details of "A" part
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
Dimensions in mm (inches)
23
MB15C03
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3753
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
Fax: (408) 922-9179
Customer Response Center
Mon. – Fri.: 7 am – 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
http:.//www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281 0770
Fax: (65) 281 0220
http://www.fmap.com.sg/
F9710
 FUJITSU LIMITED
24
Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.