E2U0053-28-81 ¡ Semiconductor MSM7728 ¡ Semiconductor This version: Aug. 1998 MSM7728 Previous version: Apr. 1997 Single Rail Linear CODEC GENERAL DESCRIPTION The MSM7728 is a single-channel linear CODEC CMOS IC for voice signals that contains filters for A/D and D/A conversions. Designed especially for a single-power supply and low-power applications, the device is optimized for applications for the analog interfaces of audio signal processing DSPs and digital wireless systems. The analog outputs include the speaker drive output, earphone drive output and ringer output. Therefore, the sound interface can be configured with a few external circuits. FEATURES • Single power supply : 2.5 V to 3.6 V • Low power consumption Operating mode : 36 mW Typ. Power down mode : 0.003 mW Typ. • Digital signal input/output interface : 14-bit serial code in 2's complement format • Transmission clock frequency : 112 kHz min., 2048 kHz max. • Filter characteristics : Complies with ITU-T Recommendation G.714 • Built-in PLL eliminates a master clock • Built-in PB tone signal generator • Built-in service tone generator • Built-in ringer tone generator • General latch output: 1 bit • Both transmit and receive gain adjustable by external control • Receive interface: Speaker direct drive output Earphone interface output : 600 W, 1 mW max. Ringer output : 70 nF, 4 VPP • Transmit gain adjustable using an external resistor • Transmit microphone amplifier is eliminated by the gain setting of a maximum of 36 dB. • Built-in reference voltage supply • Serial 8-bit processor interface • Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name: MSM7728GS-K) 1/23 ¡ Semiconductor MSM7728 BLOCK DIAGRAM CODEC MAO MAIN – + SW1 VOL1 RC LPF 8th BPF 14 BIT ADCONV PCMOUT TCONT SYNC AUTO ZERO BCLK VOL2 SG GEN SGC 5th LPF 14 BIT DACONV VR GEN SPK PLL SW 2 SW 4 SW CONTROL – + SPKN LA VOL CONTROL – + EAR EAR TOUT SW 3 Tone GEN SW 5 VOL3 PB Tone SERVICE Tone SW 6 RINGN VOL4 POWER-DOWN CONTROL WRN RDN MCU INF. CDOUT CDIN DCLK LED RINGP PCMIN RTIM – + SPKP RCONT RINGER Tone RSTN VDD AG DG 2/23 ¡ Semiconductor MSM7728 PIN CONFIGURATION (TOP VIEW) SPKP 1 30 AG SPKN 2 29 NC EAR 3 28 NC RINGP 4 27 SGC RINGN 5 26 MAO TOUT 6 25 MAIN LED 7 24 NC LA 8 23 VDD NC 9 22 NC RDN 10 CDOUT 11 21 20 NC RSTN WRN 12 19 SYNC DCLK 13 18 BCLK CDIN 14 17 PCMOUT DG 15 16 PCMIN NC: No connection 30-Pin Plastic SSOP 3/23 ¡ Semiconductor MSM7728 PIN AND FUNCTIONAL DESCRIPTIONS VDD Power supply pin for 2.5 to 3.6 V (Typically 3.0 V). AG Analog signal ground. DG Ground pin for the digital signal circuits. This ground is separated from the analog signal ground in this device. The DG pin must be connected to the AG pin on the printed circuit board. SGC Bypass capacitor pin for generating the signal ground voltage level. Insert a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and the SGC pin. MAIN, MAO Transmit microphone input and level adjustment. MAIN is connected to the inverting input of the op-amp, and MAO is connected to the output of the op-amp. This amplifier can set up a gain to a maximum of 36dB by using an external resistor. Level adjustment should be performed in a way below. A transmit level of +6, 0, –6, or –12dB can be selected using control data from the processor interface. When CODEC is turned off, the MAO output goes high impedance. R2 C1 Microphone input MAO MAIN R1 – + R1 : variable R2 > 20 kW C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1) (F) Gain = R2/R1 < 63 SG 4/23 ¡ Semiconductor MSM7728 SPKP, SPKN These pins are used for speaker driving. The SPKN output is reversed in phase against the SPKP output when the gain is 1. The receive output signal amplitude is 2.2VPP at maximum. These outputs swing around the SG potential (signal ground potential, VDD/2) and can drive the minimum 0.6kW load in pushpull driving mode. The maximum output amplitude is 4.4VPP in pushpull driving mode (a load is inserted between SPKN and SPKP). Control data from the processor interface allows selecting the D/A conversion output, PB tone output, or service tone output and also can provide a level control and mute control. When SPK is turned off, the SG potential is output with high resistance. EAR Analog output for external accessary circuit. This output swings around the SG potential and can drive the minimum 0.6kW against the SG potential. Control data from the processor interface allows selecting the D/A conversion output, PB tone output, or service tone output and also can provide a level control and mute control. When EAR is turned off, the SG potential is output with high resistance. BCLK Shift clock signal input for PCMIN and PCMOUT. The frequency is equal to the data signaling rate. SYNC Synchronizing signal input. In the transmit section, the PCM output signal from the PCMOUT pin is output synchronously with this synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section. In the receive section, 14 bits required are selected from serial input of PCM signals on the PCMIN pin by the synchronizing signal. Signals in the receive section are synchronized by this synchronizing signal. This signal must be synchronized in phase with the BCLK. When this signal frequency is 8 kHz, the transmit and receive paths have the frequency characteristics specified by ITU-T G. 714. The frequency characteristics for 8 kHz are specified in this data sheet. For different frequencies of the SYNC signal, the frequency values in this data sheet should be translated according to the following equation: Frequency values described in the data sheet ¥ the SYNC frequency values to be actually used 8 kHz 5/23 ¡ Semiconductor MSM7728 PCMIN PCM signal input. A serial PCM signal input to this pin is converted to an analog signal synchronously with the SYNC signal and BCLK signal. The data signaling rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal. The PCM signal is latched into an internal register when shifted by 14 bits. The top of the data (MSD) is identified at the rising edge of SYNC. The input signal should be input in the 14-bit 2's complement format. The MSD bit represents the polarity of the signal with respect to the signal ground. PCMOUT PCM signal output. The PCM output signal is output starting with MSD in sequential order, synchronously with the rising edge of the BCLK signal. MSD may be output at the rising edge of the SYNC signal, depending on the timing between BCLK and SYNC. This pin is in a high impedance state except during 14-bit PCM output. It is also high impedance when the CODEC is turned off. A pull-up resistor must be connected to this pin, because its output is configured as an open drain. The output coding format is in 14-bit 2's complement. The MSD represents a polarity of the signal with respect to the signal ground. Table 1 Input/Output Level PCMIN/PCMOUT MSD +Full scale 0 1 1 1 1 1 1 1 1 1 1 1 1 1 +1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 –1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 –Full scale 1 0 0 0 0 0 0 0 0 0 0 0 0 0 6/23 ¡ Semiconductor MSM7728 WRN, RDN, DCLK, CDIN, CDOUT Serial control ports for microcontroller interface. Writing data to 8-bit control registers allows controling the transmit speech path/receive speech path mute, transmit speech path/receive speech path level, PB tone, service tone, and ringer. WRN is the write control signal input, RDN is the read control signal input, DCLK is the clock signal input for data shift, CDIN is the control data input, CDOUT is the control data output. When reset (RSTN=0), the control registers are reset to the initial values as described in "Control Data Description". The initial values remains unchanged until control data is written after reset. Writing of control data: When WRN is at digital "0", data that is entered in CDIN is shifted at the rising edge of the DCLK signal pulse and is latched in an internal control register. Reading of control data: When RDN is at digital "0", control data is output from CDOUT at the rising edge of a DCLK signal pulse. See Figure 2 for write and read timings. RINGP, RINGN Ringer (sounder) drive outputs. The sounder can be structured by putting a piezo-electric type sounding body (equivalent capacitance: less than 70nF) between RINGP and RINGN. LED Ringer digital level output. This pin is used for LED blinking synchronous with the ringer. LA General latch output. This output is used as a control signal for a peripheral circuit because this output can be set to digital "0" or "1" by writing data from a microcontroller interface. TOUT PB tone/service tone output. When SW6 is in the ON state, tone is output. The output resistance of this pin is approximately 10kW, which should be taken into account when using it externally. RSTN Control register reset signal input. When this pin is set to digital "0" level. All control registers are reset to the initial values. Be sure to reset the control registers after turning on the power. 7/23 ¡ Semiconductor MSM7728 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD AG = DG = 0 V –0.3 to +7.0 V Analog Input Voltage VAIN AG = DG = 0 V –0.3 to VDD + 0.3 V Digital Input Voltage VDIN AG = DG = 0 V –0.3 to VDD + 0.3 V Storage Temperature TSTG — –55 to +150 °C Power Supply Voltage RECOMMENDED OPERATING CONDITIONS Parameter Min. Typ. Max. Unit Symbol Condition Power Supply Voltage VDD — 2.5 3.0 3.6 V Operating Temperature Ta — –30 +25 +85 °C — — 1.4 VPP — VDD V Analog Input Voltage VAIN High Level Input Voltage VIH Low Level Input Voltage VIL Clock Frequency FC Sync Pulse Frequency Gain = 1 SYNC, BCLK, PCMIN, WRN, RDN, DCLK, CDIN, RSTN 0.45 ¥ VDD 0.16 ¥ 0 — BCLK 14 ¥ Fs — 128 ¥ Fs kHz FS SYNC 4.0 8.0 12 kHz Clock Duty Ratio DC BCLK 40 50 60 % Digital Input Rise Time tIr SYNC, BCLK, PCMIN, WRN, — — 50 ns Digital Input Fall Time Sync Signal Timing VDD V tIf RDN, DCLK, CDIN, RSTN — — 50 ns tXS BCLKÆSYNC, See Fig.1 100 — — ns tSX SYNCÆBCLK, See Fig.1 100 — — ns High Level Sync Pulse Width *1 tWSH SYNC, See Fig.1 1 BCLK — — — Low Level Sync Pulse Width *1 tWSL SYNC, See Fig.1 1 BCLK — — — PCMIN Setup Time tDS Refer to Fig.1 100 — — ns PCMIN Hold Time tDH Refer to Fig.1 100 — — ns RDL Pull-up resistor 0.5 — — kW CDL — — — 100 pF Digital Output Load DCLK Pulse Width WRN Timing WRN Period tWCL DCLK Low width, See Fig.2 50 — — tWCH DCLK High width, See Fig.2 50 — — tWR1 DCLKÆWRNL, See Fig.2 50 — — tWR2 WRNLÆDCLK, See Fig.2 50 — — tWR3 DCLKÆWRNH, See Fig.2 50 — — tWR4 WRNHÆDCLK, See Fig.2 50 — — 9DCLK — — PWRN — ns ns ns — *1 For example, the minimum pulse width of SYNC is 488 ns when the frequency of BCLK is 2048 kHz. 8/23 ¡ Semiconductor MSM7728 RECOMMENDED OPERATING CONDITIONS (Continued) Parameter RDN Timing RDN Period Symbol Min. Typ. Max. tRD1 DCLKÆRDNL, See Fig.2 50 — — tRD2 RDNLÆDCLK, See Fig.2 50 — — tRD3 DCLKÆRDNH, See Fig.2 50 — — tRD4 RDNHÆDCLK, See Fig.2 50 — — 9DCLK — — Condition PRDN — Unit ns ns — CDIN Setup Time tCDS See Fig.2 50 — — CDIN Hold Time tCDH See Fig.2 50 — — Analog Input Allowable DC Offset Voff Transmit gain stage, Gain = 0 dB –100 — +100 mV Transmit gain stage, Gain = 20 dB –10 — +10 mV Allowable Jitter Width — SYNC, BCLK — — 1000 ns 20 — 100 tXD1 CL = 50 pF + 1 LSTTL 20 — 100 tXD2 Pull-up resistor = 500 W 20 — 100 20 — 100 50 — — 50 — — tSD PCM Data Output Delay Time tXD3 Control Data Output Delay Time tCD1 tCD2 — ns ns ns 9/23 ¡ Semiconductor MSM7728 ELECTRICAL CHARACTERISTICS DC and Digital Interface Characteristics (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Parameter Power Supply Current Symbol Min. Typ. Max. VDD = 3.6 V — 20 — mA VDD = 3.0 V — 12 — mA — 70 200 mA — VDD V Condition IDD1 Operating mode, No signal IDD2 Power-off mode High Level Input Voltage VIH Low Level Input Voltage VIL High Level Input Leakage Current IIH Low Level Input Leakage Current IIL Digital Output Low Voltage VOL Digital Output High Voltage VOH 0.45 ¥ SYNC, BCLK, PCMIN, WRN, RDN, CDIN, DCLK, RSTN VDD 0.16 ¥ Unit 0.0 — — — — 2.0 mA — — — 0.5 mA 0.0 0.2 0.4 V PCMOUT pull-up resistor = 500 W LA, LED, CDOUT IOL = 0.4mA LA, LED, CDOUT IOH = 1mA VDD VDD – 0.2 V V Digital Output Leakage Current IO — — — 10 mA Input Capacitance CIN — — 5 — pF Transmit Analog Interface Characteristics (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Min. Typ. Max. Unit Input Resistance RINX MAIN 10 — — MW Output Load Resistance RLGX MAO with respect to SG 30 — — kW Output Load Capacitance CLGX potential — — 30 pF Output Amplitude VOGX –0.7 — +0.7 V –20 — +20 mV Parameter Offset Voltage Symbol VOSGX Condition MAO with respect to SG potential (DC Gain = 1) Receive Analog Interface Characteristics (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Parameter Output Resistance Symbol Condition Min. Typ. ROSP SPKP, SPKN — — 10 W ROER EAR — — 100 W ROTO TOUT Output Load Resistance Max. Unit — 10 — kW RLSP SPKP-SPKN 600 — — W RLER EAR with respect to SG potential 600 — — W Output open Output Load Capacitance CLAO Output Amplitude VOAO SPKP, SPKN, EAR Offset Voltage VOSA SPKP, SPKN, EAR, TOUT with respect to SG potential — — 50 pF –1.1 — +1.1 V –100 — +100 mV 10/23 ¡ Semiconductor MSM7728 AC Characteristics Parameter Overall Frequency Response (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Loss 1 Freq. (Hz) 60 Loss 2 300 Loss 3 1020 Loss 4 2020 Loss 5 Loss 6 Symbol Level Condition (dBm0) 0 Min. Typ. Max. 20 — — –0.2 — +0.4 Analog to Reference value –0.2 — +0.4 3000 –0.2 — +0.4 3400 0 — 1.6 Analog Loss T1 60 20 — — Loss T2 300 –0.15 — +0.2 Transmit Frequency Response Loss T3 1020 (Expected Value) Loss T4 2020 Loss T5 Loss T6 Receive Frequency Response (Expected Value) Overall Signal to Distortion Ratio –0.15 — +0.2 3000 –0.15 — +0.2 3400 0 — 0.8 Loss R1 300 –0.15 — +0.2 Loss R2 1020 Loss R3 2020 Loss R4 Loss R5 –0.15 — +0.2 3000 –0.15 — +0.2 3400 0.0 — 0.8 57.0 — — 57.0 — — 3 SD 2 0 SD 3 SD 4 1020 –10 –30 Analog to Analog *1 VDD = 50.0 — — 32.0 — — 23.0 — — 20.0 — — SD 5 –40 SD 6 –45 SD T1 3 58 — — 0 58 — — –10 58 — — 38 — — SD T2 SD T4 1020 –30 2.7 to 3.3 V *1 SD T5 –40 28 — — SD T6 –45 23 — — SD R1 3 60 — — SD R2 0 60 — — Receive Signal to Distortion Ratio SD R3 –10 60 — — (Expected Value) SD R4 40 — — *1 1020 dB dB Reference value 0 SD 1 Transmit Signal to Distortion Ratio SD T3 (Expected Value) Reference value 0 Unit –30 *1 SD R5 –40 30 — — SD R6 –45 25 — — dB dB dB dB Psophometric filter is used. 11/23 ¡ Semiconductor MSM7728 AC Characteristics (Continued) Parameter Symbol (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Freq. (Hz) GT 1 GT 2 Overall Gain Tracking GT 3 Receive Gain Tracking Transmit Idle Channel Noise (Expected Value) Analog to Analog Min. Typ. Max. –0.4 +0.01 +0.4 0.0 +0.4 –1.0 –0.03 +1.0 GT 5 –55 –1.5 +0.15 +1.5 GT T1 3 –0.3 +0.01 +0.3 –40 –0.3 0.0 +0.3 GT T4 –50 –0.6 –0.03 +0.6 GT T5 –55 –1.2 +0.15 +1.2 GT R1 3 –0.3 –0.06 +0.3 GT R2 –10 1020 dB Reference value –10 1020 Unit Reference value –0.4 –50 GT R3 (Expected Value) –40 Condition GT 4 GT T3 (Expected Value) dB Reference value –40 –0.3 –0.02 +0.3 GT R4 –50 –0.6 –0.02 +0.6 GT R5 –55 –1.2 –0.27 +1.2 — –72 –68 — –76 –74 0.312 0.350 0.393 0.245 0.275 0.309 –0.2 — +0.2 dB –0.2 — +0.2 dB — — 0.6 ms — — 0.325 — — 0.175 — — 0.325 — 0.00 0.125 — 0.12 0.325 TRANS Æ RECV 75 85 — RECV Æ TRANS 70 80 — Nidle T — — Nidle R — — 1020 0 AIN: no signal dB dBmOp Receive Idle Channel Noise (Expected Value) Output Level –10 1020 GT T2 Transmit Gain Tracking Level (dBm0) 3 *2 (Initial value) Output Level (Deviation of Temperature and Power) AV T AVSPK *1 MAO-PCMOUT AVEAR PCMIN-SPKP*3 PCMIN-EAR *3 VDD = 2.5 AV Tt to 3.6 V Ta = –30 AV Rt to +85°C Vrms A to A Absolute Delay Td 1020 tGD T1 500 0 BCLK = 128 kHz Transmit Group Delay tGD T2 600 to 2600 tGD T3 Receive Group Delay Crosstalk Attenuation tGD R1 500 to 2600 tGD R2 CR T CR R 0 *4 2800 2800 1020 0 0 *4 ms ms dB *1 Psophometric filter is used. *2 AVT is the input level to output 0dBm0 pattern. VOL1 0dB setting. AVSPK is the level to be output from SPKP pin when 0dBm0 pattern is input. AVEAR is the level to be output from EAR pin when 0dBm0 pattern is input. *3 VOL2 0dB setting *4 The minimum value of group delay distortion is referenced. 12/23 ¡ Semiconductor MSM7728 AC Characteristics (Continued) Parameter Discrimination Out-of-band Spurious Intermodulation Distortion Power Supply Noise Rejection Ratio (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Freq. Level Condition (Hz) (dBm0) 4.6 kHz to DIS 0 0 to 4000 Hz 72 kHz Symbol S IMD 300 to 0 to V PB –35 dBm0 –4 2fa – fb — –52 –40 dBm0 50 mVPP Measured inband — 30 — High group –27 –22 –19 VOL3 standard Low group –28 –23 –20 High group –16 –11 –8 Low group –17 –12 –9 VOL3 standard –18 –15 –13 –8 –3 –1 –1.5 — +1.5 TOUT Service Tone Output Level PB Acknowledge Tone Frequency Distortion Service Tone Frequency Distortion VOL1 Gain Setting Value V RT SPKP, EAR TOUT DfPB — 1020 0 Gv13 Referenced to 0dB setting Gv21 VOL2 Gain Setting Value Gain Setting Value — +1.5 5 6 7 –6dBsetting –7 –6 –5 –12dBsetting –13 –12 –11 6 7 6dBsetting 5 Gv22 3dBsetting 2 3 4 Gv23 –3dBsetting –4 –3 –2 –6dBsetting Referenced to dB dBV dBV % dB –7 –6 –5 –9dBsetting –10 –9 –8 Gv26 –12dBsetting –13 –12 –11 Gv27 –15dBsetting –16 –15 –14 Gv31 12dBsetting 10.5 12 13.5 8dBsetting 6.5 8 9.5 4dBsetting 2.5 4 5.5 –4dBsetting –5.5 –4 –2.5 –8dBsetting –9.5 –8 –6.5 Gv36 –12dBsetting –13.5 –12 –10.5 Gv37 –16dBsetting –17.5 –16 –14.5 Gv24 1020 0 Gv25 0dB setting Gv32 VOL3 –1.5 6dBsetting DfRT Gv11 Gv12 dB –37.5 SPKP, EAR PB Acknowledge Tone Output Level — — fb = 320 50 kHz 32 4.6 kHz to 100 kHz fa = 470 PSR T 30 0 3400 PSR R Min. Typ. Max. Unit Gv33 Gv34 Gv35 1020 0 Referenced to 0dB setting dB dB 13/23 ¡ Semiconductor MSM7728 Ringing Tone (Fs = 8 kHz, VDD = 2.5 V to 3.6 V, Ta = –30°C to +85°C) Parameter Ringing Tone Output Amplitude Symbol Condition Min. Typ. Max. Unit Sound volume1 Sound volume max. 3.5 — — Sound volume2 730W between Sound volume mid. 1.5 — — Sound volume3 RINGP and RINGN Sound volume sma.1 0.5 — — Sound volume sma.2 0.25 — — Sound volume4 VPP 14/23 , , ¡ Semiconductor MSM7728 TIMING DIAGRAMS CODEC Interface Timing Transmit Timing BCLK 1 tXS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 17 18 19 tSX SYNC tWSL tWSH tSD tXD1 MSD D2 PCMOUT D3 D4 tXD2 D5 tXD3 D6 D7 D8 D9 D10 D11 D12 D13 D14 When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined by tXD1. When tSX < 1/2 • Fc, the Delay of the MSD bit is defined by tSD. Receive Timing BCLK 1 tRS SYNC PCMIN 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tSR tWSL tWSH MSD D2 D3 D4 D5 tDS D6 tDH D7 D8 D9 D10 D11 D12 D13 D14 Figure 1 Basic Timing Diagram Processor Interface Timing DCLK 1 CDIN tWR1 tWCL 2 A2 A1 tWR2 3 A0 4 tCDS B4 tWCH 5 6 tCDH B2 B3 7 B1 8 B0 tWR3 tWR4 WRN PWRN RDN H CDOUT Hi-Z WRITE Mode DCLK 1 CDIN tRD1 WRN H 2 A2 A1 tRD2 3 A0 4 X 5 X 6 X 7 8 X X tRD3 tRD4 PRDN RDN tCD1 CDOUT Hi-Z B4 tCD2 B3 B2 B1 B0 READ Mode Figure 2 Processor Timing Diagram 15/23 ¡ Semiconductor MSM7728 FUNCTIONAL DESCRIPTION Control Data Description The MSM7728 has eight registers to control the analog pass switch, volume, and tone via an external CPU. The data interface consists of 3-bit address data and 5-bit control data in the serial 8-bit format. The register map is as shown below. AD2 AD1 AD0 B4 B3 B2 VOL1 B1 B0 VOL2 Function Read CR0 0 0 0 CR1 0 0 1 CR2 0 1 0 CR3 0 1 1 CR4 1 0 0 PB tone PB tone setting ON/OFF control Disable CR5 1 0 1 Service tone Service tone setting ON/OFF control Disable CR6 1 1 0 Ringer tone Ringer tone setting ON/OFF control Disable CR7 1 1 1 Power ON/OFF Power ON/OFF control Enable VOL3 VOL4 VOL1, VOL2 gain setting Enable VOL3, VOL4 gain setting Enable SW5 SW4 SW3 SW2 SW1 SW ON/OFF control — — — LA Enable SW6 Latch output/SW ON/OFF control Enable Description of Each Register CR0 - - - VOL1, VOL2 control A2 A1 A0 B4 B3 B2 B1 B0 Function 0 0 0 0 0 0dB (standard) VOL1 and VOL2: 0 1 6dB Simultaneous setting 1 0 –6dB Standard after reset 1 1 –12dB is released VOL1 gain setting 0 0 0 0dB (standard) 0 0 1 6dB 0 1 0 3dB 0 1 1 1 0 0 1 0 1 –9dB 1 1 0 –12dB 1 1 1 –15dB VOL2 gain setting Remarks –3dB –6dB 16/23 ¡ Semiconductor MSM7728 CR1 - - - VOL3, VOL4 control A2 A1 A0 B4 B3 B2 B1 B0 Function 0 0 1 0 0 0 0dB (standard) VOL3 and VOL4: 0 0 1 12dB Simultaneous setting 0 1 0 8dB Standard after reset 0 1 1 4dB is released 1 0 0 1 0 1 –8dB 1 1 0 –12dB 1 1 1 VOL3 gain setting Remarks –4dB –16dB 0 0 0 1 Ringer sound Maximum 1 0 volume Small 1 1 1 B1 B0 Middle (standard) Small 2 CR2 - - - SWcontrol A2 A1 A0 0 1 0 B4 B3 B2 Function Remarks 1: SW1 ON, 0: SW1 OFF SW1 to SW5: 1: SW2 ON, 0: SW2 OFF Simultaneous setting 1: SW3 ON, 0: SW3 OFF Standard after reset 1: SW4 ON, 0: SW4 OFF is released 1: SW5 ON, 0: SW5 OFF CR3 - - - SW & latch control A2 A1 A0 B4 B3 B2 0 1 1 0 0 0 B1 B0 Function 0: SW6 OFF, 1: SW6 ON 0: LA=0, 1: LA=1 Remarks SW6 and LA: Simultaneous setting SW6: OFF, LA=0 after reset is released 17/23 ¡ Semiconductor MSM7728 CR4 - - - PB tone control HEX A2 A1 A0 B4 B3 B2 B1 B0 Function 1 0 0 1 0 0 0 0 9 0h PBtone 697Hz, 1209Hz Output destination of 1 0 0 0 1 9 1h PBtone 697Hz, 1336Hz PB tone: 1 0 0 1 0 9 2h PBtone 697Hz, 1477Hz EAR 1 0 0 1 1 9 3h PBtone 697Hz, 1633Hz SPKP 1 0 1 0 0 9 4h PBtone 770Hz, 1209Hz SPKN 1 0 1 0 1 9 5h PBtone 770Hz, 1336Hz PB OFF after reset is 1 0 1 1 0 9 6h PBtone 770Hz, 1477Hz released 1 0 1 1 1 9 7h PBtone 770Hz, 1633Hz 1 1 0 0 0 9 8h PBtone 852Hz, 1209Hz 1 1 0 0 1 9 9h PBtone 852Hz, 1336Hz 1 1 0 1 0 9 Ah PBtone 852Hz, 1477Hz 1 1 0 1 1 9 Bh PBtone 852Hz, 1633Hz 1 1 1 0 0 9 Ch PBtone 941Hz, 1209Hz 1 1 1 0 1 9 Dh PBtone 941Hz, 1336Hz 1 1 1 1 0 9 Eh PBtone 941Hz, 1477Hz 1 1 1 1 1 9 Fh PBtone 941Hz, 1633Hz 0 0 0 0 0 8 0h PBtone OFF Code Remarks CR5 - - - Service tone control A2 A1 A0 B4 B3 B2 B1 B0 1 0 1 HEX Code Frequency Intermittent Time (Note1) Make Time Break Time1 Break Time2 Remarks — Output 0.5sec — destination 0.25sec — of PB tone: — — EAR Continuous — — SPKP Continuous — — SPKN 400Hz/16Hz 1sec 2sec — 400Hz/16Hz 0.5sec • — 1 0 0 0 0 B 0h 400Hz 0.125sec 0.125sec 1 0 0 0 1 B 1h 400Hz 0.5sec 1 0 0 1 0 B 2h 400Hz 0.25sec 1 0 1 0 0 B 4h 400Hz Continuous 1 0 1 0 1 B 5h 1000Hz 1 0 1 1 0 B 6h 2000Hz 1 1 0 0 1 B 9h 1 1 0 1 0 B Ah 1 1 0 1 1 B Bh 400Hz/16Hz 0 0 0 0 0 A 0h Above tones stop 0.032sec 0.032sec — 18/23 ¡ Semiconductor MSM7728 CR6 - - - Ringer tone control A2 A1 A0 B4 B3 B2 B1 B0 1 1 0 HEX Code 1 0 0 0 0 D 0h 1 0 0 0 1 D 1h 1 0 0 1 0 D 2h 1 0 0 1 1 D 3h 1 0 1 0 0 D 4h 1 0 1 0 1 D 5h 1 0 1 1 0 D 6h 1 0 1 1 1 D 7h 1 1 0 0 1 D 9h 1 1 0 1 0 D Ah 1 1 0 1 0 0 0 0 Intermittent Time (Note1) Frequency Make Time Break Time1 Break Time2 1sec 16Hz alternation of 1kHz/1.3kHz 2sec — Output 0.5sec 0.5sec — destination 0.25sec 0.25sec 2.25sec of PB tone: Continuous — — RINGP 1sec 2sec — RINGN 0.5sec 0.5sec — 0.25sec 0.25sec 2.25sec Continuous — — 400Hz Continuous — — 1kHz Continuous — — 1 D Bh 2kHz Continuous — — 0 C 0h Above tones stop Make time Break time1 Make time 16Hz alternation of 2kHz/2.6kHz Remarks Break time2 Make time (Note1) CR7 - - - Power-on/off control A2 A1 A0 B4 B3 B2 B1 B0 1 1 1 Function Remarks 0: CODEC power-off , 1: CODEC power-on All paths enter a 0: SPK power-off , 1: SPK power-on power-down state 0: EAR power-off , 1: EAR power-on after reset is released 0: toneGEN power-off , 1: toneGEN power-on 0: SG/VR/PLL power-off , 1: SG/VR/PLL power-on 19/23 ¡ Semiconductor MSM7728 APPLICATION CIRCUIT +V +3 V MSM7728 Microphone M Speaker Auxiliary output Sounder MAIN PCMOUT MAO PCMIN * SPKP * SPKN * EAR PCM input BCLK PCM shift clock input SYNC 8 kHz SYNC signal input PDN RINGP S PCM output Reset input "1" = Operation "0" = Reset RINGN LED LED LA General latch output 0.1 mF SGC AG 0V DG DCLK WRN RDN CDIN CDOUT Controller 10 mF +3 V 0 to 20 W VDD * The analog output swings at a maximum of ±1.0 V above and below the VDD/2 offset level. 20/23 ¡ Semiconductor MSM7728 APPLICATION INFORMATION Digital pattern for 0 dBm0 The digital pattern for 0 dBm0 is shown below. (SYNC frequency = 8 kHz, signal frequency = 1 kHz) S2 S3 S1 S4 SG S5 S8 S6 Sample No. MSD D2 D3 D4 D5 S7 D6 D7 S1 0 0 1 0 0 0 1 D8 D9 D10 D11 D12 D13 D14 0 1 0 1 0 1 1 S2 0 1 0 1 0 0 1 1 1 0 1 1 1 0 S3 0 1 0 1 0 0 1 1 1 0 1 1 1 0 S4 0 0 1 0 0 0 1 0 1 0 1 0 1 1 S5 1 1 0 1 1 1 0 1 0 1 0 1 0 0 S6 1 0 1 0 1 1 0 0 0 1 0 0 0 1 S7 1 0 1 0 1 1 0 0 0 1 0 0 0 1 S8 1 1 0 1 1 1 0 1 0 1 0 1 0 0 21/23 ¡ Semiconductor MSM7728 NOTES ON USE • To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. • Connect the AG pin and the DG pin as close as possible. Connect them to the system ground with low impedance. • Mount the device directly on the PC board. Do not use an IC socket. If use of an IC socket is unavoidable, use a short lead type socket. • When mounting the device on a frame, use electro-magnetic shielding, if any electromagnetic wave source such as power supply transformers is surrounding the device. • Keep the voltage on the VDD pin not lower than –0.3 V to avoid latch-up that may otherwise occur when power is turned on. • Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power supply to avoid erroneous operation and the degradation of the characteristics of the device. 22/23 ¡ Semiconductor MSM7728 PACKAGE DIMENSIONS (Unit : mm) SSOP30-P-56-0.65-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.19 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 23/23