OKI MSM7502

E2U0023-28-81
¡ Semiconductor
MSM7502
¡ Semiconductor
This version: Aug.
1998
MSM7502
Previous version: Nov. 1996
Multi-Function PCM CODEC
GENERAL DESCRIPTION
The MSM7502, developed especially for low-power and multi-function applications in touchtone telephone sets and digital telephone terminals of digital PBXs, is a single +5 V power supply
CODEC device. The device consists of the analog speech paths directly connectable to a handset,
the calling circuit directly connectable to a piezosounder, the push-button key scanning interface
between push buttons and control processors, the dial tone generator, the m-law/A-law CODEC,
and the processor interface. The functions can be controlled via 8-bit data bus.
For the CODEC of the MSM7502, an MSM7543 is used as a core CODEC, so the MSM7502
provides the available bit clock range wider than the family product MSM6895.
In addition, the MSM7502 performs the greater key interface function and offers the upgraded
side-tone level, receive level, and speaker pre-amplifier output level.
FEATURES
• Single +5 V Power Supply
• Low Power Dissipation
Power ON Mode
: 30 mW Typ. 53 mW Max.
Power Saving Mode
: 2 mW Typ. 5 mW Max.
• In compliance with ITU-T’s companding law
• Transmission clocks
: 64, 128, 256, 512, 1024, 2048 kHz
96, 192, 384, 768, 1536, 1544 kHz
• Built-in PLL
• Built-in Reference Voltage Supply
• Calling Tone Interval
: Controlled by processor
• Calling Tone Combination
: Controlled by processor, 6 modes
• Calling Tone Volume
: Controlled by processor, 4 modes
• Ringing Tone Interval
: Controlled by processor
• Ringing Tone Frequency
: Controlled by processor, 6 modes
• Ringing Tone Level
: Controlled by processor, 4 levels
• Built-in PB Tone Generator
• Built-in Speech path Control Switches
• General Latch Output for External Control : 2 bits
• Watch-dog Timer
: 500 ms
• Key Scanning I/O
Output
: 8 bits
Input
: 8 bits
• Direct Connection to Handset
: 1.2 kW driving available
• Built-in Pre-amplifier for Loud-speaker
• Hand-free Interface
• m-law/A-law Switchable CODEC
• LCD Deflection Angle Voltage
: Controlled by processor, 8 levels
• Package :
80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name : MSM7502GS-BK)
1/35
¡ Semiconductor
MSM7502
BLOCK DIAGRAM
TPAO TPBI MPAI
MPBO MLDYI
TO
CAI
VOL 9
20 dB
TPAI
MPAO MPBI
+
+
–
SW 1
0 dB
SW 2
5.7 dB
SW 7
VOL 3
SW 16
VOL 4
–
AIN
VOL 8
SW 12
m/A
CODEC
+
CAO
PCMOUT
AOUT
–
VOL 10
R1I
PCMIN
PLL
SW 9
0 dB
–
RPO
SW 3
VOL 2
SW 4
–8.7 dB
SW 17
0 dB
SW 14
VOL 7
SW 13
BCLOCK
R-TONE GEN.
400
425
440
450
400*16
400*20
RMI
SW 5
RMO0
–
RMO1
SW 5
SW 10
VOL 6
–
0 dB
SW 6
–3 dB
SW 8
–6.8 dB
SW 18
WRN
RDN
CEN
RESETN
D0 to D7
AD0
AD1
INTT
TIMEN
F-TONE GEN.
1 kHz
–
0 dB
SPI
XSYNC
RSYNC
PB GEN.
PROCESSOR INTF
R2I
VOL 1
S-TONE GEN.
WAMBLE TONE
1000 Hz
800 Hz
400 Hz
Latch
SPO
VOL 5
SW 21
–22 dB
SW 15
VOL 11
SW 11
VOL 12
SW 20
LA
LB
LML
–
VLCD GEN.
SA0
VLCD
SW 19
VOL 13
SA1
SG GEN.
VA
VD
AG
DG
SGT
SGC
KEY INTF
SCANNING OUTPUT
PO0 to PO7
SCANNING INPUT
PI0 to PI7
2/35
¡ Semiconductor
MSM7502
65 DB0
66 DB1
67 DB2
68 DB3
69 DB4
70 DB5
71 DB6
72 DB7
73 AD0
74 AD1
75 WRN
76 RDN
77 CEN
78 RESETN
79 TIMEN
80 INTT
PIN CONFIGURATION (TOP VIEW)
LML 1
64 VD
LA 2
63 PI7
LB 3
62 PI6
VLCD 4
61 PI5
SA1 5
60 PI4
SA0 6
59 PI3
DG 7
58 PI2
AG 8
57 PI1
RMO1 9
56 PI0
RMO0 10
55 NC
RMI 11
54 PO0
SPI 12
53 PO1
NC 13
52 PO2
SPO 14
51 PO3
RPO 15
50 PO4
R2I 16
49 PO5
R1I 17
48 PO6
MLDYI 18
47 PO7
MPBO 19
46 PCMOUT
MPBI 20
45 BCLOCK
MPAO 21
44 XSYNC
NC 22
43 RSYNC
MPAI 23
42 PCMIN
NC 24
NC 40
CAO 39
NC 38
NC 37
SGC 36
NC 35
CAI 34
NC 33
VA 32
TO 31
SGT 30
TPAI 29
NC 28
TPAO 27
TPBI 26
NC 25
41 NC
NC : No connect pin
80-Pin Plastic QFP
3/35
¡ Semiconductor
MSM7502
PIN AND FUNCTIONAL DESCRIPTIONS
LA, LB
General latch outputs for external control.
Statuses of these outputs are controlled via the processor interface. Refer to the description of the
control data for details. These outputs provide the capability to drive one TTL.
DG
Digital Ground.
DG is separated from the analog ground AG inside the device. But, DG should be connected as
close to the AG pin on PCB as possible.
AG
Analog Ground.
SA0, SA1
Sounder (calling tone) driving outputs.
The output signal on SA1 is inverted against the signal on SA0. The sounder circuit can be easily
configured by connecting a piezo-sounder between SA0 and SA1. Through processor control, the
calling tone volume is selectable from four levels and one of six tone combinations is selectable.
Initially, the ringing tone volume is set at a maximum and the tone combination is set at a 16 Hz
Wamble tone by a combination of 1 kHz and 1.3 kHz. If these pins are used with no-load, tone
volume cannot be controlled. When tone volume control is required, a load resistor must be
connected between SA0 and SA1.
4/35
¡ Semiconductor
MSM7502
RMI, RMO0, RMO1
Receive main amplifier input and outputs.
RMI is the inverted input and RMO0 and RMO1 are the outputs of the receive main amplifier.
The output signal on RMO1 is inverted against RMO0 by a gain 1 (0 dB), so the earphone of a
handset is directly connected between RMO0 and RMO1. During the system power down, the
RMO0 and RMO1 outputs are in a high impedance state. The receive main amplifier gain is
determined by a resistor connected between RPO and RMI, and a resistor connected between
RMI and RMO0. The receive main amplifier gain varies between 0 and +20 dB in effect. A piezoreceiver with an impedance greater than 1.2 kW is available.
If the adjusting of receive path frequency characteristics is required, insert the following circuit
for adjustment. During the whole system Power ON, the speech path from RMI to RMO0 and
RMO1 is disconnected and the output of RMO0 and RMO1 is at the SG level (VA/2). The speech
path is provided by processor control.
A circuit example for adjustment of frequency characteristics
RPO
RMI
R1
C1
RMO0
R2
C2
Main amplifier gain without capacitors
G=
R2
R1
5/35
¡ Semiconductor
MSM7502
SPI
Addit0ion input of speaker amplifier.
The typical gain between SPI and SPO is 0 dB. But, the 2-stage gain amplifier allows to set up a
gain between 0 dB and –18 dB in a 6 dB step, or a gain between 0 dB and –28 dB in a 4 dB step
through processor control. The input resistance of SPI is typically 20 kW to 150 kW (it varies by
gain setting).
SPO
Output of pre-amplifier for speaker.
Since the driving capability is 2.4 VPP for the load of 20 kW, SPO can not directly drive a speaker.
During the whole system power down mode, SPO is at an analog ground level. During the whole
system power on mode, SPO is in a non-signal state (SG level), and a receive voice signal, R-tone,
F-tone, hold acknowledge tone, PB signal acknowledge tone, and sounder tone are output from
the speaker by processor control.
When the speaker is used as a sounder, the sounder tone is output via the SPO pin by connecting
the SPI input with the sounder output (SA0 or SA1). In addition, when the AD-converted
sounder tone is sent from the main device, the sounder tone is output via the SPO pin since the
CAO pin for CODEC output is internally connected.
R1I, R2I, RPO
R1I and R2I are for the inputs and RPO is for the output of the receive pre-amplifier.
Normally, R1I is connected via an AC-coupling capacitor to the CODEC analog output (CAO),
and R2I is used as the mixing signal input pin.
The typical gain between R1I and PRO is –6 dB. Through processor control, gains are variable
from –14 dB to 0 dB in 2 dB steps. In addition, the receive pad can control the gain of –9, –6, –3,
or 0 dB. The gain between R2I and RPO is fixed to 0 dB.
During the whole system power-on mode, the RPO output is in non-signal state, and speech
signal, R-tone, F-tone, PB acknowledge tone, side tone signal are output by processor control.
During the whole system power-down mode, the RPO output is the analog ground level.
The input resistance of R1I is typically between 20 kW and 100 kW (it varies by gain setting). The
input resistance of R2I is typically 20 kW.
MLDYI
Hold tone signal input.
For example, the output of external melody IC is connected to this pin. Through processor
control, the signal applied to MLDYI is output from the TO output pin as a hold tone on the
transmit path, and from the SPO output pin as a hold acknowledge tone on the receive path. The
typical gain between MLDYI and TO is –2 dB. Through processor control, a gain between –2 dB
and –11 dB is also settable at 3 dB steps. The typical gain between MLDYI and SPO is –3 dB.
Through processor control, a gain between –3 dB to –31 dB is also settable at 4 dB steps. MLDYI
is a high impedance input, so insert an about 100 kW bias resistor between MLDYI and SGT.
6/35
¡ Semiconductor
MSM7502
TPBI, TO
TPBI is the input and TO is the output of the transmit pre-amplifier (B).
When the handset is used, TPBI is connected to the transmit pre-amplifier (A) output pin (TPAO).
If adjustment of frequency characteristics on the transmit path is required, insert a circuit for
adjustment of characteristic between TPAO and TPBI. Through processor control, the signal
applied to this pin is output via the TO pin on the transmit path and its side tone via the RPO pin.
During the whole system power down mode, TO is at an analog ground level. The typical gain
between TPBI and TO is +17.7 dB. Through processor control, a gain between +17.7 dB and +8.7
dB is also settable at 3 dB steps.
The typical gain between TPBI and RPO is +3.0 dB. Through processor control, a gain between
–9 dB and +9 dB is variable in 3 dB steps. Changing the gain between TPBI and TO may change
the gain between TPBI and RPO. TPBI is a high impedance input, so insert an about 100 kW
resistor between TPBI and SGT.
A circuit example for adjustment of frequency characteristics
TPAO
TPBI
R3
C3
SGT
R4
C4
MPAI, MPAO
Handfree microphone pre-amplifier (A) input and output.
MPAI is the input and MPAO is the output. The speech path between MPAI and MPAO is always
active regardless of processor control. During the whole system power saving mode, MPAO is
at an analog ground level. The gain between MPAI and MPAO is typically +20 dB. Through
processor control, gains between +14 dB and +11 dB are also settable. MPAI is a high impedance
input, so insert an about 100 kW between MPAI and SGT.
MPBI, MPBO
The handfree microphone (B) input and output.
MPBI is the inverted input and MPBO is the output. With an external resistance, the amplifier
gain is adjusted in the range between –25 dB and +25 dB. A signal on the MPBO is output via the
TO pin through processor control. During the whole system power down mode, MPBO is at an
analog ground level. The gain between MPBO and TO is fixed to 0 dB.
7/35
¡ Semiconductor
MSM7502
TPAI, TPAO
The transmit pre-amplifier input and output.
TPAI is the input and TPAO is the output. TPAI should be connected to the microphone of
handset via an AC-coupling capacitor if the DC offset appears at a transmit signal (offset from
SGT). The transmit path from TPAI to TPAO is always active regardless of processor control.
During the whole system power down mode, TPAO is at an analog ground level. The gain
between TPAI and TPAO is fixed to 20 dB.
SGT
Transmit path signal ground.
SGT outputs half the supply voltage. During the whole power down mode, SGT is in a high
impedance state.
SGC
Bypass capacitor connecting pin for signal ground level.
Insert a 0.1 mF high performance capacitor between SGC and AG.
VA, VD
+5 V power supply.
VA is for an analog circuit and VD is for digital supply. Connect both VA and VD to the +5 V
analog path of the system.
CAI, CAO
CODEC analog input and output.
CAI is the analog input of CODEC to be connected to the TO pin. If the DC offset voltage on the
TO signal is great, CAI should be connected via AC-coupling capacitor. At this time, insert an
about 100 kW bias resistor between CAI and SGT.
CAO is the analog output of CODEC. CAO should be connected to R1I via AC-coupling
capacitor. A bias resistor is not required to R1I. During the whole system or CODEC power down
mode, CAO is at the SG voltage level.
8/35
¡ Semiconductor
MSM7502
BCLOCK
CODEC PCM data I/O shift clock input.
The frequency is one of 64 kHz, 128 kHz, 256 kHz, 512 kHz, 1024 kHz, 2048 kHz, 96 kHz, 192 kHz,
384 kHz, 786 kHz, 1536 kHz, and 1544 kHz. If the BCLOCK signal is not applied, PLL is out of
synchronization and the CODEC path goes into the power down mode.
XSYNC, RSYNC
Synchronous signal input.
CODEC PCM data is sent out sequencially via the PCMOUT pin from MSB at the rising edge of
the BCLOCK signal in synchronization with the rise of the XSYNC signal. PCM data should be
entered via the PCMIN pin with MSB at the head in synchronization with the rise of the RSYNC
signal. PCM data is shifted in at the falling edge of the BCLOCK signal.
Since the XSYNC signal is used for a trigger signal for PLL and for a clock signal to the tone
generator, if this signal is not applied, not only any tone can not be output, but also PLL goes out
of synchronization and the CODEC path goes into a power down mode. This signal has to be
synchronous with the BCLOCK signal and its frequency must be within 8 kHz ±50 ppm to ensure
the CODEC AC characteristics (mainly frequency characteristics).
PCMIN
PCM signal input.
PCMIN data is shifted in at the falling edge of the BCLOCK signal and is latched into the internal
register after eight bits are shifted.
PCMOUT
PCM signal output.
PCMOUT data is shifted out at the rising edge of the BCLOCK signal. PCMOUT is left open after
eight bits are shifted or when PLL goes out of synchronization. PCMOUT also is left open
through processor control. In addition, a digital path between PCMIN and PCMOUT is formed
through processor control. PCMOUT needs a pull-up resistor because of its open-drain circuit.
9/35
¡ Semiconductor
MSM7502
PO0, PO1, PO2, PO3, PO4, PO5, PO6, PO7
Key scanning outputs.
These output pins need external pull-up resistors because of their open- drain circuits. But, when
these are used in combination with PI0 to PI7, pull-up resistors are not required. Through
processor control, these outputs can be set open or to digital "0". Initially, these outputs are set
at an opened state.
PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7
Key scanning inputs.
In the READ mode, data on PI0 to PI7 can be read out of the processor via data bus (DB0 to DB7).
Since these inputs are pulled up inside the IC, external resistors are not required.
INTT
Interrupt signal output to the processor.
INTT outputs interrupt signals (digital "0") at intervals of 8 ms by the interrupt release control
signal from the processor. This output keeps digital "0" unless the interrupt is released. INTT
does not output any signal while no XSYNC signal is input. When the RESETN signal is in "0"
state, INTT is in "1" state. INTT goes from "1" state to "0" state 8 ms after the RESETN signal goes
to "1" state.
Interrupt release signal
from processor
t < 8 ms
8 ms < t < 16 ms
t < 8 ms
INTT output
8 ms
16 ms
8 ms
DB0, DB1, DB2, DB3, DB4, DB5, DB6, DB7
Data bus inputs and outputs.
These pins are configured as an output during the READ mode only and as an input during other
modes.
10/35
¡ Semiconductor
MSM7502
AD0, AD1
Address data inputs for the internal control registers.
Addressing of the internal control registers is executed by AD0 and AD1 and sub address data,
DB7 and DB6.
AD1 AD0 DB7 DB6
0
WRITE
READ
0
0
1
Function
0
0
ON/OFF controls of sounder, R-Tone, F-Tone
0
1
Level/Frequency controls of sounder, R-Tone
1
0
PB tone control
1
1
Controls of internal speech path switch and general latch
Watchdog timer reset
0
0
Controls of receive gain and side tone gain
0
1
Controls of transmit hold tone, PB tone, handfree input, handset inputs gain
1
0
Controls of speaker pre-amplifier gain and additional speaker gain
1
1
Controls of receive PAD and incoming tone input gain
1
0
—
—
Key scanning output control
1
1
0
0
Key scanning interrupt reset
1
1
0
1
LCD deflection angle control voltage setting
1
1
1
0
Power ON/OFF control
1
1
1
1
CODEC control (Controls of companding law and digital loop)
1
0
—
—
Key scanning data read-out
WRN
Write signal for internal control registers.
Data on the data bus is written into the registers at the rising edge of WRN under the condition
of digital "0" of CEN (Chip Enable). While CEN is in digital "1" state, WRN becomes invalid. The
Write cycle is a minimum of 2 ms regardless of the presence or absence of clock signals.
RDN
Read signal input to read PI0 to PI7 out of the processor.
When CEN and RDN are in digital "0" state, the digital values on PI0 to PI7 are output onto the
data buses DB0 to DB7. While CEN is in digital "1" state, the RDN signal becomes invalid.
11/35
¡ Semiconductor
MSM7502
CEN
Chip Enable signal input.
When CEN is in digital "0" state, WRN and RDN are valid.
RESETN
Reset signal input.
Digital "0" input to RESETN makes all of internal control registers to be initialized. When
powered on, this RESETN signal should be input for initializing the system.
TIMEN
Watchdog timer output.
When the processor does not reset the timer, the 500 ms period (Digital "0" : 4 ms) digital signal
is continuously output. When RESETN is at digital "0", this timer is reset. And, in about 500 ms
after RESETN goes to digital "1", the first timer output signal is issued and then the timer signal
is output at intervals of a 500 ms. If the SYNC signal is not input, the TIMEN signal is not output.
LML
Control signal output for external hold tone generator.
LML goes to digital "1" state when the hold tone transmit mode on transmit path or the hold
acknowledge tone mode on receive path is selected. During initialized state, LML is in digital "0"
state.
VLCD
By processor control, VLCD outputs a DC voltage between 0 and 1.7 V is about 0.25 V step.
This is used to control the deflection angle of the LCD display. VLCD has the internal resistance
value of about 1 kW, so the external load of over 100 kW should be used. During initialized state,
VLCD outputs the voltage of 0 V.
12/35
¡ Semiconductor
MSM7502
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
Analog Input Voltage
VAIN
AG, DG = 0 V
0 to 7
V
AG, DG = 0 V
-0.3 to VDD + 0.3
V
Digital Input Voltage
Storage Temperature
VDIN
AG, DG = 0 V
-0.3 to VDD + 0.3
V
TSTG
—
-55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply Voltage
VD
VA, VD (Voltage must be fixed)
4.75
5.0
5.25
V
Operating Temperature
Ta
—
–10
+25
+70
°C
Input High Voltage
VIH
All Digital Input Pins
2.2
—
VDD
V
Input Low Voltage
VIL
All Digital Input Pins
0
—
0.8
V
Digital Input Rise Time
tIr
All Digital Input Pins
—
—
50
ns
Digital Input Fall Time
tIf
All Digital Input Pins
—
—
50
ns
PO0 to PO7
PCMOUT
PO0 to PO7
PCMOUT
10
0.5
—
—
—
—
kW
—
—
100
pF
Min.
Typ.
Max.
Unit
20
—
—
0.6
—
—
—
—
100
pF
nF
RDL
Digital Output Load
CDL
Recommend Operating Conditions (Analog Interface)
Parameter
Symbol
Condition
TPAO, MPAO, MPBO, TO,
Analog Load Resistance
RAL
RPO, SPO, CAO
RMO0, RMO1 with respected to
SG Level
Analog Load Capacitance
Allowable Analog
Input Offset Voltage
CAL
Voff
TPAO, MPAO, MPBO, TO,
RPO, SPO, CAO
RMO0, RMO1
kW
—
—
70
TPAI, TPBI, MPAI
–10
—
+10
MLDY
–50
—
+50
R1I, R2I, SPI
–25
—
+25
CAI
–100
—
+100
mV
13/35
¡ Semiconductor
MSM7502
Recommended Operating Conditions (CODEC Digital Interface)
Parameter
Symbol
Condition
Min.
Typ.
Max.
64, 128, 256, 512, 1024,
2048
96, 192, 384, 768, 1536,
1544
Unit
FC
BCLOCK
Sync Pulse Frequency
FS
XSYNC, RSYNC
6.0
8.0
10.0
kHz
Clock Duty Ratio
DC
BCLOCK
40
50
60
%
Clock Frequency
kHz
tXS
BCLOCKÆX, RSYNC
See Fig.1
—
—
100
ns
tSX
X, RSYNCÆBCLOCK
See Fig.1
—
—
100
ns
Sync Pulse Setting Time
tWS
XSYNC, RSYNC
1 BCK
—
100
ms
Data Setup Time
tDS
PCMIN
100
—
—
ns
Data Hold Time
tDH
PCMIN
100
—
—
ns
Allowable Jitter Width
—
XSYNC, RSYNC
—
—
500
ns
Sync Pulse Width
Recommended Operating Conditions (Processor Digital Interface)
Min.
Typ.
Max.
Unit
Write Pulse Period
Parameter
PW
WRN
2000
—
—
ns
Write Pulse Width
TW
WRN
100
—
—
ns
Read Pulse Width
TR
RDN
200
—
—
ns
Address Data
Setup Time
tAW1
AD0, AD1ÆWRN
10
—
—
ns
tAR1
AD0, AD1ÆRDN
80
—
—
ns
Address Data
Hold Time
tAW2
WRNÆAD0, AD1
50
—
—
ns
tAR2
RDNÆAD0, AD1
10
—
—
ns
tCW1
CENÆWRN
tCR1
CENÆRDN
tCW2
WRNÆCEN
50
—
—
ns
tCR2
RDNÆCEN
10
—
—
ns
Data Setup Time
tDW1
DB0 to 7ÆWRN
110
—
—
ns
Data Hold Time
tDW2
WRNÆDB0 to 7
20
—
—
ns
Reset Pulse Width
tWRES
RESETN
110
—
—
ns
CEN Setup Time
CEN Hold Time
Symbol
Condition
See Fig.2
10
—
—
ns
80
—
—
ns
14/35
¡ Semiconductor
MSM7502
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Power Supply Current
Symbol
Condition
Min.
Typ.
Max.
Unit
IDD1
Operating Mode (No Signal, Sounder OFF)
—
6.0
10.0
mA
IDD2
Whole system Power Down
—
0.4
0.8
mA
IDD3
CODEC Power Down
—
2.8
5.0
mA
Input High Voltage
VIH
—
2.2
—
VDD
V
Input Low Voltage
VIL
—
0.0
—
0.8
V
High Input Leakage
Current
IIH
Low Input Leakage
Current
IIL
Digital Output High
Voltage
VOH
Digital Output Low
Voltage
Digital Pins except for PI0 to PI7
—
—
2.0
mA
PI0 to PI7 (Internal Pull-up Pins)
—
—
2.0
mA
Digital Pins except for PI0 to PI7
—
—
0.5
mA
PI0 to PI7 (Internal Pull-up Pins)
10
—
25
mA
IOH = 0.4 mA
2.4
—
VDD
IOH = 1 mA
3.8
—
VDD
VOL
IOL = –1.6 mA
0.0
—
0.4
V
IO
PCMOUT, DB0 to DB7
(Write Mode)
—
—
10
mA
Analog Output Offset
Voltage
Voff
TPAO, MPAO, MPBO, TO,
CAO, RPO, RMO0, RMO1, SPO
–100
—
+100
mV
Input Capacitance
CIN
Digital Output Leakage
Current
Analog Input Resistance
SG Voltage
SG Drive Current
Equivalent Pull-up Resistance
RIN
V
—
—
5
—
pF
TPAI, TPBI, MLDYI, RMI, MPAI,
MPBI
—
10
—
MW
R1I, R2I, SPI
10
—
—
kW
CAI (fin : < 4 kHz)
—
1
—
MW
ISGF
FORCE Current
VA/2
–0.05
1.0
1.5
VA/2
+0.05
—
ISGS
SINK Current
0.3
0.5
—
RPULL
PI0 to PI7, VI = 0 V
200
370
500
—
—
VA/2
V
mA
kW
15/35
¡ Semiconductor
MSM7502
AC Characteristics 1 (CODEC)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Transmit Frequency
Response
Receive Frequency
Response
Transmit Signal to
Distortion Ratio
Receive Signal to
Distortion Ratio
Transmit Gain
Tracking
Receive Gain
Tracking
Note:
Symbol Freq. Level
(Hz) (dBm0)
Loss T1
60
Loss T2 300
Loss T3 1020
0
Loss T4 2020
Loss T5 3000
Loss T6 3400
Loss R1 300
Loss R2 1020
0
Loss R3 2020
Loss R4 3000
Loss R5 3400
SD T1
3
SD T2
0
SD T3
1020
–30
SD T4
–40
SD T5
–45
SD R1
3
SD R2
0
SD R3
1020
–30
–40
SD R4
–45
SD R5
GT T1
3
GT T2
–10
GT T3
1020
–40
GT T4
–50
GT T5
–55
GT R1
3
GT R2
–10
GT R3
1020
–40
GT R4
–50
GT R5
–55
Condition
Min.
Typ.
Max.
20
–0.20
27
+0.07
Reference
–0.03
+0.06
0.38
–0.03
Reference
–0.02
+0.15
0.56
43.0
41.0
38.0
31.0
26.5
43.0
41.0
40.0
34.0
31.0
+0.01
Reference
–0.05
+0.05
+0.30
0.0
Reference
–0.10
–0.30
–0.40
—
+0.20
–0.15
–0.15
0.0
–0.15
*1
*1
–0.15
–0.15
0.0
35
35
35
29
24
37
37
37
30
25
–0.2
–0.2
–0.4
–1.2
–0.2
–0.2
–0.5
–1.2
Unit
+0.20
+0.20
0.80
+0.20
dB
+0.20
+0.20
0.80
—
—
—
—
—
—
—
—
—
—
+0.2
dB
+0.2
+0.4
+1.2
+0.2
dB
+0.2
+0.5
+1.2
dB
dB
dB
*1 Psophometric filter is used
16/35
¡ Semiconductor
MSM7502
AC Characteristics 1 (CODEC) (Continued)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Symbol Freq. Level
(Hz) (dBm0)
Absolute Delay Time
Transmit Group Delay
Receive Group Delay
Crosstalk Attenuation
Out-of-band Signal
Spurious
Intermodulation Distortion
Power Supply Noise
Rejection Ratio
Notes:
*2
*3
*4
*5
Typ.
Max.
—
–73.5
–71
–70
–69
—
–78.0
–75
0.5671
0.6007
0.6363
0.5671
0.6007
0.6363
—
0.58
0.60
Transmit Æ Receive
—
—
—
—
—
—
—
—
—
—
70
0.19
0.12
0.02
0.05
0.08
0.0
0.0
0.0
0.09
0.12
78
0.75
0.35
0.125
0.125
0.75
0.75
0.35
0.125
0.125
0.75
—
Receive Æ Transmit
75
86
—
—
—
AIN = SG
*1
Nidle R
—
—
*1
*3
1020
0
Td
1020
0
tgd T1
tgd T2
tgd T3
tgd T4
tgd T5
tgd R1
tgd R2
tgd R3
tgd R4
tgd R5
CR T
500
600
1000
2600
2800
500
600
1000
2600
2800
AV T
AV R
CR R
DIS
Discrimination
Min.
Nidle T
Idle Channel Noise
Absolute Amplitude
Condition
S
IMD
PSR T
PSR R
*2
Unit
dBmOp
A to A
BCLOCK = 64 kHz
0
*4
0
*4
Vrms
ms
ms
ms
dB
1020
0
4.6 kHz to
72 kHz
–25
0 to 4000 Hz
30
32.0
—
dB
0
4.6 kHz to 100 kHz
—
–37.5
–35
dBmO
–4
2fa–fb
—
–52
–35
dBmO
50
mVpp
*5
—
30
—
dB
300 to
3400
fa = 470
fb = 320
0 to 50
kHz
Upper is specified for the m-law, lower of the A-law
PCMIN input : idle CODE
Minimum value of the group delay distortion
The measurement under idle channel noise
17/35
¡ Semiconductor
MSM7502
AC Characteristics 2 (Transmit Path)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Symbol Freq.
(Hz)
Pre-Amp Gain
GTPA
Transmit Path Gain
GTPB1
1020
Transmit Path Gain
Setting (VOL8)
Microphone Pre-Amp
Gain
Microphone Pre-Amp
Gain Setting
(VOL9)
Level
(dBV)
–24.0
RG1TPB
RG2TPB
RG3TPB
GMPA
RG1MPA
1020
–24.0
RG2MPA
Additional Transmit
Signal Gain
GTMX
1020
–4.0
In-Channel PB Signal
Output Level
VPBT1
—
—
GPBT1
GPBT2
GPBT3
—
—
DfPBT
—
—
In-Channel PB Signal
Distortion
THDPBT
—
—
Hold Tone Path Gain
GPAT
Hold Tone Path Gain
Setting
(VOL3)
RG1PAT
RG2PAT
RG3PAT
1020
NiTPA
—
—
VOT
1020
—
In-Channel PB Signal
Output Level Setting
(VOL4)
In-Channel PB Signal
Frequency Deviation
Idle Channel Noise
Maximum Output Voltage
Swing
Note:
–4.0
Condition
Min.
Typ.
Max.
Unit
TPAI-TPAO
18.0
20.0
22.0
dB
TPBI-TO
Set at typical gain
15.7
17.7
19.7
dB
For
–3 dB
typical
–6 dB
setting
–9 dB
MPAI-MPAO
Set at typical gain
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
dB
18.0
20.0
22.0
dB
For
typical
setting
–6 dB
–8.0
–6.0
–4.0
–9 dB
–11.0
–9.0
–7.0
–2.0
0.0
+2.0
dB
–19.4
–17.4
–15.4
dBV
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
dB
–1.0
—
+1.0
%
In-band Distortion
—
–35
–30
dB
MLDYI-TO
Set at typical gain
–4.0
–2.0
0.0
dB
–5.0
–8.0
–11.0
–3.0
–6.0
–9.0
–1.0
–4.0
–7.0
dB
—
–75
—
dBV
2.4
—
—
VPP
MPBO-TO
To per wave
set at typical gain
For
–3 dB
typical
–6 dB
setting
–9 dB
For
–3 dB
typical
–6 dB
setting
–9 dB
TPAI:Terminated in 510 W
Measured at TO
TPAO-TPBI Directly
connected Set at
typical gain *6
TPAO, TO,
MPAO, MPBO
RL = 20 kW
dB
*6 Noise band width: 0.3 kHz to 3.4 kHz, non-weighted
18/35
¡ Semiconductor
MSM7502
AC Characteristics 3 (Receive Main Amp.)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Symbol Freq.
(Hz)
Level
(dBV)
Condition
Min.
Typ.
Max.
Unit
Receive Main Amp
Output Gain Difference
DGRMO
1020
–4.4
RMO0/RMO1
Gain = 1
—
–0.10
—
dB
Receive Main Amp
Output Phase Difference
DPRMO
1020
–4.4
RMO0/RMO1
—
–179.6
—
deg
VRMO
1020
—
1.2 kW between
RMO0 and RMO1.
Measured at each output
3.6
—
—
VPP
Maximum Amplitude
AC Characteristics 3 (Receive Path)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Receive Signal Path Gain
Receive Signal
Path Gain Setting
(VOL1)
Receive PAD
Gain Setting
(VOL10)
Symbol Freq.
(Hz)
GRPA
RGRPA1
RGRPA2
RGRPA3
RGRPA4
RGRPA5
RGRPA6
RGRPA7
RGPAD1
RGPAD2
RGPAD3
Additional Receive
Signal Path Gain
GRMX
Side Tone Path Gain
GSIDE
Side Tone Path Gain
Setting
(VOL2)
Level
(dBV)
1020
GSP
Speaker Pre-Amp
Gain Setting
(VOL5)
RGSP1
RGSP2
RGSP3
RGSP4
RGSP5
RGSP6
RGSP7
Additional Speaker
Input Path Gain
GSPI
Min.
Typ.
Max.
Unit
Typical gain is set
between R1I and RPO
–8.0
–6.0
–4.0
dB
–8 dB
–6 dB
–4 dB
–2 dB
2 dB
4 dB
6 dB
–3 dB
–6 dB
–9 dB
–10.0
–8.0
–6.0
–4.0
0.0
2.0
4.0
–5.0
–8.0
–11.0
–8.0
–6.0
–4.0
–2.0
2.0
4.0
6.0
–3.0
–6.0
–9.0
–6.0
–4.0
–2.0
0.0
4.0
6.0
8.0
–1.0
–4.0
–7.0
R2I and RPO
–2.0
0.0
+2.0
dB
Typical gain is set
betweenTPBI and RPO
1.0
3.0
5.0
dB
4.0
1.0
–5.0
–8.0
–11.0
–14.0
6.0
3.0
–3.0
–6.0
–9.0
–12.0
8.0
5.0
–1.0
–4.0
–7.0
–10.0
dB
–2.0
0.0
+2.0
dB
–6.0
–10.0
–14.0
–18.0
–22.0
–26.0
–30.0
–4.0
–8.0
–12.0
–16.0
–20.0
–24.0
–28.0
–2.0
–6.0
–10.0
–14.0
–18.0
–22.0
–26.0
dB
–2.0
0.0
+2.0
dB
For
typical
setting
For
typical
setting
1020
RGSIDE1
RGSIDE2
RGSIDE3 1020
RGSIDE4
RGSIDE5
RGSIDE6
Speaker Pre-Amp
Gain
–4.0
Condition
1020
1020
–4.0
6 dB
3 dB
For
–3 dB
–14.0 typical
–6 dB
setting
–9 dB
–12 dB
Typical gain is set
between RPO and SPO
–4 dB
–8 dB
For
–12 dB
–4.0
typical
–16 dB
setting
–20 dB
–24 dB
–28 dB
Typical gain is set
–4.0
between SPI and SPO
dB
dB
19/35
¡ Semiconductor
MSM7502
AC Characteristics 3 (Receive Path) (Continued)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Additional Speaker
Input Path Gain Setting
(VOL6)
Hold Acknowledge Tone
Path Gain
PB Acknowledge Tone
Output Level
Symbol Freq.
(Hz)
RGSPI1
RGSPI2 1020
RGSPI3
GPAR
1020
Level
(dBV)
–4.0
Setting,
–6 dB
–12 dB
than
typical gain –18 dB
Typical gain is set
–4.0 between MLDYI and SPO
Min.
Typ.
Max.
Unit
–8.0
–14.0
–20.0
–6.0
–12.0
–18.0
–4.0
–10.0
–16.0
dB
–5.0
–3.0
–1.0
dB
RPO per wave
–32.1
–30.1
–28.1
dBV
—
—
SPO per wave
Set at typical gain
–30.2
–28.2
–26.2
dBV
VPBRP
VPBSP
Condition
PB Acknowledge Tone
Frequency Difference
DfPBR
—
—
RPO, SPO
–1.0
—
+1.0
%
PB Acknowledge Tone
Distortion
THDPBR
—
—
RPO, SPO
—
–35
–30
dB
Incoming Tone Speaker
Output Path Gain
GCAO
Typical gain is set
between CAO and SPO
–2.0
0.0
+2.0
dB
–12.0
–10.0
–8.0
–22.0
–20.0
–18.0
—
–86.0
—
dBV
Incoming Tone Speaker
Output Path Gain
Setting (VOL11)
Idle Channel Noise
Maximum Output Amplitude
Note:
RGCAO1
1020
–20
RGCAO2
Setting,
–10 dB
than
typical gain –20 dB
R1I:SG,
Measured at RPO
Set at typical gain. *6
dB
NiRPO
—
—
NiSPO
—
—
R1I:SG,
Measured at SPO
Set at typical gain. *6
—
–89.0
—
dBV
NiRMO
—
—
R1I:SG, Gain
0 dB
RMO0, RMOB *6
—
–86.0
—
dBV
VOR
—
—
RPO, SPO
RL = 20 kW
2.4
—
—
VPP
*6. Noise band width : 0.3 kHz to 3.4 kHz, non weighted
AC Characteristics 4 (Ringing Tone)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
R-Tone Output
Amplitude (VOL7)
F-Tone Output Amplitude
S-Tone Output
Amplitude (VOL12)
Symbol
VRTO
VFTRP
Condition
Level Setting 1
Level Setting 2
RPO
Level Setting 3
Level Setting 4
RPO
VFTSP
VSTSP
SPO
SPO
Gain
Setting
0 dB
–10 dB
–20 dB
Min.
63
84
105
126
112
Typ.
90
120
150
180
160
Max.
117
156
195
234
208
7.5
154
49
12
11.0
220
70
17
14.5
286
91
22
Unit
mVPP
mVPP
mVPP
20/35
¡ Semiconductor
MSM7502
AC Characteristics 4 (Sounder Output Circuit)
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Sounder Tone Output
Amplitude (VOL13)
Symbol Freq.
(Hz)
VST1
VST2
VST3
VST4
—
Level
(dBV)
—
Condition
730 W between
SA0 and SA1.
Measured at
each out
Vol.1
Vol.2
Vol.3
Vol.4
Min.
Typ.
Max.
Unit
3.25
0.73
0.25
0.13
4.0
1.28
0.47
0.28
—
1.98
0.65
0.45
Vpp
LCD Defelection Angle Control Voltage Output
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Output Resistance
ROLCD
Condition
DB2 DB1 DB0
1
1
1
1
0
1
1
1
0
1
0
0
0
1
1
0
0
1
0
1
0
0
0
0
—
Output Load
RLLCD
To GND
Output Voltage
Symbol
VLCD
Min.
Typ.
Max.
Unit
1.40
1.25
1.05
0.85
0.65
0.35
0.15
0.0
—
1.70
1.50
1.30
1.10
0.85
0.55
0.30
0.0
1.0
2.00
1.75
1.55
1.35
1.05
0.75
0.45
0.05
—
kW
100
—
—
kW
V
Digital Interface Characteristics
(VDD = 5 V ±5%, Ta = –10°C to +70°C)
Parameter
Digital Output (Latch)
Delay Time
Key Scanning Output
Delay Time
Digital Output (Data)
Delay Time
CODEC Data Output
Delay Time
Symbol
Condition
Min.
Typ.
Max.
Unit
tPDLA
WRÆLA, LB
0.2
—
1.5
ms
tPDSCN
WRÆPO0 to PO7
Pull-up resistance : 10 kW
0.2
—
1.5
ms
tPDDATA
RDÆDB0 to DB7
20
52
150
ns
tPDCOD
BCLOCKÆPCMOUT
Pull-up resistance : 500 W
20
50
100
ns
21/35
¡ Semiconductor
MSM7502
TIMING DIAGRAM
CODEC Timing
BCLOCK
2
1
tSX
3
4
5
6
7
9
8
tXS
XSYNC
tPDCOD
tWS
PCMOUT
MSB
B2
B3
B4
B5
B7
B6
B8
CODEC Transmit Timing
BCLOCK
2
1
tSX
3
4
5
6
7
8
9
tXS
RSYNC
tDS tDH
tWS
PCMIN
MSB
B2
B3
B4
B5
B6
B7
B8
CODEC Receive Timing
Figure 1
Processor Interface Timing
AD0, AD1
tAW1
tAW2
tAR1
tAR2
tCW1
tCW2
tCR1
tCR2
CEN
WRN
TR
TW
RDN
tDW1 tDW2
tPDDATA
tPDDATA
DB0 to DB7
tPDSCN
PO0 to PO7
tPDLA
Latch Output
Figure 2
22/35
¡ Semiconductor
FUNCTIONAL DESCRIPTION
Control Data Description
Sounder and tone ON/OFF control
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
0
0
Sounder output ON
SW19 ON
0
0
0
Sounder output OFF
SW19 OFF
0
1
Sounder output ON
SW20 ON
0
1
Sounder output OFF
SW20 OFF
1
0
R-Tone
ON
SW13 ON
1
0
R-Tone
OFF
SW13 OFF
1
1
F-Tone
ON(1 kHz)
SW14 ON,
SW15 OFF,
1
1
F-Tone
OFF
SW14 OFF,
SW15 OFF,
1
1
F-Tone
ON(1 kHz)
SW14 OFF,
SW15 ON,
1
1
F-Tone
OFF
SW14 OFF,
SW15 OFF,
1
0
0
0
0
Remarks
1
0
0
1
0
0
0
1
1
0
Tone Output: SA0, SA1
Tone Output: SPO *1
Tone Output: RPO
Tone Output: SPO
*1: This Sounder Output is sent at the timing shown below.
ON
OFF
ON
0.625 s
2s
23/35
MSM7502
0.25 s 0.125 s
OFF
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
1
—
—
—
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
—
1
Description for Control
0
0
SA0, SA1 outputs sounder volume 1 (Large)
0
1
SA0, SA1 outputs sounder volume 2 (Middle)
1
0
SA0, SA1 outputs sounder volume 3 (Small 1)
1
1
—
Remarks
Sounder volume and tone
are defind at a time.
¡ Semiconductor
Level and frequency control of sounder and R-tone
At the initial setting, sounder
volume 1 and sounder
SA0, SA1 outputs sounder volume 4 (Small 2)
combination tone 1 are set.
Sounder combination tone 1 (16 Hz wamble tone with 1000 Hz/1333 Hz)
SA0, SA1 sounder volume:
Sounder combination tone 2 (16 Hz wamble tone with 667 Hz/800 Hz) VOL 13
Sounder combination tone 3 (8 Hz wamble tone with 800 Hz/1000 Hz)
Sounder combination tone 4 (Single tone of 1000 Hz)
Sounder combination tone 5 (Single tone of 800 Hz)
Sounder combination tone 6 (Single tone of 400 Hz)
0
0
R-Tone output level 1 (90 mVPP at RPO output)
0
1
R-Tone output level 2 (120 mVPP at RPO output)
1
0
R-Tone output level 3 (150 mVPP at RPO output)
1
1
R-Tone output level 4 (180 mVPP at RPO output)
0
0
0
R-Tone 400 Hz single tone
0
0
1
R-Tone 425 Hz single tone
0
1
0
0
1
1
1
0
0
R-Tone 400 Hz ON/OFF by 16 Hz
1
0
1
R-Tone 400 Hz ON/OFF by 20 Hz
—
R-Tone 440 Hz single tone
R-Tone output level = VOL 7
R-Tone output level and
frequency are defined at a
time.
At the initial setting, output
level 1 and a single 400 Hz
tone are set.
R-Tone 450 Hz single tone
MSM7502
24/35
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Output PB Frequency
Remarks
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PB
Low
High
0
0
0
0
1
697 Hz
1209 Hz
0
0
0
1
2
697 Hz
1336 Hz
0
0
1
0
3
697 Hz
1477 Hz
When PBTC = 0
SW16: ON
SW17: ON
SW18: OFF
0
0
1
1
A
697 Hz
1633 Hz
PB tone is sent to the transmit path T0 and the receive path RPO.
0
1
0
0
4
770 Hz
1209 Hz
0
1
0
1
5
770 Hz
1336 Hz
0
1
1
0
6
770 Hz
1477 Hz
0
1
1
1
B
770 Hz
1633 Hz
When PBTC = 1
SW16: OFF
SW17: OFF
SW18: ON
1
0
0
0
7
852 Hz
1209 Hz
PB tone is sent to the receive path SPO only.
1
0
1
0
PBTC
0
1
0
0
1
8
852 Hz
1336 Hz
1
0
1
0
9
852 Hz
1477 Hz
1
0
1
1
C
852 Hz
1633 Hz
1
1
0
0
*
941 Hz
1209 Hz
1
1
0
1
0
941 Hz
1336 Hz
1
1
1
0
#
941 Hz
1477 Hz
941 Hz
1633 Hz
1
1
1
1
D
X
X
X
X
PB tone stop
¡ Semiconductor
PB tone control
SW16, SW17, SW18: OFF
MSM7502
25/35
WRITE Mode
Address Data
AD1 = 0, AD0 = 0
Control Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1
1
1
0
1
1
Remarks
0
0
0
1
SW1
ON
Transmit handfree input
0
0
1
0
SW2
ON
Transmit handset input
0
0
1
1
SW3
ON
Receive input
0
1
0
1
SW4
ON
Side tone input
0
1
1
0
SW5
ON
Receive main amplifier input
0
1
1
1
SW6
ON
Receive speaker input
1
0
0
0
SW7
ON
1
0
0
1
SW8
ON
Transmit path hold tone input
When either of SW7 or SW8 is set to ON,
Receive path hold tone Acknowledge input external terminal LML goes to "1".
1
0
1
0
SW9
ON
Additional receive input
1
0
1
1
SW10
ON
Additional speaker input
1
1
0
0
SW11
ON
Speaker DEC input
1
1
0
1
SW12
ON
PCM output enable
1
1
1
0
LA = 1
1
1
1
1
LB = 1
When hold tone or PB tone transmit is
selected, these inputs are muted.
¡ Semiconductor
SW control and timer reset
—
When Handfree input is selected, side
tone is muted.
—
—
Speaker DEC input = CODEC AOUT
—
General Latch output for external control
0
0
0
0
0
0
0
0
All of above SWs or latches are set to OFF or "0" at the initial setting stage.
Above corresponding SW or latch is set to OFF or "0".
1
1
0
0
0
0
Watchdog timer is reset.
Above codes
MSM7502
26/35
WRITE Mode
Address Data
AD1 = 0, AD0 = 1
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
—
0
—
—
0
Description for Control
0
0
0
0
0
1
–8 dB than the typical gain
0
1
0
–6 dB than the typical gain
Typical receive gain (–6dB)
0
1
1
–4 dB than the typical gain
1
0
0
–2 dB than the typical gain
1
0
1
+2 dB than the typical gain
1
1
0
+4 dB than the typical gain
1
1
1
Remarks
Receive gain = VOL1
Side tone gain = VOL2
¡ Semiconductor
Gain setting (receive gain, side tone gain)
Receive gain and side tone gain are set at a time.
At the initial setting, the typical gain is set.
+6 dB than the typical gain
Typical side tone gain (–9 dB)
0
0
0
0
0
1
–12 dB than the typical gain
0
1
0
–9 dB than the typical gain
0
1
1
1
0
0
1
0
1
+3 dB than the typical gain
1
1
0
+6 dB than the typical gain
1
1
1
—
–6 dB than the typical gain
–3 dB than the typical gain
Side tone OFF (VOL2 max loss)
MSM7502
27/35
WRITE Mode
Address Data
AD1 = 0, AD0 = 1
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
—
—
0
0
1
0
0
0
0
1
1
0
1
1
—
—
1
0
0
0
1
1
0
1
1
Description for Control
0
0
0
1
–3 dB with respect to the typical gain
1
0
–6 dB with respect to the typical gain
1
1
–9 dB with respect to the typical gain
Typical transmit hold tone gain (–2 dB)
Typical transmit PB tone gain (+4 dB)
–3 dB with respect to the typical gain
—
Remarks
Transmit hold tone gain = VOL3
Transmit PB tone gain = VOL4
¡ Semiconductor
Gain control (transmit hold tone, PB tone, microphone input, handset input)
Hold tone gain and PB tone
gain are set at a time.
At the initial setting, the typical gain is set.
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
0
0
0
1
–6 dB with respect to the typical gain
1
0
1
1
–9 dB with respect to the typical gain
—
Typical handfree input gain (+20 dB)
Typical handset input gain (+12 dB)
—
–3 dB with respect to the typical gain
Handfree input gain = VOL9
Handset input gain = VOL8
Handfree input gain and handset Input
gain are set at a time.
At the initial setting, the typical gain is set.
–6 dB with respect to the typical gain
–9 dB with respect to the typical gain
MSM7502
28/35
WRITE Mode
Address Data
AD1 = 0, AD0 = 1
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
—
—
1
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
-4 dB with respect to the typical gain
0
1
0
-8 dB with respect to the typical gain
0
1
1
-12 dB with respect to the typical gain
1
0
0
-16 dB with respect to the typical gain
1
0
1
-20 dB with respect to the typical gain
1
1
0
-24 dB with respect to the typical gain
1
1
1
1
0
Speaker amp. gain = VOL5
Additional speaker gain = VOL6
Speaker amp. gain and additional
speaker gain are set at a time.
At the initial setting, SW21-OFF and the
typical gain are set.
-28 dB with respect to the typical gain
-6 dB with respect to the typical gain
—
-12 dB with respect to the typical gain
-18 dB with respect to the typical gain
0
0
0
0
Typical speaker amp. gain (0 dB)
Remarks
Typical additional speaker input path gain (0 dB)
—
1
Description for Control
¡ Semiconductor
Gain control (receive PAD, speaker)
0
1
Speaker receive ON (SW21 ON)
0
Typical receive PAD gain (0 dB)
0
1
-3 dB with respect to the typical gain
1
1
0
1
-6 dB with respect to the typical gain
1
0
-9 dB with respect to the typical gain
Typical incoming tone gain (0 dB)
—
-10 dB with respect to the typical gain
-20 dB with respect to the typical gain
Receive PAD = VOL10
Incoming tone gain = VOL11, VOL12
Receive PAD and incoming tone gain are
set at a time.
At the initial setting, the typical gain is set.
29/35
MSM7502
1
Speaker receive OFF(SW21 OFF)
0
0
0
0
WRITE Mode
Address Data
AD1 = 1, AD0 = 0
Controlo Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
The data set on DB7 to DB0 are output on PO7 to PO0 respectively.
Output data is held until next data is written.
When the set data is set to "0", output data goes to "0", when set to "1", output pin becomes open.
At the initial setting, PO7 to PO0 are in open state.
Output Data
¡ Semiconductor
Key scanning signal output control
Key scanning data read out
Read Mode
Address Data
AD1 = 1, AD0 = 0
Contorol Data
Description for Control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
Data input onto PI7 to PI0 are output onto DB7 to DB0.
Key scanning interrupt reset
WRITE Mode
Address Data
AD1 = 1, AD0 = 1
Control Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
1
Description for Control
INTT output is reset (Output = 1)
Remarks
Valid during write mode only
MSM7502
30/35
WRITE Mode
Address Data
AD1 = 1, AD0 = 1
Contorol Data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Description for Control
Remarks
LCD Deflection Angle Control Voltage Output
0
1
0
0
0
0
0
0
0
0
1
VLCD pin output voltage: 0.0 V
: 0.30 V
0
1
0
: 0.55 V
0
1
1
: 0.85 V
1
0
0
: 1.1 V
1
0
1
: 1.3 V
1
1
0
: 1.5 V
1
1
1
: 1.7 V
0
0
Whole system power down mode
0
1
Whole system power ON mode
1
0
CODEC power down mode
1
1
CODEC power ON mode
¡ Semiconductor
Special functions
At the initial setting stage,
set to 0 V.
Power Down Mode Control
1
0
0
0
0
0
At the initial setting stage, set to
whole system power down mode.
CODEC power ON/OFF control is
valid in the whole system power
ON mode.
CODEC Control
—
1
1
0
0
0
0
0
1
*2:
0
CODEC operates in m-law
1
CODEC operates in A-law
—
PCMIN and PCMOUT are normally connected
PCMOUT is connected to PCMIN
31/35
MSM7502
Even during the whole system power down mode, following functions are available, if XSYNC is input. :
Key scanning data I/O, sounder outputs (SA0, SA1), WDT, INTT, and general latch output (LA, LB)
At the initial setting stage, set to
m-law, and PCMIN and PCMOUT
are normally connected.
The componding law and the
connection control are set at a
time.
100 kW
MPAI
TPAO
TPBI
MPAO MPBI
MPBO
TO
0.1 mF
CAI
MLDYI
LML
+5 V
SGT
100 kW
TPAI
CAO
PCMOUT
PCMIN
BCLOCK
XSYNC
RSYNC
R1I
RPO
Hold Tone
Generator
Line
Interface
Line
¡ Semiconductor
100 kW
0.1 mF
APPLICATION CIRCUIT
*1
+5 V
Handset
RMI
*2
RMO0
WRN
RDN
CEN
RESETN
RMO1
DB0 to DB7
Controller
AD0
AD1
INTT
TIMEN
SPO
AG
DG
VA
VD
PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7
SGC
SAO
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
Speaker
SPI
0-20 W
+
*1
Insert a resistor if necessary.
0.1 mF
0V
0.1 mF to 1 mF
SW Matrix
*2
Inserting a capacitor (1 mF to 22 mF)
between SGT and AG will improve
the transmit path noise
characteristic.
+5 V
10 mF
MSM7502
32/35
TPAI
VOL 9
+
20 dB
MPBI
–
–20 dB to +25 dB
+
VOL 8
+
CAO
VOL 10
–
SW1
0 dB
SW2
5.7 dB
SW7
VOL 3
SW16
VOL 4
AIN
–
CODEC
PB GEN.
Per Wave
0.24 VPP(–21.4 dBV Equivalent)
RPO
RMI
–
SW5
–
RMO0
SW5
0 dB
RMO1
0 dB
SW9
VOL 1
SW3
R-Tone GEN.
90 mVPP Pulse (–27.8 dBV Equivalent)
VOL 2
SW4
F-Tone GEN.
0.16 VPP Pulse (–22.8 dBV Equivalent)
VOL 7
SW13
–8.7 dB
SW17
0 dB
SW14
–
0 dB
SPI
CAI
AOUT
R1I
R2I
SPO
TO
MPBO
–
VOL 5
SW21
VOL 12
SW20
VOL 11
SW11
–22 dB
SW15
–
SW6
–3 dB
SW8
–6.8 dB
SW18
VOL 6
SW10
CODEC I/O Level
Overload Point: 1.2 Vop
0 dBmO
: 0.6007 Vrms
(–4.4 dBV)
¡ Semiconductor
MPAO
MSM7502 Speech Path Level Setting
MLDYI
TPAO TPBI MPAI
S-Tone GEN.
0.22 VPP Pulse (–20.0 dBV Equivalent)
VOL No. Typical Level Variable Range
Step Width
VOL 1
VOL 2
VOL 3
VOL 4
VOL 5
VOL 6
VOL 7
VOL 8
VOL 9
VOL 10
–6 dB
–9 dB
–2 dB
+4 dB
0 dB
–14 dB to 0 dB
–21 dB to –3 dB
–11 dB to –2 dB
–5 dB to +4 dB
–28 dB to 0 dB
0 dB
0 dB
+12 dB
+20 dB
0 dB
–18 dB to 0 dB
90 mV to 180 mV
+3 dB to +12 dB
+11 dB to +20 dB
–9 dB to 0 dB
2 dB
3 dB
3 dB
3 dB
4 dB
6 dB
30 mV
3 dB
3,6 dB
3 dB
VOL 11
VOL 12
0 dB
0 dB
–20 dB to 0 dB
–20 dB to 0 dB
10 dB
10 dB
MSM7502
33/35
¡ Semiconductor
MSM7502
RECOMMENDATIONS FOR ACTUAL DESIGN
• To assure proper electrical characteristics, use bypass capacitors with excellent high frequency
characteristics for the power supply and keep them as close as possible to the VA and AG pins.
• Connect the AG pin and the DG pin each other as close as possible. Connect to the system
ground with low impedance.
• Connect the VA pin and the VD pin as close together as possible and route them to the analog
5 V power supply.
• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If an
IC socket is unavoidable, use the short lead type socket.
• When mounted on a frame, use electro-magnetic shielding, if any electro-magnetic wave
source such as power supply transformers surround the device.
• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-up
phenomenon when turning the power on.
• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise) power
supply to avoid erroneous operation and the degradation of the characteristics of these devices.
• Connect analog input pins and digital input pins that are not used to the SG pin and to GND,
respectively.
• When the data is written differently from the data defined in the section, Control Data
Description in FUNCTIONAL DESCRIPTION, normal device operation is not guaranteed.
34/35
¡ Semiconductor
MSM7502
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
35/35