ETC TPS54616PWPR

TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
Typical Size
6,6 mm X 9,8 mm
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT)
FEATURES
D 30-mΩ, 12-A Peak MOSFET Switches for High
D
D
D
D
D
D
Efficiency at 6-A Continuous Output Source
and Sink
0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V Fixed
Output Voltage Devices With 1.0% Initial
Accuracy
Internally Compensated for Easy Use and
Minimal Component Count
Fast Transient Response
Wide PWM Frequency – Fixed 350 kHz,
550 kHz or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
D Low-Voltage, High-Density Systems With
D
D
The SWIFT family of dc/dc regulators, the TPS54611,
TPS54612, TPS54613, TPS54614, TPS54615 and
TPS54616 low-input voltage high-output current
synchronous-buck PWM converters integrate all
required active components. Included on the substrate
are true, high-performance, voltage error amplifiers that
provide high performance under transient conditions;
an under-voltage-lockout circuit to prevent start-up until
the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush currents;
and a power good output useful for processor/logic
reset, fault signaling, and supply sequencing.
The TPS54611–6 devices are available in a thermally
enhanced 28-pin TSSOP (PWP) PowerPAD
package, which eliminates bulky heatsinks. TI provides
evaluation modules and the SWIFT designer software
tool to aid in quickly achieving high-performance power
supply designs to meet aggressive equipment
development cycles.
Power Distributed at 5 V or 3.3 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
EFFICIENCY AT 350 kHz
100
95
90
85
Efficiency – %
D
DESCRIPTION
Output
VIN
75
70
65
SIMPLIFIED SCHEMATIC
Input
80
60
PH
55
TPS54614
BOOT
50
0
1
2
3
4
5
6
Load Current – A
PGND
VBIAS VSENSE
AGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
THERMAL 22
PAD
21
20
19
18
17
16
15
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
AVAILABLE OPTIONS
OUTPUT
VOLTAGE
TA
– 40°C
40 C to 85°C
85 C
PACKAGED DEVICES
TA
PLASTIC HTSSOP
(PWP)†
0.9 V
TPS54611PWP
1.2 V
TPS54612PWP
1.5 V
TPS54613PWP
– 40°C
40 C to 85°C
85 C
OUTPUT
VOLTAGE
PACKAGED DEVICES
1.8 V
TPS54614PWP
2.5 V
TPS54615PWP
3.3 V
TPS54616PWP
PLASTIC HTSSOP
(PWP)†
† The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54616PWPR).
See application section of data sheet for PowerPAD drawing and layout information.
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
AGND
1
Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to
AGND.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-set FET driver.
NC
3
No connection
PGND
15–19
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6–14
Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low or internal shutdown signal active.
RT
28
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
SS/ENA
26
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
FSEL
27
Frequency select input. Provides logic input to select between two internally set switching frequencies.
VBIAS
25
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
20–24
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.
VIN
VSENSE
2
2
Error amplifier inverting input. Connect directly to output voltage sense point.
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TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range, VI: VIN, SS/ENA, FSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
RT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
VSENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
BOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 17 V
Output voltage range, VO: VBIAS, PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to 10 V
Source current, IO: PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mA
Sink current, IS:
PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 A
SS/ENA, PWRGD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Voltage differential, AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Power Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE‡
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
28 Pin PWP with solder
18.2 °C/W
5.49 W§
3.02 W
2.20 W
28 Pin PWP without solder
40.5 °C/W
2.48 W
1.36 W
0.99 W
NOTE: For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
‡ Test Board Conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
§ Maximum power dissipation may be limited by over current protection.
ADDITIONAL 6A SWIFT DEVICES
DEVICE
OUTPUT VOLTAGE
TPS54610
0.9 V to 3.3 V
related dc/dc products
D UCC3585—dc/dc controller
D TPS759xx—7.5 A low dropout regulator
D PT6440 series—6 A plugin modules
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3
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
electrical characteristics, TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
I(Q)
3.0
fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open
fs = 550 kHz, FSEL ≤ 2.5 V, RT open, phase pin open
Quiescent current
Shutdown, SS/ENA = 0 V
6.0
6.2
9.6
8.4
12.8
1
1.4
2.95
3.0
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
V
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch,
UVLO
See Note 1
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
See Note 2
Output current, VBIAS
2.70
2.80
2.90
V
100
µA
OUTPUT VOLTAGE
VO
TPS54611
TJ = 25°C, VIN = 5 V
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, –40° ≤ TJ ≤ 125°C
TPS54612
TJ = 25°C, VIN = 5 V
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, –40° ≤ TJ ≤ 125°C
TPS54613
TJ = 25°C, VIN = 5 V
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, –40° ≤ TJ ≤ 125°C
–2.0%
TPS54614
TJ = 25°C, VIN = 5 V
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, –40° ≤ TJ ≤ 125°C
–3.0%
TPS54615
TJ = 25°C, VIN = 5 V
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, –40° ≤ TJ ≤ 125°C
TPS54616
TJ = 25°C, VIN = 5 V
3 V ≤ VIN ≤ 6 V, 0 ≤ IL ≤ 6 A, –40° ≤ TJ ≤ 125°C
Output voltage
0.9
–2.0%
V
2.0%
1.2
–2.0%
V
2.0%
1.5
V
2.0%
1.8
V
3.0%
2.5
–3.0%
V
3.0%
3.3
–3.0%
V
3.0%
REGULATION
Line regulation (see Notes 1 and 3)
Load regulation (see Notes 1 and 3)
IL = 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C
IL = 0 A to 6 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C
0.088
%/V
0.0917
%/A
OSCILLATOR
Internally set—free
set free running
frequency
Externally
E
t
ll set—free
t f
running
i
frequency range
SYNC ≤ 0.8 V,
RT open
280
350
420
SYNC ≥ 2.5 V,
RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
RT = 68 kΩ (1% resistor to AGND)
280
700
762
High level threshold, FSEL
2.5
kHz
V
Low level threshold, FSEL
0.8
V
Ramp valley
See Note 1
0.75
V
Ramp amplitude (peak-to-peak)
See Note 1
1
V
Minimum controllable on time
See Note 1
Maximum duty cycle
See Note 1
200
90%
NOTES: 1. Specified by design
2. Static resistive loads only
3. Tested using circuit in Figure 10.
4
kHz
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ns
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
electrical characteristics, TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
See Note 1
Error amplifier unity gain bandwidth
See Note 1
3
Error amplifier common mode input voltage range
Powered by internal LDO (see Note 1)
0
26
dB
5
MHz
VBIAS
V
70
85
ns
1.20
1.40
V
PWM COMPARATOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding deadtime)
10-mV overdrive (see Note 1)
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.95
Enable hysteresis voltage, SS/ENA
See Note 1
Falling edge deglitch, SS/ENA
See Note 1
Internal slow-start time
Charge current, SS/ENA
SS/ENA = 0V
Discharge current, SS/ENA
SS/ENA = 1.3 V, VI = 1.5 V
0.03
V
µs
2.5
2.6
3.35
4.1
ms
3
5
8
µA
1.5
2.3
4.0
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
Power good hysteresis voltage
See Note 1
3
%VO
%VO
Power good falling edge deglitch
See Note 1
35
µs
Output saturation voltage, PWRGD
I(sink) = 2.5 mA
VI = 5.5 V
Leakage current, PWRGD
90
0.18
0.3
V
1
µA
CURRENT LIMIT
Current limit
VI = 3 V
VI = 6 V
(see Note 1)
7.2
10
(see Note 1)
10
12
A
Current limit leading edge blanking time
100
ns
Current limit total response time
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point
See Note 1
Thermal shutdown hysteresis
See Note 1
135
150
10
165
IO = 3 A, VI = 6 V (see Note 4)
IO = 3 A, VI = 3 V (see Note 4)
26
47
36
65
_C
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
mΩ
NOTES: 1: Specified by design
4: Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
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5
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
internal block diagram
AGND
VBIAS
VIN
Enable
5 µA Comparator
SS/ENA
Falling
Edge
Deglitch
1.8 V
Hysteresis: 0.03 V
VIN UVLO
Comparator
VIN
2.94 V
Hysteresis: 0.16 V
VIN
ILIM
Comparator
Thermal
Shutdown
145°C
2.5 µs
REG
VBIAS
SHUTDOWN
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
Sensefet
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-Start
(Internal Slow-Start Time =
3.3 ms to 6.6 ms)
VI
PH
+
–
2 kΩ
S
40 kΩ
Error
Amplifier
VI
Feed-Forward
Compensation
PWM
Comparator
25 ns Adaptive
Deadtime
VIN
30 mΩ
PGND
OSC
Power good
Comparator
Reference/
DAC
Falling
Edge
Deglitch
VSENSE
0.90 Vref
Hysteresis: 0.03 Vref
TPS5461x
VSENSE
6
CO
Adaptive Dead-Time
and
Control Logic
R Q
LOUT
RT
FSEL
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SHUTDOWN
35 µs
PWRGD
VO
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
detailed description
under voltage lock out (UVLO)
The TPS5461x incorporates an under voltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN.
slow-start/enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise. Refer to the following table for start up times for each device
DEVICE
OUTPUT VOLTAGE
SLOW-START
DEVICE
OUTPUT VOLTAGE
SLOW-START
TPS54611
0.9 V
3.3 ms
TPS54614
1.8 V
3.3 ms
TPS54612
1.2 V
4.5 ms
TPS54615
2.5 V
4.7 ms
TPS54613
1.5 V
5.6 ms
TPS54616
3.3 V
6.1 ms
The second function of the SS/ENA pin provides an external means for extending the slow-start time with a
ceramic capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay
is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold.
The start-up delay is approximately:
t +C
d
(SS)
1.2 V
5 mA
(1)
Second, as the output becomes active, a brief ramp up at the internal slow-start rate may be observed before
the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start
capacitor. The slow-start time set by the capacitor is approximately:
t
(SS)
+C
(SS)
0.7 V
5 mA
(2)
The actual slow-start time is likely to be less than the above approximation due to the brief ramp up at the internal
rate.
VBIAS regulator
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may
be useful as a reference voltage for external circuits.
voltage reference
The voltage reference system produces a precise, temperature-stable voltage from a bandgap circuit. A scaling
amplifier and DAC are then used to produce the reference voltages for each of the fixed output devices.
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7
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
detailed description (continued)
oscillator and PWM ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency
can be externally adjusted from 280 kHz to 700 kHz by connecting a resistor from the RT pin to AGND and
floating the FSEL pin. The switching frequency is approximated by the following equation, where R is the
resistance from RT to AGND:
Switching Frequency + 100 kW
R
500 [kHz]
(3)
The following table summarizes the frequency selection configurations:
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥2.5 V
Float
Externally set 280 kHz to 700 kHz
Float
R = 180 k to 68 k
error amplifier
The high performance, wide bandwidth, voltage error amplifier is gain-limited to provide internal compensation
of the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good
noise and ripple characteristics, but with exceptional transient response. Transient recovery times are typically
in the range of 10 µs to 20 µs.
PWM control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM
latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the
current limit threshold, the PWM comparator output and oscillator pulse train alternately set and reset the PWM
latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above
the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains
on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54611 – TPS54616
devices are capable of sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and the low-side FET turns on to decrease the energy
in the output inductor and consequently decrease the output current. This process is repeated each cycle in
which the current limit comparator is tripped.
8
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TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
detailed description (continued)
dead-time control and MOSFET drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. The high-side and low-side
drivers are designed with 300 mA source and sink capability to quickly drive the power MOSFETs gates. The
low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit
uses an external BOOT capacitor and internal 2.5-Ω bootstrap switch connected between the VIN and BOOT
pins. The integrated bootstrap switch improves drive efficiency and reduces external component count.
overcurrent protection
Cycle-by-cycle current limiting is achieved by sensing the current flow through the high-side MOSFET and a
differential amplifier with preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of current limit.
Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter.
Load protection during current sink operation is provided by thermal shutdown.
thermal shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases
to 10°C below the thermal shutdown trip point, and will start up under control of the slow-start circuit.Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. With a
persistent fault condition, the device will cycle continuously: starting up by control of the slow-start circuit,
heating up due to the fault, and then shutting down upon reaching the thermal shutdown trip point.
power good (PWRGD)
The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE falls 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold,
SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the power good
comparator due to high-frequency noise.
www.ti.com
9
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE
RESISTANCE
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE ON-STATE
RESISTANCE
vs
JUNCTION TEMPERATURE
Drain-Source On-State Resistance – Ω
Drain-Source On-State Resistance – Ω
VI = 3.3 V
100
IO = 3 A
80
60
40
20
0
25
85
IO = 3 A
60
40
20
0
–40
0
–40
VI = 5 V
80
125
TJ – Junction Temperature – °C
0
25
85
TJ – Junction Temperature – °C
Figure 1
450
250
–40
600
RT = 100 k
500
400
RT = 180 k
300
85
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
0.893
0.891
0.889
0.887
–80
–100
60
–120
40
Gain
20
–140
–160
0
–180
–20
–200
10 k 100 k 1 M 10 M
10
100
1k
f – Frequency – Hz
Figure 7
25
85
125
3
4
5
VI – Input Voltage – V
DEVICE POWER LOSSES
vs
LOAD CURRENT
5
TJ = 125°C
FS = 700 kHz
4.5
3.65
3.50
3.35
3.20
3.05
2.90
2.75
–40
6
Figure 6
3.80
–40
–60
Phase
80
0.8870
–20
Phase – Degrees
100
f = 350 kHz
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
Internal Slow-Start Time – ms
120
0.8890
Figure 5
0
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
0.8910
0.8850
0
Figure 4
140
TA = 85°C
0.8930
TJ – Junction Temperature – °C
ERROR AMPLIFIER
OPEN LOOP RESPONSE
125
0.8950
0.885
–40
125
85
25
Figure 3
Device Power Losses – W
25
0
TJ – Junction Temperature – °C
VO – Output Voltage Regulation – V
700
0
SYNC ≤ 0.8 V
350
125
RT = 68 k
Vref – Voltage Reference – V
f – Externally Set Oscillator Frequency – kHz
550
0.895
800
200
–40
SYNC ≥ 2.5 V
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
Gain – dB
650
Figure 2
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
0
750
f – Internally Set Oscillator Frequency –kHz
100
120
10
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
4
VI = 33 V
3.5
3
2.5
2
1.5
VI = 50 V
1
0.5
0
0
25
85
TJ – Junction Temperature – °C
Figure 8
www.ti.com
125
0
1
2
3
4
5
IL – Load Current – A
Figure 9
6
7
8
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54614 application. The TPS54614 (U1) can provide
greater than 6 A of output current at a nominal output voltage of 1.8 V. For proper operation, the exposed thermal
PowerPAD underneath the integrated circuit package needs to be soldered to the printed-circuit board.
VI
3V–6V
20
220 µF
10 µF
21
VIN
BOOT
VIN
PH
22
VIN
23
VIN
24
VIN
7
PH
8
PH
9
PH
10
PH
11
PH
12
PH
13
PH
14
PH
15
PGND
PGND 16
17
PGND
18
PGND
19
PGND
10 kΩ
27
28
PwrGood
26
25
4
Enable
0.1 µF
5
6
3
2
CSS
FSEL
RT
SS/ENA
VBIAS
PWRGD
NC
VSENSE
1
AGND
0.047 µF
7.2 µH
VO
1.8 V
680 µF
PwrPad
Figure 10. Application Circuit
component selection
The values for the components used in this design example were selected using the SWIFT designer software
tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the
TPS54614, or other devices in the SWIFT product family. Additional design information is available at
www.ti.com.
input filter
The input to the circuit is a nominal 3.3 VDC or 5 VDC. The input filter is a 220-µF POSCAP capacitor, with a
maximum allowable ripple current of 3 A. A 10-µF ceramic capacitor for the TPS54614 is required, and must
be located as close as possible to the device.
feedback circuit
The output voltage of the converter is fed directly into the VSENSE pin of the TPS54614. The TPS54614 is
internally compensated to provide stability of the output under varying line and load conditions.
www.ti.com
11
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
operating frequency
In the application circuit, 350 kHz operation is selected by leaving FSEL open. Different operating frequencies
can be selected by connecting a resistor between RT pin and AGND. Choose the value of R using equation 4
for the desired operating frequency:
R+
500 kHz
SwitchingFrequency
100 kW
(4)
Alternately, a preset operating frequency of 550 kHz can be selected by leaving RT open and connecting the
FSEL pin to VI.
output filter
The output filter is composed of a 5.2-µH inductor and a 470-µF capacitor. The inductor is low dc resistance
(16-mΩ) type, Sumida CDRH104R–5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal compensation network to provide a stable closed loop
response for the converter.
grounding and PowerPAD layout
The TPS54611–16 have two internal grounds (analog and power). Inside the TPS54611–16, the analog ground
ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD
is tied internally to the analog ground. Noise injected between the two grounds can degrade the performance
of the TPS54611–16, particularly at higher output currents. However, ground noise on an analog ground plane
can also cause problems with some of the control and bias signals. For these reasons, separate analog and
power ground planes are recommended. These two planes should tie together directly at the IC to reduce noise
between the two grounds. The only components that should tie directly to the power ground plane are the input
capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54611–16.
The layout of the TPS54614 evaluation module is representative of a recommended layout for a 4-layer board.
Documentation for the TPS54614 evaluation module can be found on the Texas Instruments web site
(www.ti.com) under the TPS54614 product folder. See the TPS54614–185 User’s Guide, TI literature number
SLVU053, and the application note, TI literature number SLVA105.
layout considerations for thermal performance
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area.
A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance
thermal performance should be included in areas not under the device package.
12
www.ti.com
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
Minimum Recommended Thermal Vias:
8 x 0.013 Diameter Inside Powerpad Area
4 x 0.018 Diameter Under Device as Shown
Additional 0.018 diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
8 PL Ø 0.0130
4 PL
Ø 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area For Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3478 0.0500
0.1900
0.0500
0.0256
0.0650
0.0339
Exposed Copper Area
For Powerpad
0.1700
0.1250
Minimum Recommended Top
Side Analog Ground Area
0.1000
0.0600
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
performance graphs
EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
100
LOOP RESPONSE
1.03
80
VI = 3.3V
70
60
40
1.01
Gain – dB
VO – Output Voltage – V
Efficiency – %
50
1.02
VI = 5 V
VI = 5 V
1
VI = 3.3V
Phase
90
20
Gain
10
0.99
135
30
Phase – Degrees
90
180
60
45
0
0.98
–10
50
0
1
2
3
4
5
6
7
IL – Load Current – A
Figure 12
8
9
10
0.97
0
1
2
3
4
5
6
7
IL – Load Current – A
Figure 13
www.ti.com
8
9
10
–20
10
100
1k
10 k
0
100 k
f – Frequency – Hz
Figure 14
13
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
APPLICATION INFORMATION
TRANSIENT RESPONSE
OUTPUT RIPPLE VOLTAGE
START-UP WAVEFORMS
350
14
7
70
300
12
6
250
10
200
8
150
6
100
4
50
2
1
0
0
40 60 80 100 120 140 160 180 200
0
0
20
VO – Output Voltage – mV
80
VI – Input Voltage – V
8
I O – Output Current – A
16
VO – Output Voltage – mV
400
5
4
3
2
6
4
8
10 12
14 16 18 20
30
20
Figure 15
Figure 16
125
TJ = 125°C
FS = 700 kHz
105
VI = 5 V
95
85
75
65
VI = 3.3 V
55
45
Safe Operating Area
35
25
1
2
3
4
5
6
IL – Load Current – A
Figure 18
www.ti.com
20
40 60 80 100 120 140 160 180 200
Figure 17
AMBIENT TEMPERATURE
vs
LOAD CURRENT
115
0
t – Time – µs
t – Time – µs
T A – Ambient Temperature – ° C
40
0
2
t – Time – µs
14
50
10
0
0
60
7
8
TPS54611, TPS54612, TPS54613
TPS54614, TPS54615, TPS54616
SLVS400A– AUGUST 2001 – REVISED JANUARY 2002
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°–ā8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/F 10/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
www.ti.com
15
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