6,4 mm x 9,7 mm TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 9-A OUTPUT, 3-V TO 4-V INPUT TRACKING/TERMINATION SYNCHRONOUS PWM SWITCHER WITH INTEGRATED FETS (SWIFT™) FEATURES DESCRIPTION • • • • • • As a member of the SWIFT™ family of dc/dc regulators, the TPS54972 low-input voltage high-output current synchronous-buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter L and C components; an under-voltage-lockout circuit to prevent start-up until the input voltage reaches 3.0 V; an internally set slow-start circuit to limit in-rush currents; and a status output to indicate valid operating conditions. The TPS54972 is available in a thermally enhanced 28-pin TSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles. Tracks Externally Applied Reference Voltage 15-mΩ MOSFET Switches for High Efficiency at 9-A Continuous Output Source or Sink Current 6% to 90% VI Output Tracking Range Wide PWM Frequency: Fixed 350 kHz or Adjustable 280 kHz to 700 kHz Load Protected by Peak Current Limit and Thermal Shutdown Integrated Solution Reduces Board Area and Total Cost APPLICATIONS • • • • DDR Memory Termination Voltage Active Termination of GTL and SSTL High-Speed Logic Families DAC Controlled High Current Output Stage Precision Point of Load Power Supply Input VIN PH TPS54972 BOOT PGND REFIN V(TTQ) COMP VBIAS AGND VSENSE Compensation Network TRANSIENT RESPONSE VI = 3.3 V VO = 1.25 V 2.25 A to 6.75 A I O – Output Current –2 A/div V(DDQ) VO – Output Voltage – 50 mV/div SIMPLIFIED SCHEMATIC t – Time – µs/div Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002, Texas Instruments Incorporated TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA REFIN VOLTAGE -40°C to 85°C 0.2 V to 1.75 V PACKAGE Plastic HTSSOP (PWP)(1) PART NUMBER TPS54972PWP The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54972PWPR). See the application section of the data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (2) TPS54972 Input voltage range, VI Output voltage range, VO Source current, IO ENA -0.3 V to 7 V VIN -0.3 V to 4.5 V RT -0.3 V to 6 V VSENSE, REFIN -0.3 V to 4 V BOOT -0.3 V to 17 V VBIAS, COMP, STATUS -0.3 V to 7 V PH -0.6 V to 6 V PH Internally Limited COMP, VBIAS 6 mA PH 16 A Sink current, IS COMP 6 mA ENA, STATUS 10 mA Voltage differential AGND to PGND ±0.3 V Operating virtual junction temperature range, TJ -40 to 125 °C Storage temperature, Tstg -65 to 150 °C 300 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Input voltage, VI Operating junction temperature, TJ 2 3 -40 4 V 125 °C TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 DISSIPATION RATINGS (3) (4) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT TA=25°C POWER TA=70°C POWER TA=85°C POWER RATING RATING RATING 28 Pin PWP with solder 14.4°C/W 6.94 W (5) 3.81 W 2.77 W 28 Pin PWP without solder 27.9°C/W 3.58 W 1.97 W 1.43 W ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX fs=350 kHz, RT open, PH pin open 11 15.8 fs=500 kHz, RT=100 kΩ, PH pin open 16 23.5 1 1.4 2.95 3.0 UNIT SUPPLY VOLTAGE, VIN VIN Input voltage range I(Q) Quiescent current 3.0 Shutdown, SS/ENA=0 V 4.0 V mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO Hysteresis voltage, UVLO V 2.7 2.8 V 0.14 0.16 V 2.5 µs Rising and falling edge deglitch, UVLO (6) BIAS VOLTAGE Output voltage, VBIAS I(VBIAS)=0 2.70 2.80 Output current, VBIAS (7) 2.90 V 100 µA REGULATION Line regulation (6) (8) IL=4 A, fs=350 kHz, TJ=85°C 0.04 %/V Load regulation (6) (8) IL=0 A to 8 A, fs=350 kHz, TJ=85°C 0.03 %/A kHz OSCILLATOR Internally set free running frequency Externally set free running frequency range RT open 280 350 420 RT=180 kΩ (1% resistor to AGND) 252 280 308 RT=100 kΩ (1% resistor to AGND) 460 500 540 RT=68 kΩ (1% resistor to AGND) 663 700 762 Ramp valley (6) 0.75 Ramp amplitude (peak-to-peak) (6) V 1 Minimum controllable on time (6) V 200 Maximum duty cycle (6) kHz ns 90% ERROR AMPLIFIER (3) (4) (5) (6) (7) (8) Error amplifier open loop voltage gain 1 kΩ COMP to AGND (6) 90 110 Error amplifier unity gain bandwidth Parallel 10 kΩ, 160 pF COMP to AGND (6) 3 5 Error amplifier common mode input voltage range Powered by internal LDO (6) 0 Input bias current, VSENSE VSENSE=Vref 60 dB MHz VBIAS V 250 nA For more information on the PWP package, refer to TI technical brief, literature number SLMA002. Test board conditions: 3" x 3", 4 layers, thickness: 0.062" 1.5 oz. copper traces located on the top of the PCB 1.5 oz. copper ground plane on the bottom of the PCB 12 thermal vias (see Recommended Land Pattern in applications section of this data sheet) Maximum power dissipation may be limited by overcurrent protection. Specified by design Static resistive loads only Specified by the circuit used in Figure 8 ••• • 3 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS Output voltage slew rate (symmetric), COMP MIN TYP 1.0 1.4 MAX UNIT V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding 10-mV overdrive (6) deadtime) 70 85 ns 1.20 1.40 V SLOW-START/ENABLE Enable threshold voltage, ENA 0.82 Enable hysteresis voltage, ENA (6) Falling edge deglitch, ENA (6) Internal slow-start time 2.6 0.03 V 2.5 µs 3.35 4.1 ms 0.18 0.30 V 1 µA STATUS Output saturation voltage, PWRGD Isink=2.5 mA Leakage current, PWRGD VI=3.6 V CURRENT LIMIT Current limit 15 A Current limit leading edge blanking time VI=3.3 V 11 100 ns Current limit total response time 200 ns THERMAL SHUTDOWN Thermal shutdown trip point (9) 135 Thermal shutdown hysteresis (9) 150 165 °C °C 10 OUTPUT POWER MOSFETS rDS(on) Power MOSFET switches VI=3.0 V (10) 15 30 VI=3.6 V (10) 14 28 (9) Specified by design (10) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) production tested. 4 mΩ TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 TPS54972 Externally Composed Pin-Out 28 Pin HTSSOP PowerPAD (TOP VIEW) AGND VSENSE COMP STATUS BOOT PH PH PH PH PH PH PH PH PH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 THERMAL 22 21 PAD 20 19 18 17 16 15 RT ENA REFIN VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND PGND TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor, and SYNC pin. Connect PowerPAD connection to AGND. BOOT 5 Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE ENA 27 Enable input. Logic high enables oscillator, PWM control, and MOSFET driver circuits. Logic low disables operation and places device in a low quiescent current state. PGND 15-19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6-14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. REFIN 26 External reference input. High impedance input to slow-start and error amplifier circuits. STATUS 4 Open drain output. Asserted low when VIN < UVLO, VBIAS and internal reference are not settled or the internal shutdown signal is active. Otherwise STATUS is high. VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor. VIN 20-24 VSENSE 2 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. Error amplifier inverting input. Connect to output voltage compensation network/output divider. 5 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 INTERNAL BLOCK DIAGRAM VIN ENABLE COMPARATOR ENA VIN 1–4 µs VIN UVLO COMPARATOR Rising Edge Delay /T_SHUT FAULT BIAS UVLO BG GOOD Delay REFIN Vin_uvlo BIAS REG VIN Falling Edge Delay 0.8 V VDDQ Vbias SHUTDOWN UVLO highdr UVLO highin TPS54972 Rising Edge Delay SHUTDOWN SAMPLING LOGIC VPHASE Vilim VIN BOOT SHUTDOWN ILIM COMPARATOR SHUTDOWN highin highdr Reference/DAC VSENSE MUX PWM COMPARATOR ERROR AMPLIFIER R Q C S PGND SHUTDOWN OSC Ct Iset AGND RT RELATED DC/DC PRODUCTS • • • 6 TPS54372 TPS54672 TPS54872 Lout PH DEADTIME FAULT STATUS O V TTQ TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 25 10 5 0 25 85 TJ – Junction Temperature – °C f – Internally Set Oscillator Frequency – kHz 15 0 –40 VI = 3.6 V IO = 9 A 20 15 10 5 0 –40 125 0 25 85 125 750 650 550 450 RT = Open 350 250 –40 0 25 85 125 TJ – Junction Temperature – °C TJ – Junction Temperature – °C Figure 1 Figure 2 Figure 3 EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE DEVICE POWER LOSSES vs LOAD CURRENT INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE 8 RT = 68 kΩ 700 600 RT = 100 kΩ 500 400 RT = 180 kΩ 6 5 4 3 2 300 1 0 0 25 85 3.50 3.35 3.20 3.05 2.90 2.75 0 125 3.65 2 TJ – Junction Temperature – °C 4 6 8 10 12 14 16 Figure 4 –40 0 25 85 125 TJ – Junction Temperature – °C IL – Load Current – A Figure 5 Figure 6 ERROR AMPLIFIER OPEN LOOP RESPONSE 0 140 RL = 10 kΩ, CL = 160 pF, TA = 25°C 120 –20 –40 100 –60 80 Phase –80 –100 60 –120 40 Gain 20 –140 Phase – Degrees 200 –40 3.80 VI = 3.3 V TJ = 125°C fS = 700kHz 7 Internal Slow-Start Time – ms 800 Device Power Losses – W f – Externally Set Oscillator Frequency – kHz Drain Source On-State Reststance – m Ω 20 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 25 VIN = 3.0 V IO = 9 A Gain – dB Drain Source On-State Reststance – m Ω DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE –160 0 –180 –20 1 10 100 –200 1 k 10 k 100 k 1 M 10 M f – Frequency – Hz Figure 7 7 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 APPLICATION INFORMATION Figure 8 shows the schematic diagram for a typical TPS54972 application. The TPS54972 (U1) can provide up to 9 A of output current at a nominal output voltage of one half of V(DDQ) (typically 1.25 V). For proper operation, the PowerPAD underneath the integrated circuit TPS54972 is soldered directly to the printed-circuit board. COMPONENT SELECTION The values for the components used in this design example were selected for good transient response and small PCB area. Ceramic dielectric capacitors are utilized in the output filter circuit. A small size, small value output inductor is also used. Compensation network components are chosen to maximize closed loop bandwidth and provide good transient response characteristics. Additional design information is available at www.ti.com. INPUT VOLTAGE The input voltage is a nominal 3.3 VDC. The input filter (C4) is a 10-µF ceramic capacitor (Taiyo Yuden). Capacitor C8, a 10-µF ceramic capacitor (Taiyo Yuden) that provides high frequency decoupling of the TPS54972 from the input supply, must be located as close as possible to the device. Ripple current is carried in both C4 and C8, and the return path to PGND should avoid the current circulating in the output capacitors C7, C9, C11, and C12. FEEDBACK CIRCUIT The values for these components are selected to provide fast transient response times. Components R1, R2, R3, C1, C2, and C3 form the loop compensation network for the circuit. For this design, a type 3 topology is used. The transfer function of the feedback network is chosen to provide maximum closed loop gain available with open loop characteristics of the internal error amplifier. Closed loop cross-over frequency is typically between 70 kHz and 80 kHz for input from 3 V to 4 V. OPERATING FREQUENCY In the application circuit, RT is grounded through a 71.5 kΩ resistor to select the operating frequency of 700 kHz. To set a different frequency, place a 68-kΩ to 180-kΩ resistor between RT (pin 28) and analog ground or leave RT floating to select the default of 350 kHz. The resistance can be approximated using the following equation: 500 kHz R 100 [k] Switching Frequency (1) 8 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 VIN C4 10 µF R2 10 kΩ C2 470 pF C6 0.047 µF C1 12 pF R3 301 Ω R1 10 kΩ VDDQ U1 TPS54972PWP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C3 470 pF AGND RT VSENSE ENA COMP REFIN STATUS VBIAS BOOT VIN PH VIN PH VIN PH VIN VIN PH PH PGND PH PGND PH PGND PGND PH PH PGND PwrPad 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R6 10 kΩ C10 1 µF R5 71.5 kΩ R7 10 kΩ C13 0.1 µF C14 0.1 µF C8 10 µF VTTQ C12 1 µF C11 22 µF C9 22 µF C7 22 µF R4 2.4 Ω L1 0.65 µH C5 3300 pF Figure 8. Application Circuit OUTPUT FILTER The output filter is composed of a 0.65-µH inductor and three 22-µF capacitors. The inductor is a low dc resistance (0.017 Ω) type, Pulse PA0277 0.65-µH. The capacitors used are 22 µF, 6.3-V ceramic types with X5R dielectric. An additional 1-µF output capacitor (C12) is included to suppress high frequencies. GROUNDING AND POWERPAD LAYOUT The TPS54972 has two internal grounds (analog and power). Inside the TPS54972, the analog ground ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD must be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54972, particularly at higher output currents. However, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground areas are recommended. The analog ground area should be tied to the power ground area directly at the IC to reduce noise between the two grounds. The only components that should tie directly to the power ground area are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54972. The power ground areas as well as the PowerPAD mounting area should be tied to any internal ground planes using multiple vias. The layout of the TPS54972 evaluation module is representative of a recommended layout for a 4-layer board with the two internal layers representing the system ground plane. Documentation for the TPS54972 evaluation module can be found on the Texas Instruments web site under the TPS54972 product folder. 9 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 9 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance thermal performance should be included in areas not under the device package. 8 PL ∅ 0.0130 4 PL ∅ 0.0180 Connect Pin 1 to Analog Ground plane in this area for optimum performance Minimum recommended thermal vias: 8 x .013 dia. inside powerpad area 4 x .018 dia. under device as shown. Additional .018 dia. vias may be used if top side Analog Ground ar ea is extended. 0.0150 0.06 0.0339 0.0650 0.3820 0.0500 0.3478 0.0500 0.0500 0.2090 0.0256 0.0650 0.0339 0.1700 0.1340 Minimum recommended top side Analog Ground area Minimum recommended exposed copper area for powerpad. 5 mm stencils may required 10 percent larger area. 0.0603 0.0400 Figure 9. Recommended Land Pattern for 28-Pin PWP PowerPAD 10 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 PERFORMANCE GRAPHS TA = 25°C (unless otherwise noted) EFFICIENCY vs OUTPUT CURRENT 100 90 1.255 1.257 fs = 700 kHz VI = 3.3 V VO = 1.25 V 95 LINE REGULATION vs INPUT VOLTAGE LOAD REGULATION vs OUTPUT CURRENT 1.254 fs = 700 kHz VI = 3.3 V VO = 1.25 V 1.255 1.253 1.252 80 75 70 65 Line Regulation Load Regulation Efficiency – % 85 1.253 1.251 1.249 IO = 4.5 A 1.25 IO = 9 A 1.249 1.248 fs = 700 kHz VI = 3.3 V VO = 1.25 V 1.247 60 1.247 1.246 55 50 IO = 0 A 1.251 1.245 1.245 0 1 2 3 4 5 6 7 8 9 10 0 IO – Output Current – A Figure 10 2 4 6 8 IO – Output Current – A 3 10 3.5 4 VI – Input Voltage – V Figure 11 Figure 12 TRANSIENT RESPONSE Figure 13 VI = 3.3 V VO = 1.25 V VO – Output voltage – 500 mV/div 2.25 A to 6.75 A t – Time – 1 µs/div VI – Input Voltage 1V/div SLOW-START TIMING VI = 3.3 V VO = 1.25 V I O – Output Current –2 A/div VO – Output Voltage – 50 mV/div fs = 700 kHz, IO =9 A, VI = 3.3 V, VO = 1.25 V t – Time – µs/div t – Time – 2.5 µs/div Figure 14 Figure 15 AMBIENT TEMPERATURE vs OUTPUT CURRENT1 125 SOURCE-SINK TRANSIENT RESPONSE Figure 16 Ambient Temperature – ° C VI = 3.3 V VO = 1.25 V t – Time – 2.5 µs/div TJ = 125°C, fs = 700 kHz, VI = 5 V, VO = 1.25 V 115 I O – Output Current 5A/div VO – Output Voltage 50mV/div Output Ripple Voltage – 10 mV/div OUTPUT RIPPLE VOLTAGE 105 95 85 75 65 55 45 35 25 0 2 4 6 8 10 12 14 16 IO – Output Current – A 1. Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this data sheet. Figure 17 11 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 DETAILED DESCRIPTION UNDERVOLTAGE LOCKOUT (UVLO) The TPS54972 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.80 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. ENABLE (ENA) The enable pin, ENA, provides a digital control to enable or disable (shut down) the TPS54972. An input voltage of 1.4 V or greater ensures the TPS54972 is enabled. An input of 0.9 V or less ensures the device operation is disabled. These are not standard logic thresholds, even though they are compatible with TTL outputs. When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output starting from 0 V. SLOW-START The slow-start circuit provides start-up slope control control of the output voltage to limit in-rush currents. The nominal internal slow-start rate is 0.25 V/ms with the minimum rate being 0.35 V/ms. When the voltage on REFIN rises faster than the internal slope or is present when device operation is enabled, the output rises at the internal rate. If the reference voltage on REFIN rises more slowly, then the output rises at approximately the same rate as REFIN. VBIAS REGULATOR (VBIAS) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. VOLTAGE REFERENCE The REFIN pin provides an input for a user supplied tracking voltage. Typically this input is one half of V(DDQ). The input range for this external reference is 0.2 V to 1.75 V. Above this level, the internal bandgap reference overrides the externally supplied reference voltage. OSCILLATOR AND PWM RAMP The oscillator frequency can be set to an internally fixed value of 350 kHz by leaving the RT pin unconnected (floating). If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 700 kHz by connecting a resistor to the RT pin to ground. The switching frequency is approximated by the following equation, where R is the resistance from RT to AGND: Switching Frequency 100 k 500 [kHz] R The following table summarizes the frequency selection configurations: SWITCHING FREQUENCY RT PIN 350 kHz, internally set Float Externally set 280 kHz to 700 kHz R=68 kΩ to 180 kΩ ERROR AMPLIFIER The high performance, wide bandwidth, voltage error amplifier sets the TPS54972 apart from most dc/dc converters. The user has a wide range of output L and C filter components to suit the particular application needs. Type 2 or type 3 compensation can be employed using external compensation components. 12 www.ti.com TPS54972 SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 PWM CONTROL Signals from the error amplifier output, oscillator and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset, and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54972 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off, and the low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. DEAD-TIME CONTROL AND MOSFET DRIVERS Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn on until the gate drive voltage to the low-side FET is below 2 V, while the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω. bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. OVERCURRENT PROTECTION The cycle by cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100 ns leading edge blanking circuit prevents false tripping of the current limit when the high-side switch is turning on. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. THERMAL SHUTDOWN The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault condition, and then shutting down upon reaching the thermal limit trip point. This sequence repeats until the fault condition is removed. 13 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 STATUS The status pin is an open drain output that indicates when internal conditions are sufficient for proper operation. STATUS can be coupled back to a system controller or monitor circuit to indicate that the termination or tracking regulator is ready for start-up. STATUS is high impedance when the TPS54972 is operating or ready to be enabled. STATUS is active low if any of the following occur: VIN < UVLO threshold VBIAS or internal reference have not settled. Thermal shutdown is active. • • • 14 TPS54972 www.ti.com SLVS437A — AUGUST 2002 – REVISED DECEMBER 2002 MECHANICAL DATA PWR (R-PDSO-G**) PowerPAD™ PLASTIC SMALL-OUTLINE 20 PINS SHOWN 0,30 0,19 0,65 20 0,10 M 11 Thermal Pad (See Note D) 4,50 4,30 0,15 NOM 6,60 6,20 Gage Plane 1 10 0,25 0° –8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 14 16 20 24 28 A MAX 5,10 5,10 6,60 7,90 9,80 A MIN 4,90 4,90 6,40 7,70 9,60 DIM 4073225/F 10/98 (A) (B) (C) (D) All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusions. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. 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