SEMICONDUCTOR TECHNICAL DATA The MC10/100E445 is an integrated 4-bit serial to parallel data converter. The device is designed to operate for NRZ data rates of up to 2.0Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. The conversion sequence was chosen to convert the first serial bit to Q0, the second to Q1 etc. • • • • • • • • On-Chip Clock ÷4 and ÷8 4-BIT SERIAL/ PARALLEL CONVERTER 2.0Gb/s Data Rate Capability Differential Clock and Serial Inputs VBB Output for Single-Ended Input Applications Asynchronous Data Synchronization Mode Select to Expand to 8-Bits Internal 75kΩ Input Pulldown Resistors Extended 100E VEE Range of –4.2V to –5.46V SINA SINA Pin SINA, SINA SINB, SINB SEL Q0–Q3 CLK, CLK CL/4, CL/4 CL/8, CL/8 MODE SYNCH Function Differential Serial Data Input A Differential Serial Data Input B Serial Input Selector Pin Parallel Data Outputs Differential Clock Inputs Differential ÷4 Clock Output Differential ÷8 Clock Output Conversion Mode 4-Bit/8-Bit Conversion Synchronizing Input FUNCTION TABLES Mode Conversion SEL Serial Input L H 4-Bit 8-Bit H L A B 1 22 17 SOUT 28 16 VCC VEE 1 Figure 1. 28–Lead Pinout 15 (Top View) Q0 CLK 2 14 Q1 CLK 3 13 VCCO VBB 4 12 Q2 SINB 27 SEL 5 6 7 8 21 9 20 10 11 CL/8 CL/8 VCCO CL/4 CL/4 VCCO Q3 8/97 Motorola, Inc. 1997 23 SOUT 26 24 MODE NC VCCO 19 18 SINB 25 RESET PIN NAMES SYNC Two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the E446 parallel to serial converter. The start bit for conversion can be moved using the SYNC input. A FN SUFFIX single pulse applied asynchronously for at least two input clock cycles PLASTIC PACKAGE shifts the start bit for conversion from Qn to Qn–1. For each additional CASE 776-02 shift required an additional pulse must be applied to the SYNC input. Asserting the SYNC input will force the internal clock dividers to “swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn–1 output (see Timing Diagram B). The MODE input is used to select the conversion mode of the device. With the MODE input LOW, or open, the device will function as a 4-bit converter. When the mode input is driven HIGH the data on the output will change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E445’s. When cascaded in an 8-bit conversion scheme the devices will not operate at the 2.0Gb/s data rate of a single device. Refer to the applications section of this data sheet for more information on cascading the E445. For lower data rate applications a VBB reference voltage is supplied for single-ended inputs. When operating at clock rates above 500MHz differential input signals are recommended. For single-ended inputs the VBB pin is tied to the inverting differential input and bypassed via a 0.01µF capacitor. The VBB provides the switching reference for the input differential amplifier. The VBB can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design guide in the ECLinPS data book. Upon power-up the internal flip-flops will attain a random state. To synchronize multiple E445’s in a system the master reset must be asserted. REV 3 MC10E445 MC100E445 SINB SINB SINA D Q D Q Q3 D Q D Q Q2 D Q D Q Q1 D Q D Q Q0 SINA SEL SOUT SOUT 0 1 MODE CL/4 Out ÷4 CLK In Out CLK CL/4 R Latch EN CL/8 Out ÷2 SYNC D Q D CL/8 R Q RESET Figure 2. Logic Diagram MOTOROLA 2 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E445 MC100E445 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 150 85°C Max Min Typ 150 Max Unit 150 µA IIH Input HIGH Current VOH Ouput HIGH Current 10E (SOUT Only) 100E (SOUT Only) –1020 –1025 –790 –830 –980 –1025 –760 –830 –910 –1025 –670 –830 VBB Output Reference Voltage 10E 100E –1.38 –1.38 –1.27 –1.26 –1.35 –1.38 –1.25 –1.26 –1.31 –1.38 –1.19 –1.26 IEE Power Supply Current 10E 100E Condition V 1 1 V mA 154 154 185 185 154 154 185 185 154 177 185 212 1. The maximum VOH limit was relaxed from standard ECL due to the high frequency output design. All other outputs are specified with the standard 10E and 100E VOH levels. AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Characteristic Min fMAX Symbol Maximum Conversion Frequency 2.0 Typ tPLH tPHL Propagation Delay to Output CLK to Q CLK to SOUT CLK to CL/4 CLK to CL/8 1500 800 1100 1100 1800 975 1325 1325 ts Setup Time SINA, SINB SEL –100 0 th Hold Time SINA, SINB, SEL tRR 25°C Max Min Typ Max 2.0 Min Typ Max 2.0 Unit Condition Gb/s NRZ ps 1500 800 1100 1100 1800 975 1325 1325 –250 –200 –100 0 450 300 Reset Recovery Time 500 300 tPW Minimum Pulse Width CLK, MR 400 tr tf Rise/Fall Times SOUT Other 100 200 ECLinPS and ECLinPS Lite DL140 — Rev 4 85°C 2100 1150 1550 1550 2100 1150 1550 1550 1500 800 1100 1100 1800 975 1325 1325 –250 –200 –100 0 –250 –200 450 300 450 300 500 300 500 300 2100 1150 1550 1550 ps ps ps ps 400 400 ps 225 425 350 650 100 200 3 225 425 350 650 100 200 225 425 20%–80% 350 650 MOTOROLA MC10E445 MC100E445 Figure 3. Timing Diagrams CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 RESET Q0 Dn-4 Dn Q1 Dn-3 Dn+1 Q2 Dn-2 Dn+2 Q3 Dn-1 Dn+3 SOUT Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 CL/4 CL/8 Timing Diagram A. 1:4 Serial to Parallel Conversion CLK SIN Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 RESET SYNC Q0 Dn-4 Dn+1 Q1 Dn-3 Dn+2 Q2 Dn-2 Dn+3 Q3 Dn-1 Dn+4 SOUT Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn+4 CL/4 CL/8 Timing Diagram B. 1:4 Serial to Parallel Conversion With SYNC Pulse MOTOROLA 4 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E445 MC100E445 APPLICATIONS INFORMATION increased. The delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (Figure 6). The MC10E/100E445 is an integrated 1:4 serial to parallel converter. The chip is designed to work with the E446 device to provide both transmission and receiving of a high speed serial data path. The E445, can convert up to a 2.0Gb/s NRZ data stream into 4-bit parallel data. The device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. CLOCK CLOCK The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 4 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E445 has an extra buffer delay and thus should be used as the loop back serial input. E445a SERIAL INPUT DATA SIN SIN SOUT SOUT E445b SIN SIN Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 PARALLEL OUTPUT DATA PARALLEL DATA SOUT SOUT TO SERIAL MEDIUM 100ps CLOCK PARALLEL DATA Tpd CLK to SOUT SINA SINA SINB SINB 800ps FROM SERIAL MEDIUM 1150ps Figure 4. Loopback Test Architecture Figure 5. Cascaded 1:8 Converter Architecture With a minimum delay of 800ps on this output the clock for the lower order E445 cannot be delayed more than 800ps relative to the clock of the first E445 without potentially missing a bit of information. Because the setup time on the serial input pin is negative coincident excursions on the data and clock inputs of the E445 will result in correct operation. The E445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 5 illustrates the architecture for a 1:8 demultiplexer using two E445’s; the timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, TPD CLK to SOUT = 1150ps and tS for SIN = –100ps, yields a minimum period of 1050ps or a clock frequency of 950MHz. CLOCK A CLOCK B Tpd CLK to SOUT 800ps The clock frequency is significantly lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445 the frequency of operation can be ECLinPS and ECLinPS Lite DL140 — Rev 4 1150ps Figure 6. Cascade Frequency Limitation 5 MOTOROLA MC10E445 MC100E445 frequency up to 1.4GHz. The divide by eight clock of the second E445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two E445’s will no longer be synchronized. This skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses. Perhaps the easiest way to delay the second clock relative to the first is to take advantage of the differential clock inputs of the E445. By connecting the clock for the second E445 to the complimentary clock input pin the device will clock a half a clock period after the first E445 (Figure 7). Utilizing this simple technique will raise the potential conversion CLOCK CLOCK E445a SERIAL INPUT DATA SIN SIN 700ps (1.4GHz) E445b SOUT SOUT CLOCK A SIN SIN Q3 Q2 Q1 Q0 100ps CLOCK B Tpd CLK to SOUT Q3 Q2 Q1 Q0 800ps Q7 Q6 Q5 Q4 1150ps Q3 Q2 Q1 Q0 PARALLEL OUTPUT DATA Figure 7. Extended Frequency 1:8 Demultiplexer CLK SINa Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Q0 Dn-4 Q1 Dn-3 Q2 Dn-2 Q3 Dn-1 Q4 (Q0 a) Dn Q5 (Q1 a) Dn+1 Q6 (Q2 a) Dn+2 Q7 (Q3 a) Dn+3 SOUTa Dn-4 Dn-3 SOUTb Dn-2 Dn-1 Dn Dn+1 Dn+2 Dn+3 Dn-4 Dn-3 Dn-2 Dn-1 Dn Dn+1 CL/4a CL/4b CL/8a CL/8b Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion MOTOROLA 6 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E445 MC100E445 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). ECLinPS and ECLinPS Lite DL140 — Rev 4 T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) DIM A B C E F G H J K R U V W X Y Z G1 K1 7 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — MOTOROLA MC10E445 MC100E445 Motorola reserves the right to make changes without further notice to any products herein. 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