NL17SH00 Single 2-Input NAND Gate The NL17SH00 is an advanced high speed CMOS 2−input NAND gate fabricated with silicon gate CMOS technology. The internal circuit is composed of multiple stages, including a buffer output which provides high noise immunity and stable output. The NL17SH00 input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the NL17SH00 to be used to interface 5.0 V circuits to 3.0 V circuits. http://onsemi.com MARKING DIAGRAM Features • • • • • • High Speed: tPD = 3.0 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families These are Pb−Free Devices SOT−953 CASE 527AE A M AM 1 = Specific Device Code = Month Code PIN ASSIGNMENT 5 1 IN A GND 2 IN B 3 4 VCC 1 IN A 2 GND 3 IN B 4 OUT Y 5 VCC FUNCTION TABLE OUT Y Inputs Figure 1. Pinout (Top View) IN A & IN B OUT Y Output A B Y L L H H L H L H H H H L Figure 2. Logic Symbol ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2011 August, 2011 − Rev. 1 1 Publication Order Number: NL17SH00/D NL17SH00 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V −0.5 to VCC +0.5 V VOUT DC Output Voltage IIK DC Input Diode Current −20 mA IOK DC Output Diode Current ±20 mA IOUT DC Output Current ±25 mA ICC DC Supply Current per Supply Pin 50 mA −65 to +150 °C TSTG Storage Temperature Range TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias +150 °C PD Power Dissipation in Still Air 50 mW MSL Moisture Sensitivity FR Flammability Rating ILATCHUP Level 1 Oxygen Index: 28 to 34 Latchup Performance UL 94 V−0 @ 0.125 in Above VCC and Below GND at 125°C (Note 1) mA ±100 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Min Max Unit VCC DC Supply Voltage 2.0 5.5 V VIN DC Input Voltage 0.0 5.5 V DC Output Voltage 0.0 VCC V Operating Temperature Range −55 +125 °C 0 0 100 20 ns/V VCC = 3.3 V ± 0.3 V VCC = 5.0 V ± 0.5 V Time, Hours Time, Years 80 1,032,200 117.8 90 419,300 47.9 100 178,700 20.4 110 79,600 9.4 120 37,000 4.2 130 17,800 2.0 140 8,900 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 80°C Junction Temperature °C NORMALIZED FAILURE RATE DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES TJ = 90°C Input Rise and Fall Time TJ = 100°C tr , tf TJ = 110°C TA TJ = 120°C VOUT Parameter TJ = 130°C Symbol 1 1 10 100 1000 TIME, YEARS Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 NL17SH00 DC ELECTRICAL CHARACTERISTICS TA = 255C VCC Symbol Parameter Test Conditions (V) Min 1.5 2.1 3.15 3.85 VIH Minimum High−Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low−Level Input Voltage 2.0 3.0 4.5 5.5 VOH Minimum High−Level Output Voltage VIN = VIH or VIL VOL Maximum Low−Level Output Voltage VIN = VIH or VIL Typ TA v 855C Max Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 VIN = VIH or VIL IOH = −50 mA 2.0 3.0 4.5 1.9 2.9 4.4 VIN = VIH or VIL IOH = −4 mA IOH = −8 mA 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50 mA 2.0 3.0 4.5 VIN = VIH or VIL IOL = 4 mA IOL = 8 mA Max 2.0 3.0 4.5 0.0 0.0 0.0 *555C to 1255C Min Max 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 V 0.5 0.9 1.35 1.65 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 2.34 3.66 Unit V V 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5 V or GND 0 to 5.5 $0.1 $1.0 $1.0 mA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 1.0 10 40 mA AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns TA = 255C TA v 855C *555C to 1255C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Typ Max VCC = 3.3 $ 0.3 V CL = 15 pF CL = 50 pF 4.5 5.6 7.9 11.4 VCC = 5.0 $ 0.5 V CL = 15 pF CL = 50 pF 3.0 3.8 5.5 Symbol Parameter Test Conditions tPLH, tPHL Maximum Propagation Delay, Input A or B to Y CIN Min Maximum Input Capacitance Min Max Min Max Unit 9.5 13.0 11.0 15.5 ns 5.5 7.5 6.5 8.5 8.0 10.0 10 10 10 pF Typical @ 25°C, VCC = 5.0 V CPD 10 Power Dissipation Capacitance (Note 2) pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 NL17SH00 A or B VCC 50% GND tPLH Y tPHL 50% VCC Figure 4. Switching Waveforms VCC OUTPUT INPUT CL* *Includes all probe and jig capacitance. A 1−MHz square input wave is recommended for propagation delay tests. Figure 5. Test Circuit ORDERING INFORMATION Device NL17SH00P5T5G Package Shipping† SOT−953 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 NL17SH00 PACKAGE DIMENSIONS SOT−953 CASE 527AE ISSUE E X D PIN ONE INDICATOR 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF THE BASE MATERIAL. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. A Y 4 HE E 1 2 3 DIM A b C D E e HE L L2 L3 C TOP VIEW SIDE VIEW e L 5X 5X L3 MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 0.10 0.15 0.20 0.07 0.12 0.17 0.95 1.00 1.05 0.75 0.80 0.85 0.35 BSC 0.95 1.00 1.05 0.175 REF 0.05 0.10 0.15 −−− −−− 0.15 SOLDERING FOOTPRINT* 5X 0.35 5X 0.20 5X L2 5X BOTTOM VIEW b PACKAGE OUTLINE 0.08 X Y 1.20 1 0.35 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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