Ordering number : ENA0844A Bi-CMOS LSI LV8092GQ Piezo Actuator Driver IC Overview The LV8092GQ is a piezoelectric actuator driver IC. It internally generates drive waveforms and this makes it possible to control piezoelectric actuators with simple instructions. Features • Actuators using piezoelectric elements can be driven simply by I2C communication. • The piezoelectric drive waveforms are set externally by serial input signals using the I2C interface. • The rising and falling timings are determined with clock count. • EN input that controls the startup/stop of the IC. • The time for which the actuator is driven is determined with the drive frequency setting based on I2C communication. • Provides a busy signal output during periods when the actuator is being driven by OUT pin output so that applications can be aware of the actuator operating/stopped state. • Built-in thermal protection and undervoltage protection circuits Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage VCC max -0.5 to 6.0 Signal system supply voltage VDD max -0.5 to 6.0 Output current IO max Input signal voltage VIN max Allowable power dissipation Pd 300 -0.5 to VDD+0.5 *Mounted on a specified board. 700 V V mA V mW Operating temperature Topr -30 to +85 °C Storage temperature Tstg -55 to +150 °C * Specified board : 50mm×40mm×0.8mm, 4-layer glass epoxy circuit board. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 83107 MS / 71807 MS PC 20070402-S00001 No.A0844-1/12 LV8092GQ Allowable Operating Conditions at Ta = 25°C, GND = 0V Parameter Symbol Conditions Ratings Unit Supply voltage VCC 2.5 to 3.3 Signal system supply voltage VDD 1.6 to 3.3 V Input signal voltage VIN 0 to VDD V Maximum operating frequency Set STP count × 512 Ct max V Times Electrical Characteristics at Ta = 25°C, VCC = 2.8V, GND = 0V, unless otherwise specified. Parameter Symbol Ratings Conditions min Standby mode current drain ICC0 No CLK input, When EN = L Operating mode current drain ICC1 CLK = 10MHz, When EN = H Unit typ max 0.7 1.0 µA 1.5 mA High-level input voltage VIH 1.6V ≤ VDD ≤ 3.3V EN, SCL, SDA, RESET 0.8×VDD VDD V Low-level input voltage VIL 1.6V ≤ VDD ≤ 3.3V EN, SCL, SDA, RESET 0 0.2×VDD V CLK, TEST pin high-level input VIH2 CLK, TEST1/2 0.5×VCC VCC V VIL2 CLK, TEST1/2 0 0.1×VDD V Low voltage detection voltage Vres VCC voltage 2.1 2.25 2.4 V Thermal protection temperature TSD *1 150 180 210 °C Output block upper-side on RonP 1.0 1.5 Ω RonN 1.0 1.5 Ω voltage CLK, TEST pin low-level input voltage resistance Output block lower-side on resistance Turn on time TPLH With no load *2 0.2 µS Turn off time TPHL With no load *2 0.2 µS *1 : Design guaranteed value (no measurement is performed) *2 : Rising time from 10 to 90% and falling time from 90 to 10% are specified with regard to the OUT pin voltage. Package Dimensions unit : mm (typ) 3341 Pd max -- Ta SIDE VIEW TOP VIEW BOTTOM VIEW (0.125) 2.6 0.4 2.6 (0.13) (C0.116) 16 0.5 2 1 (0.55) 0.25 0.6 SIDE VIEW Allowable power dissipation, Pd max – W 0.8 0.6 0.4 0.36 0.2 0 – 20 (0.035) Specified board : 50.0×40.0×0.8mm3 4-layer glass epoxy 0.7 0 20 40 60 80 85 100 Ambient temperature, Ta – °C SANYO : UCT16(2.6X2.6) No.A0844-2/12 LV8092GQ Pin Assignment VCC (NC) (NC) VDD 16 15 14 13 BUSY 1 12 TEST2 OUT2 2 11 GND (TOP VIEW) REG 3 10 EN OUT1 4 9 5 6 7 8 TEST1 CLK SCL SDA RESET Block Diagram VCC OUT1 OUT2 RFG BUSY TEST1 Thermal protection circuit Piezoelectric drive waveform generation register Startup control block Output control TEST2 I2C interface Level shifter VDD GND EN CLK SCL SDA RESET Microcontroller input voltage Value of the resistor connected to the RFG pin Inrush current flowing to the piezoelectric elements can be controlled in the LV8092GQ by inserting a resistor between the RFG pin and GND potential. Since the resistance affects the actuator operation, the constant must be determined in a range from 0 to 3.3Ω while monitoring the operation of the actuator. Capacitor on the VCC line Piezoelectric actuators are capacitive loads in electrical terms, and they operate units by charging and discharging the charges. Since the charge between the capacitor on the VCC line and piezoelectric elements is transferred, the capacitor must be mounted near the VCC pin. The capacitance of the capacitor required is determined by the capacitance of the piezoelectric element. A capacitance within a range that does not affect operation must be selected. No.A0844-3/12 LV8092GQ Serial Bus Communication Specifications I2C serial transfer timing conditions twH SCL th1 twL th2 tbuf SDA th1 ts2 ts1 ts3 Resend start condition Start condition ton Stop condition tof Input waveform condition Standard mode Parameter symbol Conditions SCL clock frequency fscl SCL clock frequency Data setup time ts1 ts2 Data hold time Pulse width Input waveform conditions Bus free time min typ max unit 0 - 100 kHz Setup time of SCL with respect to the falling edge of SDA 4.7 - - Setup time of SDA with respect to the rising edge of SCL 250 - - ns ts3 Setup time of SCL with respect to the rising edge of SDA 4.0 - - µs th1 Hold time of SCL with respect to the rising edge of SDA 4.0 - - µs th2 Hold time of SDA with respect to the falling edge of SCL 0 - - µs twL SCL low period pulse width 4.7 - - µs twH SCL high period pulse width 4.0 - - µs ton SCL/SDA (input) rising time - - 1000 ns tof SCL/ SDA (input) falling time - - 300 ns tbuf Interval between stop condition and start condition 4.7 - - µs µs High-speed mode Parameter Symbol Conditions min typ Clock frequency of SCL Data setup time ts1 Setup time of SCL with respect to the falling edge of SDA 0.6 ts2 Setup time of SDA with respect to the rising edge of SCL 100 ns ts3 Setup time of SCL with respect to the rising edge of SDA 0.6 µs th1 Hold time of SCL with respect to the rising edge of SDA 0.6 µs th2 Hold time of SDA with respect to the falling edge of SCL 0 µs twL SCL low period pulse width 1.3 µs twH SCL high period pulse width 0.6 ton SCL/SDA (input) rise time 300 ns tof SCL/SDA (input) fall time 300 ns tbuf Interval between the stop condition and the start condition Pulse width Input waveform conditions Bus free time 1.3 400 unit fscl Data hold time 0 max SCL clock frequency kHz µs µs µs No.A0844-4/12 LV8092GQ I2C bus transfer method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition th1 th3 SCL SDA Data transfer and acknowledgement response After the start condition is generated, data is transferred one byte (8 bits) at a time. Any number of data bytes can be transferred consecutively. An ACK signal is sent to the sending side from the receiving side every time 8 bits of data are transferred. The transmission of an ACK signal is performed by setting the receiving side SDA to low after SDA at the sending side is released immediately after the clock pulse of SCL bit 8 in the data transferred has fallen low. After the receiving side has sent the ACK signal, if the next byte transfer operation is to receive only the byte, the receiving side releases SDA on the falling edge of the 9th clock of SCL. There are no CE signals in the I2C bus ; instead, a 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) which specifies the direction of subsequent data transfer. The LB8092GQ is a drive IC with a dedicated write function and it does not have a read function. The 7-bit address is transferred in sequence starting with MSB, and the eighth bit is set to low. The second and subsequent bytes are transferred in write mode. In the LV8092GQ, the slave address is stipulated to be “1110010.”. Start M S B Slave address L S B W A C K M S B Register address L S B A C K M S B Data L S B A C K Stop SCL SDA 1 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 No.A0844-5/12 LV8092GQ Serial Map Register Address Data A7 A6 A5 A4 A3 A2 A1 A0 D7 0 0 0 0 0 0 0 0 M/I 0 0 0 0 0 0 0 0 0 0 0 1 GATE × × CKSEL [1 : 0] 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 5 0 0 0 0 1 1 1 7 D2 D1 0 0 D0 0 0 RET [1 : 0] 0 INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST [7 : 0] 0 GTAS [7 : 0] 0 0 0 0 0 0 0 0 0 GTBR [7 : 0] 0 GTBS [7 : 0] 0 6 D3 DRVPULSE [6 : 0] 0 4 0 D4 1 3 0 D5 0 2 0 D6 0 0 0 0 STP [7 : 0] 0 0 0 0 × × × × 0 0 0 0 0 INITMOV [7 : 4] 0 0 0 0 Upper : Register name Lower : Default value Serial Mode Settings 0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D0 to D6: DRVPULSE [6 : 0] Operation count setting register. Specify a number from 0 to 127. The number of cyclic operations determined by <DRVPLUSE setting> × <STP setting> are performed. Additional data can be input and data is added up to the equivalent of total of 512 pulses. D7 M/I 0 ∞ 1 macro Operation direction switching *Default Infinity distance direction Macro direction Operation direction switching register The operation count setting register is reset when the register is switched. To stop the operation of the unit, switch the M/I register and set DRVPULSE to 0 for input. This register is also used to set the direction of operation when the initialization sequence is to be performed. No.A0844-6/12 LV8092GQ 1 0 0 0 0 0 0 0 1 D7 0 0 D4 D3 D2 D1 D0 D0: Register for selecting whether the initialization sequence is to be performed when EN is set high. D0 INIT Initialization to be performed/not to be performed setting 0 Initialization to be performed *Default 1 Initialization not to be performed D0 D1 0 0 2 times 0 1 1 time 1 0 3 times 1 1 4 times D4 D3 0 0 2 0 Input clock division ratio switching *Default 1/4 1/2 1 (no frequency division) 1 (no frequency division) CKSEL 1/4 0 1 1/2 1 0 1 1 1 1 D7 Number of initialization sequence swing back *Default RET GATE Gate mode operation 0 MODE1 *Default 1 MODE2 0 0 Forward/reverse/braking Forward/reverse/standby 0 0 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 D2 D1 D0 RST7 to RST0 : Specifies the number of clocks per period (0 to 255). Default = 0 (Internally set to 115 when TEST = H and RESET = L.) 3 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 GTAS7 to GTAS0 : Sets the GATE_A pulse set value (0 to 255). Default = 0 (Internally set to 21 when TEST = H and RESET = L.) 4 0 0 0 0 0 1 0 0 D7 D6 D5 D4 D3 GTBR7 to GTBR0 : Sets the GATE_B pulse reset value (0 to 255). Default = 0 (Internally set to 24 when TEST = H and RESET = L.) No.A0844-7/12 LV8092GQ 5 0 0 0 0 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 GTBS7 to GTBS0 : Sets the GATE_B pulse set value (0 to 255). Default = 0 (Internally set to 54 when TEST = H and RESET = L.) RST7-0 GTAS7-0 GATEA GTBS7-0 GTBR7-0 GATEB 6 0 0 0 0 0 1 1 0 D7 D6 D5 D4 D3 STP7 to STP0 : Specifies the number of output pulse steps with regard to DRIVE input (1 to 256). Default = 1 The setting value range is handled as the data value plus 1. When data is input in 8-bit units (0 to 255), it is handled as an STP period of 1 to 256. (Internally set to 139=140 periods when TEST = H and RESET = L.) 7 0 0 0 0 0 1 1 1 0 0 0 0 D3 D2 D1 D0 INITMOV7 to INITMOV4 : Sets the number of swing back of the initialization sequence to be performed (16 to 256). Default = 16 (Internally set to 175 when TEST = H and RESET = L.) D3 D2 D1 D0 INIT7 to 4 16 to 256 0 0 0 0 0 15 0 0 0 1 1 31 0 0 1 0 2 47 0 0 1 1 3 63 0 1 0 0 4 79 0 1 0 1 5 95 0 1 1 0 6 111 0 1 1 1 7 127 1 0 0 0 8 143 1 0 0 1 9 159 1 0 1 0 10 175 1 0 1 1 11 191 1 1 0 0 12 207 1 1 0 1 13 223 1 1 1 0 14 239 1 1 1 1 15 255 No.A0844-8/12 LV8092GQ Functional Description 1 period : One period of OUT waveform operation is equivalent to one output operation. Tf = 1 period EN input : A low-level EN input causes the IC to stop operation, placing the IC in the standby mode to save current consumption. A high-level EN input starts the IC. After performing the initialization sequence according to the predefined startup sequence, the IC starts operation due to DRVPULSE (when the initialization sequence is to be performed). The IC accepts I2C communication whether EN is high or low. Initialization sequence (on or off and direction can be set by I2C) : This is an internal sequence in which the actuator is moved to the initial position when the IC is started up. Setting EN from low to high initiates this initialization sequence. The presence or absence of the initialization operation can be set using the initialization mode select register (INIT). If the initialization operation is specified, the direction of the initialization sequence can be set using the M/I register. • M/I register = 0 : Initialization processing in infinity direction The IC performs the number of operations determined by STP setting period × INIT setting times in the infinite direction, then waits for the period equivalent to STP setting period × 4 times, and performs the number of swing back operations equal to STP setting period × RET setting times in the macro direction. • M/I register = 1 : Auto macro operation in macro direction The IC performs the number of operations determined by STP setting period × INIT setting times in the macro direction, then waits for the period equivalent to STP setting periods × 4, and performs the number of swing back operations equal to STP period setting period × RET setting times in the infinity direction. RESET input : The input pin to reset the internal registers. When it is low, the counter is reset. When it is high the reset state is released. The reset input needs to be held high when I2C communication is in progress. TEST1 pin : This is a setting pin used when the IC is tested. It must be short-circuited to ground when the IC is used in a real application. When this pin is set high, a test counter value is loaded into the internal register, and it can no longer be set in I2C communication. TEST2 pin : This is a setting pin used when the IC is tested. It must be short-circuited to ground when the IC is used in a real application. When this pin is set high, the IC is ready for continuous output operation and continues operation in the infinity direction. BUSY output : This is an output signal pin that is held high (H = VDD voltage) while the actuator is in operation and set low when the actuator is stopped. VDD : This is a power voltage pin for the input pins. It supplies power to the EN, SCL, SDA, and RESET pins. Each input pin is provided with an internal level shifter circuit, so that it is not affected by potential difference from the VCC voltage (the CLK and TEST pins accept input with respect to the VCC voltage level). CLK input : The pin for the external CLK input that provides the reference time for generating drive waveforms. The frequency division ratio for I2C communication can be selected from 1/4, 1/2, and 1/1. Drive waveforms are generated by counting this frequency-divided clk pulses as the basic count unit. The LV8092GQ supports frequency from 10MHz to 60MHz depending on the frequency division ratio and counter settings. No.A0844-9/12 LV8092GQ Actuator drive waveform settings : Configuration of piezoelectric actuator drive waveform f = 1 period Ta off Tb Since the counter starts from zero, a value minus 1 is set. Drive parameter settings RST = Number of clock pulses in period minus 1 GTAS = Ta + 1 Ta - 1 + 2 = Ta + 1 since the waveforms start after two clock pulses. Rises here after two clock pulses from reference. GTBR = GTAS + off Waveform start reference point GTBS = GTBR + Tb The drive waveforms are set using four parameters: RST, GTAS, GTBR and GTBS. RST : Parameter determines the period, and sets the reference clock pulse count minus 1. GTAS : Parameter determines the time taken for the gate signal A to the falling edge from the reference point. Since the signal raises after two clock pulses from the reference, the Ta reference clock cycle count plus 1 is set. GTBR : Parameter determines the time taken for the gate signal B to the rising edge from the reference point. It sets the value obtained by adding the reference clock pulse count during the time from GTAS to “off.” GTBS : Parameter determines the time taken for the gate signal B to the falling ewdge from the reference point. It sets the value obtained by adding the reference clock pulse count during the time from GTBR to “Tb.” [Example of settings] When setting reference clock to 10MHz, period to 13µs, Ta to 2.0µs, off to 0.3µs, and Tb to 3.0µs Since the reference clock time is 0.1µs : The period is 130 clks. → Specify 129 (RST value of 130 -1). Ta is 20 clks. → Specify 21 (GTAS value of 20 + 1). off is 3 clks. → Specify 24 (GTBR value of 21 + 3). Tb is 30 clks. → Specify 54 (GTBS value of 24 + 30). No.A0844-10/12 LV8092GQ Timing charts Enlarged view of the sequence of output signals (RST setting + 1) × number of clock pulses Operation toward infinity (GTAS setting - 1) × number of clock pulses (GTAS setting - 1) × number of clock pulses OUT1 (GTAS setting - 1) × number of clock pulses OUT2 (GTBR setting -1) × number of clock pulses (RST setting + 1) × number of clock pulses Operation toward macro (GTBR setting -1) × number of clock pulses OUT1 (GTBS setting - 1) × number of clock pulses OUT2 (GTAS setting - 1) × number of clock pulses (GTAS setting - 1) × number of clock pulses Sequence of initial setting operation (“on” or “off” can be set by the I2C settings.) When M/I register = 00 → Movement toward infinity position Startup when EN is high, initial setting sequence starts EN 1 period OUT1 OUT2 Operation toward infinity Standby state STP period × INIT times STP period × 4 STP period × RET setting times Operation toward macro Initial setting operation time BUSY High during initial setting in wait state too BUSY output is low after initial setting. BUSY output is high during initial setting operation. When M/I register = 01 → Movement toward macro position Startup when EN is high, initial setting sequence starts EN OUT1 1 period OUT2 Operation toward macro STP period × INIT times Standby state Operation toward infinity STP period × 4 STP period × RET setting times Initial setting operation time BUSY High during initial setting in wait state too BUSY output is high during initial setting operation. BUSY output is low after initial setting. No.A0844-11/12 LV8092GQ Sequence of operations triggered by DRVPULSE input EN Infinity direction logic selection M/I register state Operation stops when EN input is low. Macro direction logic selection I2C communication operation instruction completed 00000000_00000010 (operation 2 times toward infinity) DRVPULSE setting OUT1 I2C communication operation instruction completed 00000000_10000010 (operation 2 times toward macro) Equivalent to 2 pulses = STP setting period × operation for 2 times 1 period Operation toward infinity (STP setting period × 2 times) Operation toward macro OUT2 I2C communication Operation starts on completion of DRVPULSE input. Return to high when EN is set to low even before the completion of the operation. BUSY BUSY output high, only during operation period Gate setting output logic 1 period GATE MODE1 : Forward, Braking, Reverse Forward Forward Output mode OUT1 Braking Braking OUT2 on OUT1 1 period Forward Forward OUT1 Wait Wait OUT2 off on OUT2 OUT1 off Reverse GATE MODE2 : Forward, Wait, Reverse off OUT2 on on off Forward Reverse off off off OUT1 off OUT2 OUT1 on on OUT2 off Braking off Wait Reverse SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of August, 2007. Specifications and information herein are subject to change without notice. PS No.A0844-12/12