SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 FEATURES • • • • • • • • • • • Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Low Static-Power Consumption (ICC = 0.0 µA Max) Low Dynamic-Power Consumption (Cpd = 4 pF Typ at 3.3 V) Low Input Capacitance (Ci = 1.5 pF Typ) Low Noise – Overshoot and Undershoot <10% of VCC Input-Disable Feature Allows Floating Input Conditions Ioff Supports Partial-Power-Down Mode Operation Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input DBV PACKAGE (TOP VIEW) OE 1 2 GND 3 • • DCK PACKAGE (TOP VIEW) OE VCC 5 A A • • • Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation tpd = 4.6 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 – 2000-V Humna-Body Model (A114-B, Class II) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) ESD Protection Exceeds ±5000 V With Human-Body Model 1 5 VCC 1 OE A 2 GND GND 3 4 YEP OR YZP PACKAGE (BOTTOM VIEW) DRL PACKAGE (TOP VIEW) 5 VCC GND 2 A 3 OE 4 Y Y 3 4 2 1 5 VCC Y Y 4 See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2). xxxx Switching Characteristics Static-Power Consumption Dynamic-Power Consumption (µA) (pF) 100% at 25 MHz† 3.5 3 80% Voltage − V 100% 80% 60% 60% 3.3-V Logic† 40% 40% 20% 3.3-V LVC Logic† 0% † 0% Input 2 1.5 1 Output 0.5 20% AUP 2.5 AUP Single, dual, and triple gates Figure 1. AUP – The Lowest-Power Family 0 −0.5 0 † 5 10 15 20 25 30 Time − ns 35 40 45 AUP1G08 data at CL = 15 pF Figure 2. Excellent Signal Integrity xxx Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA PACKAGE (1) ORDERABLE PART NUMBER NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP SN74AUP1G125YEPR Reel of 3000 NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) –40°C to 85°C SOT (SOT-23) – DBV SOT (SOT-553) – DRL (2) _ _ _ HM _ SN74AUP1G125YZPR SOT (SC-70) – DCK (1) Reel of 3000 SN74AUP1G125DBVR Reel of 250 SN74AUP1G125DBVT Reel of 3000 SN74AUP1G125DCKR Reel of 250 SN74AUP1G125DCKT Reel of 4000 SN74AUP1G125DRLR H25_ HM_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUTS (1) OE A OUTPUT Y L H H L L L H X (1) Z Floating inputs allowed. LOGIC DIAGRAM (POSITIVE LOGIC) OE A 2 TOP-SIDE MARKING (2) 1 2 4 Y SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 4.6 V –0.5 4.6 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Output voltage range in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±20 mA Continuous current through VCC or GND ±50 mA θJA Tstg (1) (2) (3) Package thermal impedance (3) Storage temperature range DBV package 206 DCK package 252 DRL package 142 YEP/YZP package 132 –65 150 V °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 Recommended Operating Conditions (1) VCC Supply voltage VCC = 0.8 V VIH High-level input voltage VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V MIN MAX 0.8 3.6 VCC 3.6 0.65 × VCC 3.6 1.6 3.6 2 3.6 VCC = 0.8 V VIL Low-level input voltage VO Output voltage IOH High-level output current Low-level output current VCC = 1.1 V to 1.95 V 0 0.35 × VCC VCC = 2.3 V to 2.7 V 0 0.7 VCC = 3 V to 3.6 V 0 0.9 Active state 0 VCC 3-state 0 3.6 VCC = 0.8 V –20 VCC = 1.1 V –1.1 VCC = 1.4 V –1.7 VCC = 1.65 V –1.9 VCC = 2.3 V –3.1 Input transition rise or fall rate TA Operating free-air temperature (1) 4 V V V µA mA –4 VCC = 0.8 V 20 VCC = 1.1 V 1.1 VCC = 1.4 V 1.7 VCC = 1.65 V 1.9 VCC = 2.3 V 3.1 VCC = 3 V ∆t/∆v V 0 VCC = 3 V IOL UNIT µA mA 4 VCC = 0.8 V to 3.6 V –40 200 ns/V 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow of Floating CMOS Inputs, literature number SCBA004. SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOL TEST CONDITIONS TA = –40°C to 85°C MAX MIN VCC – 0.1 VCC – 0.1 IOH = –1.1 mA 1.1 V 0.75 × VCC 0.7 × VCC IOH = –1.7 mA 1.4 V 1.11 1.03 IOH = –1.9 mA 1.65 V 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 IOH = –2.7 mA IOH = –4 mA 2.3 V 3V IOL = 20 µA 0.8 V to 3.6 V IOL = 1.1 mA 2.6 MAX UNIT V 2.55 0.1 0.1 1.1 V 0.3 × VCC 0.3 × VCC IOL = 1.7 mA 1.4 V 0.31 0.37 IOL = 1.9 mA 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 0 V to 3.6 V 0.1 0.5 µA IOL = 2.3 mA IOL = 3.1 mA IOL = 2.7 mA IOL = 4 mA II TYP 0.8 V to 3.6 V IOH = –3.1 mA A or OE input TA = 25°C MIN IOH = –20 µA IOH = –2.3 mA VOL VCC VI = GND to 3.6 V 2.3 V 3V V Ioff VI or VO = 0 V to 3.6 V 0V 0.2 0.6 µA ∆Ioff VI or VO = 0 V to 3.6 V 0 V to 0.2 V 0.2 0.6 µA IOZ VO = VCC or GND 0.5 µA ICC VI = GND or (VCC to 3.6 V), OE = GND, IO = 0 0.5 0.9 µA 40 50 110 120 0 0 A input ∆ICC OE input All inputs 0.8 V to 3.6 V VI = VCC – 0.6 V (1), IO = 0 3.3 V VI = GND to 3.6 V, OE = VCC (2) 0.8 V to 3.6 V Ci VI = VCC or GND Co VO = VCC or GND (1) (2) 3.6 V 0V 1.5 3.6 V 1.5 3.6 V 3 µA pF pF One input at VCC – 0.6 V, other input at VCC or GND To show ICC is very low when the input-disable feature is enabled 5 SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A Y OE Y 6 OE Y UNIT MAX MIN MAX 18.1 4.3 7.4 12.6 2.7 15.3 1.5 V ± 0.1 V 3.3 5.2 8.5 1 10.2 1.8 V ± 0.15 V 2.6 4.1 6.8 1.3 8.3 2.5 V ± 0.2 V 2 2.9 4.7 1.1 5.8 3.3 V ± 0.3 V 1.7 2.4 3.8 1 4.6 ns 19.1 1.2 V ± 0.1 V 5.1 9.3 15.9 3.6 19.2 1.5 V ± 0.1 V 4.1 6.6 10.5 2.5 12.7 1.8 V ± 0.15 V 3.2 5.3 8.7 2.1 10.3 2.5 V ± 0.2 V 2.5 3.8 6 1.6 7.2 3.3 V ± 0.3 V 2.1 3.2 4.9 1.4 5.9 0.8 V tdis TYP 1.2 V ± 0.1 V 0.8 V ten TA = –40°C to 85°C TA = 25°C VCC ns 12.1 1.2 V ± 0.1 V 2.4 4.1 6.9 2.2 7.7 1.5 V ± 0.1 V 1.8 2.9 4.5 1.7 5.1 1.8 V ± 0.15 V 1 2.9 4.3 1.5 4.7 2.5 V ± 0.2 V 1 1.8 2.7 1 3.3 3.3 V ± 0.3 V 1.2 2.2 3.2 1.1 4 ns SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A or B Y OE Y OE Y MAX UNIT MIN MAX 20.5 13.7 4.6 8.4 9.3 3.6 16.6 1.5 V ± 0.1 V 3.5 5.9 7.5 2.4 11.1 1.8 V ± 0.15 V 3.9 4.7 5.3 1.3 9.1 2.5 V ± 0.2 V 2.3 3.4 4.3 1.6 6.4 3.3 V ± 0.3 V 2.1 2.8 1.4 5.2 21.8 16.8 1.2 V ± 0.1 V 4.9 10.2 11.2 4.4 20.2 1.5 V ± 0.1 V 3.9 7.3 9.2 3.3 13.5 1.8 V ± 0.15 V 3.4 5.8 6.4 2.7 11 2.5 V ± 0.2 V 2.5 4.3 5.4 2.1 7.8 3.3 V ± 0.3 V 2.1 3.7 1.9 6.4 0.8 V tdis TYP 1.2 V ± 0.1 V 0.8 V ten TA = –40°C to 85°C TA = 25°C VCC ns ns 13 1.2 V ± 0.1 V 3.8 6.6 11.7 1.2 14 1.5 V ± 0.1 V 2.2 4.7 7.9 1.3 9.3 1.8 V ± 0.15 V 2.4 4.4 6.4 2.2 7.5 2.5 V ± 0.2 V 1.3 3.1 4.9 1.2 5.4 3.3 V ± 0.3 V 1.9 3.4 5 1.9 5.6 ns 7 SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Duration) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input VCC/2 0V tPLH tsu VOH VM Output VCC VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms 8 th SN74AUP1G125 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT www.ti.com SCES595E – JULY 2004 – REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC S1 5 kΩ From Output Under Test GND CL (see Note A) 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 0V tPZL tPLZ VCC VCC/2 tPZH Output Waveform 2 S1 at GND (see Note B) VCC/2 VOL + V∆ VOL tPHZ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Oct-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74AUP1G125DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G125DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G125DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G125DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74AUP1G125DRLRG4 ACTIVE SOP DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G125DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G125DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G125DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G125DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G125DRLR ACTIVE SOP DRL 5 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AUP1G125YZPR ACTIVE WCSP YZP 5 3000 SNAGCU Level-1-260C-UNLIM Pb-Free (RoHS) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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