TSC TSM4925D_08

TSM4925D
30V Dual P-Channel MOSFET
SOP-8
Pin Definition:
1. Source 1
8. Drain 1
2. Gate 1
7. Drain 1
3. Source 2
6. Drain 2
4. Gate 2
5. Drain 2
PRODUCT SUMMARY
VDS (V)
RDS(on)(mΩ)
-30
Features
ID (A)
25 @ VGS = -10V
-7.1
41 @ VGS = -4.5V
-5.5
Block Diagram
●
Advance Trench Process Technology
●
High Density Cell Design for Ultra Low On-resistance
Application
●
Load Switches
●
Notebook PCs
●
Desktop PCs
Ordering Information
Part No.
Package
Packing
TSM4925DCS RL
SOP-8
2.5Kpcs / 13” Reel
Dual P-Channel MOSFET
Absolute Maximum Rating (Ta = 25oC unless otherwise noted)
Parameter
Symbol
Limit
Unit
Drain-Source Voltage
VDS
-30
V
Gate-Source Voltage
VGS
±20
V
Continuous Drain Current
ID
-7.1
A
Pulsed Drain Current
IDM
-40
A
IS
-1.7
A
Continuous Source Current (Diode Conduction)
a,b
o
Maximum Power Dissipation
Ta = 25 C
PD
o
Ta = 75 C
Operating Junction Temperature
W
1.3
+150
o
C
TJ, TSTG
- 55 to +150
o
C
Symbol
Limit
TJ
Operating Junction and Storage Temperature Range
2.0
Thermal Performance
Parameter
Junction to Case Thermal Resistance
RӨJC
Junction to Ambient Thermal Resistance (PCB mounted)
RӨJA
Unit
30
o
C/W
50
o
C/W
Notes:
a. Pulse width limited by the Maximum junction temperature
b. Surface Mounted on FR4 Board, t ≤ 10 sec.
1/6
Version: A07
TSM4925D
30V Dual P-Channel MOSFET
Electrical Specifications (Ta = 25oC unless otherwise noted)
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
Static
Drain-Source Breakdown Voltage
VGS = 0V, ID = -250uA
BVDSS
-30
--
--
V
Gate Threshold Voltage
VDS = VGS, ID = -250µA
VGS(TH)
-1
--
-3
V
Gate Body Leakage
VGS = ±20V, VDS = 0V
IGSS
--
--
±100
nA
VDS = -30V, VGS = 0V
IDSS
--
--
-1.0
µA
VDS = -5V, VGS = -10V
ID(ON)
-40
--
--
A
--
20
25
--
33
41
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
Forward Transconductance
a
Diode Forward Voltage
Dynamic
a
VGS = -10V, ID = -7.1A
VGS = -4.5V, ID = -5.5A
RDS(ON)
mΩ
VDS = -10V, ID = -7.1A
gfs
--
24
--
S
IS = -1.7A, VGS = 0V
VSD
--
-0.8
-1.2
V
Qg
--
33
70
Qgs
--
5.8
--
Qgd
--
8.6
--
Ciss
--
1573
1900
Coss
--
319
--
Crss
--
211
295
td(on)
--
10
15
tr
--
15
25
td(off)
--
110
170
--
70
110
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching
VDS = -15V, ID = -7.1A,
VGS = -10V
VDS = -15V, VGS = 0V,
f = 1.0MHz
nC
pF
c
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
VDD = -15V, RL = 15Ω,
ID = -1A, VGEN = -10V,
RG = 6Ω
Turn-Off Fall Time
tf
Notes:
a. pulse test: PW ≤300µS, duty cycle ≤2%
b. For DESIGN AID ONLY, not subject to production testing.
b. Switching time is essentially independent of operating temperature.
2/6
nS
Version: A07
TSM4925D
30V Dual P-Channel MOSFET
Electrical Characteristics Curve (Ta = 25oC, unless otherwise noted)
Output Characteristics
Transfer Characteristics
On-Resistance vs. Drain Current
Gate Charge
On-Resistance vs. Junction Temperature
Source-Drain Diode Forward Voltage
3/6
Version: A07
TSM4925D
30V Dual P-Channel MOSFET
Electrical Characteristics Curve (Ta = 25oC, unless otherwise noted)
On-Resistance vs. Gate-Source Voltage
Threshold Voltage
Single Pulse Power
Normalized Thermal Transient Impedance, Junction-to-Ambient
4/6
Version: A07
TSM4925D
30V Dual P-Channel MOSFET
SOP-8 Mechanical Drawing
DIM
A
B
C
D
F
G
K
M
P
R
SOP-8 DIMENSION
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX.
4.80
5.00
0.189
0.196
3.80
4.00
0.150
0.157
1.35
1.75
0.054
0.068
0.35
0.49
0.014
0.019
0.40
1.25
0.016
0.049
1.27BSC
0.05BSC
0.10
0.25
0.004
0.009
0º
7º
0º
7º
5.80
6.20
0.229
0.244
0.25
0.50
0.010
0.019
Marking Diagram
Y = Year Code
M = Month Code
(A=Jan, B=Feb, C=Mar, D=Apl, E=May, F=Jun, G=Jul, H=Aug,
I=Sep, J=Oct, K=Nov, L=Dec)
L = Lot Code
5/6
Version: A07
TSM4925D
30V Dual P-Channel MOSFET
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6/6
Version: A07