SCES578 – JUNE 2004 D Available in the Texas Instruments D D D D D D D D NanoStar and NanoFree Packages Low Static-Power Consumption; ICC = 0.9-µA Max Low Dynamic-Power Consumption; Cpd = 4.4 pF Typical at 3.3 V Low Input Capacitance; Ci = 1.5 pF Typical Low Noise − Overshoot and Undershoot <10% of VCC Ioff Supports Partial-Power-Down Mode Operation Includes Schmitt-Trigger Inputs Wide Operating VCC Range of 0.8 V to 3.6 V Optimized for 3.3-V Operation D 3.6-V I/O Tolerant to Support Mixed-Mode D D D D D Signal Operation tpd = 4.9 ns Max at 3.3 V Suitable for Point-to-Point Applications Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) ESD Protection Exceeds ±5000-V With Human-Body Model DBV OR DCK PACKAGE (TOP VIEW) NC A GND 1 5 YEP OR YZP PACKAGE (BOTTOM VIEW) GND A DNU VCC 2 3 4 Y Y 3 4 2 VCC 1 5 DNU − Do not use NC − No internal connection description /ordering information The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figures 1 and 2). Static-Power Consumption (µA) 100% 80% 60% 3.3-V Logic† 3.3-V Logic LVC † 40% AUP 0% 2.5 Input 2 Output 1.5 1 0.5 20% 20% 0% Voltage − V 40% 3.5 3 80% 60% Switching Characteristics at 25 MHz† Dynamic-Power Consumption (pF) 100% AUP † Single, dual, and triple gates. 0 −0.5 0 5 10 15 20 25 30 Time − ns 35 40 45 † AUP1G08 data at CL = 15 pF. Figure 1. AUP−The Lowest-Power Family Figure 2. Excellent Signal Integrity This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # #* "# '' +,( '"! $!#- '# #!#&, !&"'# #- && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES578 – JUNE 2004 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP TOP-SIDE MARKING‡ SN74AUP1G14YEPR NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) −40 C to 85 C −40°C 85°C SOT (SOT-23) − DBV SOT (SC-70) − DCK Reel of 3000 _ _ _HF_ SN74AUP1G14YZPR Reel of 3000 SN74AUP1G14DBVR Reel of 250 SN74AUP1G14DBVT Reel of 3000 SN74AUP1G14DCKR Reel of 250 SN74AUP1G14DCKT H14_ HF_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE INPUT A OUTPUT Y H L L H logic diagram (positive logic) 2 4 A 2 POST OFFICE BOX 655303 Y • DALLAS, TEXAS 75265 SCES578 – JUNE 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Output voltage range in the high or low state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and outpu negative-voltaget ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX UNIT VCC VI Supply voltage 0.8 3.6 V Input voltage 0 3.6 V VO Output voltage 0 VCC −20 V VCC = 0.8 V VCC = 1.1 V IOH‡ IOL‡ ∆t/∆v High-level output current Low-level output current Input transition rise or fall rate VCC = 1.4 V VCC = 1.65 VCC = 2.3 V −1.7 VCC = 3 V VCC = 0.8 V −4 VCC = 1.1 V VCC = 1.4 V 1.1 VCC = 1.65 V VCC = 2.3 V 1.9 VCC = 3 V VCC = 0.8 V to 3.6 V µA −1.1 −1.9 mA −3.1 20 µA 1.7 mA 3.1 4 200 ns/V TA Operating free-air temperature −40 85 °C ‡ Defined by the signal-integrity requirements and design-goal priorities. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES578 – JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TA = 25 °C TYP MAX 0.8 V 0.3 0.6 0.3 1.1 V 0.53 0.9 0.53 0.9 1.4 V 0.74 1.11 0.74 1.11 1.65 V 0.91 1.29 0.91 1.29 2.3 V 1.37 1.77 1.37 1.77 3V 1.88 2.29 1.88 2.29 VCC VT+ Positive-going input threshold voltage VT− Negative-going input threshold voltage ∆V VT Hysteresis (VT+ − VT−) 0.1 0.6 0.1 0.6 1.1 V 0.26 0.65 0.26 0.65 1.4 V 0.39 0.75 0.39 0.75 1.65 V 0.47 0.84 0.47 0.84 2.3 V 0.69 1.04 0.69 1.04 1.24 3V 0.88 1.24 0.88 0.8 V 0.07 0.5 0.07 0.5 1.1 V 0.08 0.46 0.08 0.46 1.4 V 0.18 0.56 0.18 0.56 1.65 V 0.27 0.66 0.27 0.66 2.3 V 0.53 0.92 0.53 0.92 0.79 1.31 0.79 1.31 0.8 V to 3.6 V 1.1 V IOH = −1.7 mA IOH = −1.9 mA VOH IOH = −2.3 mA IOH = −3.1 mA IOL = 20 µA IOL = 1.1 mA IOL = 1.7 mA IOL = 1.9 mA VOL IOL = 2.3 mA IOL = 3.1 mA ∆Ioff ICC ∆ICC 4 A input 1.11 1.03 1.32 1.3 2.05 1.97 1.9 1.85 2.72 2.67 V V 2.6 V 2.55 0.8 V to 3.6 V 0.1 0.1 1.1 V 0.3 × VCC 0.3 × VCC 1.4 V 0.31 0.37 1.65 V 0.31 0.35 0.31 0.33 0.44 0.45 0.31 0.33 0.44 0.45 0.1 0.5 µA 0.2 0.6 µA 2.3 V IOL = 2.7 mA IOL = 4 mA II Ioff 1.4 V 3V V VCC − 0.1 0.7 × VCC 1.65 V 2.3 V IOH = −2.7 mA IOH = −4 mA VCC − 0.1 0.75 × VCC UNIT 0.6 0.8 V 3V IOH = −20 µA IOH = −1.1 mA TA = −40 °C TO 85 °C MIN MAX 3V V VI = GND to 3.6 V VI or VO = 0 V to 3.6 V 0 V to 3.6 V VI or VO = 0 V to 3.6 V VI = GND or IO = 0 (VCC to 3.6 V) 0 V to 0.2 V 0.2 0.6 µA 0.8 V to 3.6 V 0.5 0.9 µA 3.3 V 40 50 µA VI = VCC − 0.6 V 0V IO = 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES578 – JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Ci VI = VCC or GND Co VO = GND VCC 0V MIN TYP MAX MIN MAX UNIT 1.5 3.6 V 1.5 0V 2.5 pF pF switching characteristics over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V tpd A Y TA = −40 °C TO 85 °C TA = 25 °C TYP MAX MIN MAX UNIT 16.3 1.2 V ± 0.1 V 4.2 6.9 11.7 0.9 15 1.5 V ± 0.1 V 3.7 5.2 8.4 1.7 10.7 1.8 V ± 0.15 V 3.3 4.4 6.9 1.9 8.5 2.5 V ± 0.2 V 2.8 3.5 4.8 1.8 6.1 3.3 V ± 0.3 V 2.5 3 4 1.7 4.9 ns switching characteristics over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V tpd A Y TA = −40 °C TO 85 °C TA = 25 °C TYP MAX MIN MAX UNIT 18.4 1.2 V ± 0.1 V 4.6 7.9 13.4 1.3 16.7 1.5 V ± 0.1 V 4 6 9.6 2.2 11.8 1.8 V ± 0.15 V 3.6 5 7.9 2.4 9.5 2.5 V ± 0.2 V 3.2 4 5.5 2.3 6.8 3.3 V ± 0.3 V 2.9 3.5 4.6 2.1 5.6 ns switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN 0.8 V tpd A Y POST OFFICE BOX 655303 TA = −40 °C TO 85 °C TA = 25 °C TYP MAX MIN MAX 14 2.5 17.3 20.1 1.2 V ± 0.1 V 5.5 8.7 1.5 V ± 0.1 V 4.7 6.7 10 3 12.5 1.8 V ± 0.15 V 4.2 5.6 8.3 3 10.1 2.5 V ± 0.2 V 3.6 4.5 5.9 2.7 7.4 3.3 V ± 0.3 V 3.3 3.9 5 2.5 6.1 • DALLAS, TEXAS 75265 UNIT ns 5 SCES578 – JUNE 2004 switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figures 3 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) MIN 0.8 V tpd A Y TA = −40 °C TO 85 °C TA = 25 °C VCC TYP MAX MIN MAX UNIT 25.7 1.2 V ± 0.1 V 7.4 11.2 17.1 4.5 20.5 1.5 V ± 0.1 V 6.1 8.5 12.3 4.6 14.7 1.8 V ± 0.15 V 5.4 7.2 10.3 4.1 12 2.5 V ± 0.2 V 4.7 5.7 7.4 3.7 8.8 3.3 V ± 0.3 V 4.2 5 6.2 3.5 7.3 ns operating characteristics, TA = 25°C PARAMETER Cpd 6 TEST CONDITIONS Power dissipation capacitance f = 10 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC 0.8 V TYP UNIT 4 1.2 V ± 0.1 V 4 1.5 V ± 0.1 V 4.1 1.8 V ± 0.15 V 4.1 2.5 V ± 0.2 V 4.3 3.3 V ± 0.3 V 4.4 pF SCES578 – JUNE 2004 PARAMETER MEASUREMENT INFORMATION (Propagation Delays, Setup and Hold Times, and Pulse Width) From Output Under Test CL (see Note A) 1 MΩ LOAD CIRCUIT CL VM VI VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC 5, 10, 15, 30 pF VCC/2 VCC tw VCC Input VCC/2 VCC/2 VI VM Input 0V VM VOLTAGE WAVEFORMS PULSE DURATION 0V tPHL tPLH VOH VM Output VM VOL tPHL VCC Timing Input 0V tPLH tsu VOH VM Output th VCC VM VOL Data Input VCC/2 VCC/2 0V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. B. C. D. E. VCC/2 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. The outputs are measured one at a time, with one transition per measurement. tPLH and tPHL are the same as tpd. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SCES578 – JUNE 2004 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) 2 × VCC 5 kΩ From Output Under Test CL (see Note A) S1 GND 5 kΩ TEST S1 tPLZ/tPZL tPHZ/tPZH 2 × VCC GND LOAD CIRCUIT CL VM VI V∆ VCC = 0.8 V VCC = 1.2 V ± 0.1 V VCC = 1.5 V ± 0.1 V VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.1 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.15 V 5, 10, 15, 30 pF VCC/2 VCC 0.3 V VCC Output Control Output Waveform 1 S1 at 2 × VCC (see Note B) VCC/2 VCC/2 0V tPLZ tPZL VCC VCC/2 VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. 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