SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 D D D D D Load Clocks and Unload Clocks Can Be Asynchronous or Coincident 2048 Words by 9 Bits Low-Power Advanced CMOS Technology Fast Access Times of 15 ns With a 50-pF Load Programmable Almost-Full/Almost-Empty Flag D D D D D D Expansion Logic for Depth Cascading Empty, Full, and Half-Full Flags Fall-Through Time of 20 ns Typical Data Rates up to 50 MHz 3-State Outputs Package Options Include 44-Pin Plastic Leaded Chip Carrier (FN), 64-Pin Thin Quad Flat (PM), and Reduced-Height 64-Pin Quad Flat (PAG) Packages description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7808 is a 2048-word by 9-bit FIFO designed for high speed and fast access times. It processes data at rates up to 50 MHz and access times of 15 ns in a bit-parallel format. Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds the number of words clocked out by 2048. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almost-full/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output is high when the FIFO contains 1024 or more words and is low when it contains 1023 or fewer words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset can be used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (2048 – Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (2047 – Y) words. A low level on the reset (RESET) input resets the internal stack pointers and sets FULL high, AF/AE high, HF low, and EMPTY low. The Q outputs are not reset to any specific logic level. The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are in the high-impedance state when the output-enable (OE) input is low. OE does not affect the output flags. Cascading is easily accomplished in the word-width and word-depth directions. When not using the FIFO in depth expansion, cascade enable (CASEN) must be tied high. The FIFO must be reset upon power up. The SN74ACT7808 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 VCC HF AF/AE GND PEN RESET VCC XO OE GND Q0 FN PACKAGE (TOP VIEW) 6 7 5 4 3 2 1 44 43 42 41 40 39 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 Q1 VCC Q2 Q3 GND Q4 VCC Q5 Q6 GND Q7 Q8 17 29 18 19 20 21 22 23 24 25 26 27 28 GND LDCK DP9 XI FULL EMPTY FL CASEN UNCK VCC D0 D1 D2 GND D3 D4 D5 VCC D6 D7 D8 Q2 Q3 GND GND Q4 VCC VCC Q5 Q6 GND GND Q7 NC Q1 VCC VCC PAG OR PM PACKAGE (TOP VIEW) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC Q0 GND GND OE XO VCC VCC RESET PEN GND GND AF/AE HF VCC VCC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 D6 D7 D8 NC NC D0 D1 D2 GND GND D3 D4 NC D5 VCC VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC – No internal connection 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 NC Q8 VCC VCC UNCK CASEN NC FL EMPTY FULL XI DP9 LDCK GND GND NC SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 logic symbol† 1 RESET LDCK UNCK OE PEN FL CASEN XI DP9 D0 D1 D2 D3 D4 D5 D6 D7 D8 Φ FIFO 2048 × 9 SN74ACT7808 RESET 19 26 42 2 24 25 21 20 7 FULL LDCK HALF FULL UNCK ALMOST FULL/EMPTY EMPTY EN1 22 5 4 23 AF/AE EMPTY PROGRAM ENABLE FIRST LOAD EXPANSION OUT 43 XO CASCADE ENABLE EXPANSION IN DATA PIN 9 0 0 40 8 39 9 37 11 36 12 Data Data 34 1 13 32 15 31 16 29 17 FULL HF 8 8 28 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 functional block diagram OE D0–D8 UNCK Location 1 Location 2 Read Pointer 2048 × 9 RAM LDCK Write Pointer Location 2047 Location 2048 DP9 Q0–Q8 RESET PEN FL Reset Logic EMPTY Expansion and Status-Flag Logic CASEN HF AF/AE XO XI 4 FULL POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 Terminal Functions TERMINAL NAME I/O DESCRIPTION AF/AE O Almost-full/almost-empty flag. Depth-offset values can be programmed for AF/AE or the default value of 256 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer words or (2048 – Y) or more words. AF/AE is high after reset. CASEN† I Cascade enable. When multiple SN74ACT7808 devices are depth cascaded, every device must have CASEN tied low. CASEN must be tied high when a device is not used in depth expansion. D0–D8 I Nine-bit data input port DP9 I DP9 is used as the most significant bit when programming the AF/AE offset values. EMPTY O Empty flag. EMPTY is low when the FIFO memory is empty. A FIFO reset also causes EMPTY to go low. FL† I First load. When multiple SN74ACT7808 devices are depth cascaded, the first device in the chain must have its FL input tied low and all other devices must have their FL inputs tied high. FULL O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high. HF O Half-full flag. HF is high when the FIFO memory contains 1024 or more words. HF is low after reset. LDCK I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high. OE I Output enable. When OE is low, D0–D8 are in the high-impedance state. PEN I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D8 and DP9 is latched as an AF/AE offset value when PEN is low and LDCK is high. Q0–Q8 O Nine-bit data output port RESET I Reset. A low level on RESET resets the FIFO and drives FULL and AF/AE high and HF and EMPTY low. UNCK I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high. XI† I XO† O Expansion input (XI) and expansion output (XO). When multiple SN74ACT7808 devices are depth cascaded, the XO of one device must be connected to the XI of the next device in the chain. chain The XO of the last device in the chain is connected to the XI of the first device in the chain. † See Figures 6 and 7 for application information on FIFO word-width and word-depth expansions, respectively. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 offset values for AF/AE The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the offsets are not programmed, the default values of X = Y = 256 are used. The AF/AE flag is high when the FIFO contains X or fewer words or (2048 – Y) or more words. To program the offset values, program enable (PEN) can be brought low after reset only when LDCK is low. On the following low-to-high transition of LDCK, the binary value on D0–D8 and DP9 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LDCK reprograms Y to the binary value on D0–D8 and DP9 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are disabled while the offsets are programmed. A maximum value of 1023 can be programmed for either X or Y (see Figure 1). To use the default values of X = Y = 256, PEN must be held high. RESET LDCK ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÉÉÉÉ ÎÎÎÎÎÎÎÎÎÎ PEN D0–D8 DP9 EMPTY Don’t Care ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Don’t Care Don’t Care X and Y Y X and Y MSB Y MSB Figure 1. Programming X and Y Separately 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY W2048 W2047 W (2049–x) W (2048–X) W1026 W1025 W (Y+2) Define the AF/AE Flag Using the Default Value or X and Y FULL HF AF/AE EMPTY ÌÌ ÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ Q0–Q8 OE UNCK D0–D8 LDCK CASEN PEN RESET W1 W2 W (X+1) W1 W1024 W (2048–Y) W2048 W2 W (Y+1) Figure 2. Read ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ ÌÌ Don’t Care 1 0 1 0 SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 Figure 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Package thermal impedance, θJA (see Note 1): FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PAG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W PM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions ’ACT7808-20 ’ACT7808-25 ’ACT7808-30 ’ACT7808-40 MIN MAX MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 UNIT VCC Supply voltage VIH High level input voltage High-level VIL IOH Low-level input voltage 0.8 0.8 0.8 0.8 V High-level output current –8 –8 –8 –8 mA IOL Low level output current Low-level 16 16 16 16 8 8 8 8 TA Operating free-air temperature XI 3.85 3.85 3.85 3.85 2 2 2 2 Other inputs Q outputs Flags 0 70 0 70 0 70 0 V V 70 mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC§ Ci Flags Q outputs TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, IOH = –8 mA IOL = 8 mA VCC = 4.5 V, VCC = 5.5 V, IOL = 16 mA VI =VCC or 0 VCC = 5.5 V, VCC = 5.5 V, VO =VCC or 0 VI = VCC – 0.2 V or 0 VCC = 5.5 V, VI = 0, One input at 3.4 V, MIN TYP‡ MAX 2.4 V 0.5 0.5 Other inputs at VCC or GND f = 1 MHz 4 Co UNIT V ±5 µA ±5 µA 400 µA 1 mA pF VO = 0, f = 1 MHz 8 pF ‡ All typical values are at VCC = 5 V, TA = 25°C. § This is the increase in supply current for each input, excluding XI, that is at one of the specified TTL voltage levels rather 0 V or VCC. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 timing requirements over recommended operating conditions (unless otherwise noted) (see Figures 1 through 3) ’ACT7808-20 MIN fclock tw Clock frequency Pulse duration Setup time th Hold time ’ACT7808-25 MIN MAX 50 ’ACT7808-30 MIN 40 MAX ’ACT7808-40 MIN 33.3 MAX 25 LDCK high or low 8 9 11 13 UNCK high or low 8 9 11 13 PEN low 9 9 11 13 RESET low tsu MAX 10 13 16 19 D0–D8, DP9 before LDCK↑ 5 5 5 5 LDCK inactive before RESET high 5 5 5 5 PEN before LDCK↑ 5 5 5 5 D0–D8, DP9 after LDCK↑ 0 0 0 0 LDCK inactive after RESET high 5 5 5 5 PEN low after LDCK↑ 4 4 4 4 PEN high after LDCK low 0 0 0 0 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) fmax LDCK or UNCK TO (OUTPUT) ’ACT7808-20 TYP† MAX MIN 50 40 LDCK↑ tpd UNCK↑ 5 Any Q UNCK↑ Any Q tPLH LDCK↑ EMPTY tPHL RESET low tPLH tpd d tPLH tPHL tPLH tPHL ten tdis ten tdis EMPTY FULL UNCK↑ RESET low LDCK↑ UNCK↑ ’ACT7808-30 MIN MAX 33.3 ’ACT7808-40 MIN MAX 25 5 22 5 25 5 28 15 4.5 18 4.5 20 4.5 22 4 15 4 17 4 19 4 21 2 15 2 17 2 19 2 21 2 16 2 18 2 20 2 22 4 15 4 17 4 19 4 21 4 14 4 16 4 18 4 20 2 18 2 20 2 22 2 24 2 16 2 18 2 20 2 22 2 16 2 18 2 20 2 22 11 FULL AF/AE UNIT MHz 10 UNCK↑ LDCK↑ MAX 20 4.5 tpd‡ ’ACT7808-25 MIN ns ns ns ns ns ns RESET low AF/AE 0 10 0 12 0 14 0 16 LDCK↑ HF 2 19 2 21 2 23 2 25 2 16 2 18 2 20 2 22 2 12 2 14 2 16 2 18 XO 2 11 2 13 2 15 2 17 ns LDCK↑ XO 2 11 2 13 2 15 2 17 ns OE Any Q 1 10 1 12 1 14 1 16 ns OE Any Q 1 9 1 11 1 13 1 15 ns XI high Any Q 3 13 3 15 3 17 3 19 ns XO high Any Q 4 ns UNCK↑ RESET low UNCK↑ HF 4 4 4 ns ns † All typical values are at VCC = 5 V, TA = 25°C. ‡ This parameter is measured with CL = 30 pF (see Figure 4). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, TYP f = 5 MHz UNIT 91 pF PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 ten 500 Ω From Output Under Test Test Point CL = 50 pF (see Note A) tdis tpd 500 Ω S1 tPZH tPZL tPHZ tPLZ tPLH tPHL Open Closed Open Closed Open Open tw LOAD CIRCUIT 3V Input 0V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 0V tsu th 3V Data Input 1.5 V 1.5 V 0V 3V Output Control tPZL 3V 1.5 V 1.5 V 1.5 V 0V tPLH 1.5 V 1.5 V tPZH 1.5 V VOL Output Waveform 2 S1 at Open VOL + 0.3 V 1.5 V VOH VOH – 0.3 V ≈0V NOTE A: CL includes probe and jig capacitance. Figure 3. Load Circuit and Voltage Waveforms • DALLAS, TEXAS 75265 VOL tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES POST OFFICE BOX 655303 tPLZ ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL VOH 10 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output 1.5 V 3V Timing Input Input 1.5 V SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME vs LOAD CAPACITANCE SUPPLY CURRENT vs CLOCK FREQUENCY 160 VCC = 5 V RL = 500 Ω TA = 25°C typ + 6 TA = 75°C CL = 0 pF 140 I CC(f) – Supply Current – mA t pd – Propagation Delay Time – ns typ + 8 typ + 4 typ + 2 typ VCC = 5.5 V VCC = 5 V 120 100 80 VCC = 4.5 V 60 40 20 typ – 2 0 50 100 150 200 250 300 0 0 10 CL – Load Capacitance – pF 20 30 40 50 60 70 80 fclock – Clock Frequency – MHz Figure 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 APPLICATION INFORMATION LDCK FULL SN74ACT7808 LDCK UNCK EMPTY FULL OE D9–D17 D0–D8 CASEN Q0–Q8 UNCK EMPTY OE Q9–Q17 H SN74ACT7808 LDCK UNCK EMPTY FULL OE D0–D8 D0–D8 CASEN Q0–Q8 H Figure 6. Word-Width Expansion: 2048 × 18 Bits 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0–Q8 SN74ACT7808 2048 × 9 STROBED FIRST-IN, FIRST-OUT MEMORY SCAS205E – FEBRUARY 1991 – REVISED NOVEMBER 2001 APPLICATION INFORMATION depth cascading (see Figure 7) The SN74ACT7808 provides expansion logic necessary for cascading an unlimited number of the FIFOs in depth. CASEN must be low on all FIFOs used in depth expansion. FL must be tied low on the first FIFO in the chain; all others must have FL tied high. The expansion-out (XO) output of a FIFO must be tied to the expansion-in (XI) input of the next FIFO in the chain. The XO output of the last FIFO is tied to the XI input of the first FIFO to complete the loop. Data buses are common to each FIFO in the chain. A composite EMPTY and FULL signal must be generated to indicate boundary conditions. RESET OE L FL L H CASEN FL H CASEN FL L CASEN SN74ACT7808 SN74ACT7808 SN74ACT7808 XI XO XI XO XI XO RESET OE RESET OE RESET OE D0–D8 Q0–Q8 LDCK UNCK 9 FULL EMPTY D0–D8 L D0–D8 Q0–Q8 9 LDCK UNCK D0–D8 Q0–Q8 9 9 LDCK UNCK FULL EMPTY FULL EMPTY 9 9 9 9 Q0–Q8 UNCK LDCK FULL EMPTY Figure 7. Depth Cascading to Form a 6K × 9 FIFO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ACT7808-20FN ACTIVE PLCC FN 44 26 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-20PAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-20PM OBSOLETE LQFP PM 64 TBD Call TI SN74ACT7808-25FN ACTIVE PLCC FN 44 26 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-25PAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-25PM OBSOLETE LQFP PM 64 TBD Call TI SN74ACT7808-30FN ACTIVE PLCC FN 44 26 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-30PAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-30PM OBSOLETE LQFP PM 64 TBD Call TI SN74ACT7808-40FN ACTIVE PLCC FN 44 26 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-40PAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN74ACT7808-40PM OBSOLETE LQFP PM 64 TBD Call TI Lead/Ball Finish MSL Peak Temp (3) Call TI Call TI Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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