SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 D D D D D D D D D DV OR NP PACKAGE (TOP VIEW) Reads and Writes Can Be Asynchronous or Coincident Organization: – SN74ACT7200L – 256 × 9 – SN74ACT7201LA – 512 × 9 – SN74ACT7202LA – 1024 × 9 Fast Data Access Times of 15 ns Read and Write Frequencies up to 40 MHz Bit-Width and Word-Depth Expansion Fully Compatible With the IDT7200/ 7201 / 7202 Retransmit Capability Empty, Full, and Half-Full Flags TTL-Compatible Inputs Available in 28-Pin Plastic DIP (NP), Small-Outline (DV), and 32-Pin Plastic J-Leaded Chip-Carrier (RJ) Packages W D8 D3 D2 D1 D0 XI FF Q0 Q1 Q2 Q3 Q8 GND 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC D4 D5 D6 D7 FL /RT RS EF XO/HF Q7 Q6 Q5 Q4 R D3 D8 W NC VCC D4 D5 4 D2 D1 D0 XI FF Q0 Q1 NC Q2 5 3 2 1 32 31 30 29 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 Q3 Q8 Data is loaded into memory by the write-enable (W) input and unloaded by the read-enable (R) input. Read and write cycle times of 25 ns (40 MHz) are possible with data access times of 15 ns. 28 2 RJ PACKAGE (TOP VIEW) description The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are constructed with dual-port SRAM and have internal write and read address counters to provide data throughput on a first-in, first-out (FIFO) basis. Write and read operations are independent and can be asynchronous or coincident. Empty and full status flags prevent underflow and overflow of memory, and depth-expansion logic allows combining the storage cells of two or more devices into one FIFO. Word-width expansion is also possible. 1 D6 D7 NC FL /RT RS EF XO/HF Q7 Q6 GND NC R Q4 Q5 D NC – No internal connection These devices are particularly suited for providing a data channel between two buses operating at asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in dataacquisition systems, temporary storage elements between buses and magnetic or optical memories, and queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for retransmitting previously read data when a device is not used in depth expansion. The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 SN74ACT7200L logic symbol† FIFO 256 × 9 Φ SN74ACT7200L 22 RS 1 W 2,4 CT = 0 (RST) 6 (WR PNTR) 6 C1 G2 XI FL /RT 7 23 (EXPAND) R (CT = 0) G5 8 FF 21 EF (1ST LOAD) 2,4 (REXMIT) 15 2(CT = 255) G6 4(CT = 255) G6 (CT = 256) G6 5 (RD PNTR) (EXPAND) CT > 128 20 XO/HF 5EN3 G4 (CT = WR PNTR – RD PNTR) D0 D1 D2 D3 D4 D5 D6 D7 D8 6 1D 3 5 10 4 11 3 12 27 16 26 17 25 18 24 19 2 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DV and NP packages. 2 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 SN74ACT7201LA logic symbol† FIFO 512 × 9 Φ SN74ACT7201LA 22 RS 1 W 2,4 CT = 0 (RST) 6 (WR PNTR) 6 C1 G2 XI FL /RT 7 23 (EXPAND) R (CT = 0) G5 8 FF 21 EF (1ST LOAD) 2,4 (REXMIT) 15 2(CT = 511) G6 4(CT = 511) G6 (CT = 512) G6 5 (RD PNTR) (EXPAND) CT > 256 20 XO/HF 5EN3 G4 (CT = WR PNTR – RD PNTR) D0 D1 D2 D3 D4 D5 D6 D7 D8 6 1D 3 9 5 10 4 11 3 12 27 16 26 17 25 18 24 19 2 13 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DV and NP packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 SN74ACT7202LA logic symbol† FIFO 1024 × 9 Φ SN74ACT7202LA 22 RS 1 W 2,4 CT = 0 (RST) 6 (WR PNTR) 6 C1 G2 XI FL /RT 7 23 (EXPAND) R (CT = 0) G5 8 FF 21 EF (1ST LOAD) 2,4 (REXMIT) 15 2(CT = 1023) G6 4(CT = 1023) G6 (CT = 1024) G6 5 (RD PNTR) (EXPAND) CT > 512 20 XO/HF 5EN3 G4 (CT = WR PNTR – RD PNTR) D0 D1 D2 D3 D4 D5 D6 D7 D8 6 3 1D 5 10 4 11 3 12 27 16 26 17 25 18 24 19 2 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DV and NP packages. 4 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 functional block diagram 9 D0 – D8 Location 1 Location 2 Write Control W 256 × 9 or 512 × 9 or 1024 × 9 RAM † Write Pointer Read Pointer • 9 • RS FL /RT Q0 – Q8 Reset Logic StatusFlag Logic FF EF Read Control R Expansion Logic XI XO/HF † 256 × 9 for SN74ACT7200L; 512 × 9 for SN74ACT7201LA; 1024 × 9 for SN74ACT7202LA RESET AND RETRANSMIT FUNCTION TABLE (single-device depth; single-or multiple-device width) INTERNAL TO DEVICE INPUTS RS FL/RT XI OUTPUTS READ POINTER WRITE POINTER EF FF XO/HF FUNCTION L X L Location zero Location zero L H H Reset device H L L Location zero Unchanged X X X Retransmit H H L Increment if EF high Increment if FF high X X X Read/write RESET AND FIRST- LOAD FUNCTION TABLE (multiple-device depth; single-or multiple-device width) INTERNAL TO DEVICE INPUTS RS FL/RT L L XI ‡ L H ‡ H X ‡ OUTPUTS FUNCTION READ POINTER WRITE POINTER EF FF Location zero Location zero L H Reset first device Location zero Location zero L H Reset all other devices X Read/write X X X ‡ XI is connected to XO/HF of the previous device in the daisy chain (see Figure 15). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 Terminal Functions TERMINAL NAME I/O D0 – D8 I Data inputs EF O Empty-flag output. EF is low when the read pointer is equal to the write pointer, inhibiting any operation initiated by a read cycle. When the FIFO is empty, a data word can be read automatically at Q0 – Q8 by holding R low when loading the data word with a low-level pulse on W. O Full-flag output. FF is low when the write pointer is one location less than the read pointer, indicating that the device is full and inhibiting any operation initiated by a write cycle. FF goes low when the number of writes after reset exceeds the number of reads by 256 for the SN74ACT7200L, 512 for the SN74ACT7201LA, and 1024 for the SN74ACT7202LA. When the FIFO is full, a data word can be written automatically into memory by holding W low while reading out another data word with a low-level pulse on R. FF DESCRIPTION First-load/retransmit input. FL /RT performs two separate functions. When cascading two or more devices for word-depth expansion, FL /RT is tied to ground on the first device in the daisy chain to indicate that it is the first device loaded and unloaded; it is tied high on all other devices in the depth-expansion chain. FL /RT I GND Q0 – Q8 A device is not used in depth expansion when its expansion (XI) input is tied to ground. In that case, FL /RT acts as a retransmit enable. A retransmit operation is initiated when FL/RT is pulsed low. This sets the internal read pointer to the first location and does not affect the write pointer. R and W must be at a high logic level during the low-level FL /RT retransmit pulse. Retransmit should be used only when less than 256/512/1024 writes are performed between resets; otherwise, an attempt to retransmit can cause the loss of unread data. The retransmit function can affect XO/HF depending on the relative locations of the read and write pointers. Ground O Data outputs. Q0 – Q8 are in the high-impedance state when R is high or the FIFO is empty. R I Read-enable input. A read cycle begins on the falling edge of R if EF is high. This activates Q0 – Q8 and shifts the next data value to this bus. The data outputs return to the high-impedance state as R goes high. As the last stored word is read by the falling edge of R, EF transitions low but Q0 – Q8 remain active until R returns high. When the FIFO is empty, the internal read pointer is unchanged by a pulse on R. RS I Reset input. A reset is performed by taking RS low. This initializes the internal read and write pointers to the first location and sets EF low, FF high, and HF high. Both R and W must be held high for a reset during the window shown in Figure 7. A reset is required after power up before a write operation can take place. VCC Supply voltage W I Write-enable input. A write cycle begins on the falling edge of W if FF is high. The value on D0 – D8 is stored in memory as W returns high. When the FIFO is full, FF is low, inhibiting W from performing any operation on the device. XI I Expansion-in input. XI performs two functions. XI is tied to ground to indicate that the device is not used in depth expansion. When the device is used in depth expansion, XI is connected to the expansion-out (XO) output of the previous device in the depth-expansion chain. XO/HF O Expansion-out/half-full-flag output. XO/HF performs two functions. When the device is not used in depth expansion (i.e., when XI is tied to ground), XO/HF indicates when half the memory locations are filled. After half of the memory is filled, the falling edge on W for the next write operation drives XO/HF low. XO/HF remains low until a rising edge of R reduces the number of words stored to exactly half of the total memory. When the device is used in depth expansion, XO/HF is connected to XI of the next device in the daisy chain. XO/HF drives the daisy chain by sending a pulse to the next device when the previous device reaches the last memory location. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range (any input), VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. recommended operating conditions VCC Supply voltage XI MIN NOM MAX 4.5 5 5.5 2.6 UNIT V VIH High level input voltage High-level VIL IOH Low-level input voltage 0.8 V High-level output current –2 mA IOL TA Low-level output current 8 mA 70 °C Other inputs Operating free-air temperature V 2 0 electrical characteristics over recommended operating free-air temperature range, VCC = 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC = 4.5 V, VCC = 4.5 V, IOH = – 2 mA IOL = 8 mA IOZH IOZL VO = VCC , VO = 0.4 V, R ≥ VIH II VI = 0 to 5.5 V ta = 15 and 25 ns ICC1‡ ICC2‡ ICC3‡ Ci§ Co§ MIN ta = 35 and 50 ns ta = 15 and 25 ns ta = 35 and 50 ns VI = 0, VO = 0, MAX 2.4 –1 50 0.4 V ±10 µA ±10 µA 1 125¶ µA 80 15 R W, R, W RS, RS and FL/RT at VIH 5 TA = 25°C, TA = 25°C, 8 0.5 VI = VCC – 0 0.2 2V 0.5 f = 1 MHz UNIT V R ≥ VIH ta = 35 and 50 ns ta = 15 and 25 ns TYP 8 mA mA mA pF f = 1 MHz 8 pF ‡ ICC1 = supply current; ICC2 = standby current; ICC3 = power-down current. ICC measurements are made with outputs open (only capacitive loading). § This parameter is sampled and not 100% tested. ¶ Tested at fclock = 20 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) FIGURE ′ACT7200L-15 ′ACT7201LA-15 ′ACT7202LA-15 MIN MAX ′ACT7200L-25 ′ACT7201LA-25 ′ACT7202LA-25 MIN MIN MIN 22.2 UNIT MAX Clock frequency, R or W Cycle time, read 1(a) 25 35 45 65 ns tc(W) tc(RS) Cycle time, write 1(b) 25 35 45 65 ns Cycle time, reset 7 25 35 45 65 ns tc(RT) tw(RL) Cycle time, retransmit 4 25 35 45 65 ns Pulse duration, R low 1(a) 15 25 35 50 ns tw(WL) tw(RH) Pulse duration, W low 1(b) 15 25 35 50 ns Pulse duration, R high 1(a) 10 10 10 15 ns tw(WH) tw(RT) Pulse duration, W high 1(b) 10 10 10 15 ns 4 15 25 35 50 ns tw(RS) tw(XIL) Pulse duration, RS low 7 15 25 35 50 ns Pulse duration, XI low 10 15 25 35 50 ns tw(XIH) tsu(D) Pulse duration, XI high 10 10 10 10 10 ns Setup time, data before W↑ 28.5 MAX ′ACT7200L-50 ′ACT7201LA-50 ′ACT7202LA-50 fclock tc(R) Pulse duration, FL/RT low 40 MAX ′ACT7201LA-35† ′ACT7202LA-35† 15 MHz 1(b), 6 11 15 18 30 ns tsu(RT) Setup time, R and W high before FL/RT↑‡ 4 15 25 35 50 ns tsu(RS) Setup time, R and W high before RS↑‡ 7 15 25 35 50 ns tsu(XI-R) Setup time, XI low before R↓ 10 10 10 10 15 ns tsu(XI-W) Setup time, XI low before W↓ 10 10 10 10 15 ns 1(b), 6 0 0 0 5 ns th(D) th(E-R) Hold time, data after W↑ Hold time, R low after EF↑ 5, 11 15 25 35 50 ns th(F-W) Hold time, W low after FF↑ 6, 12 15 25 35 50 ns th(RT) Hold time, R and W high after FL/RT↑ 4 10 10 10 15 ns th(RS) Hold time, R and W high after RS↑ 7 10 10 10 15 ns † Released in RJ package only ‡ These values are characterized but not currently tested. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figure 13) PARAMETER FIGURE ′ACT7200L-15 ′ACT7201LA-15 ′ACT7202LA-15 MIN 1(a), 3, 5 MAX ′ACT7200L-25 ′ACT7201LA-25 ′ACT7202LA-25 MIN MAX ′ACT7201LA-35† ′ACT7202LA-35† MIN MAX ′ACT7200L-50 ′ACT7201LA-50 ′ACT7202LA-50 MIN UNIT MAX ta Access time, R↓ or EF↑ to data out valid tv(RH) Valid time, data out valid after R↑ 1(a) 5 5 5 5 ns ten(R-QX) Enable time, R↓ to Q outputs at low impedance‡ 1(a) 5 5 10 10 ns ten(W-QX) Enable time, W↑ to Q outputs at low impedance‡§ 5 5 5 5 15 ns tdis(R) Disable time, R↑ to Q outputs at high impedance‡ 1(a) 15 18 20 30 ns tw(FH) Pulse duration, FF high in automatic write mode 6 15 25 30 45 ns tw(EH) Pulse duration, EF high in automatic read mode 5 15 25 30 45 ns tpd(W-F) Propagation delay time, W↓ to FF low 2 15 25 30 45 ns tpd(R-F) Propagation delay time, R↑ to FF high 2, 6, 12 15 25 30 45 ns tpd(RS-F) Propagation delay time, RS↓ to FF high 7 25 35 45 65 ns tpd(RS-HF) Propagation delay time, RS↓ to XO/HF high 7 25 35 45 65 ns tpd(W-E) Propagation delay time, W↑ to EF high 3, 5, 11 15 25 30 45 ns tpd(R-E) Propagation delay time, R↓ to EF low 3 15 25 30 45 ns tpd(RS-E) Propagation delay time, RS↓ to EF low 7 25 35 45 65 ns tpd(W-HF) Propagation delay time, W↓ to XO/HF low 8 25 35 45 65 ns tpd(R-HF) Propagation delay time, R↑ to XO/HF high 8 25 35 45 65 ns tpd(R-XOL) Propagation delay time, R↓ to XO/HF low 9 15 25 35 50 ns tpd(W-XOL) Propagation delay time, W↓ to XO/HF low 9 15 25 35 50 ns tpd(R-XOH) Propagation delay time, R↑ to XO/HF high 9 15 25 35 50 ns tpd(W-XOH) Propagation delay time, W↑ to XO/HF high 9 15 25 35 50 ns tpd(RT-FL) Propagation delay time, FL /RT↓ to HF, EF, FF valid 4 25 35 45 65 ns 15 25 35 50 ns † Released in RJ package only ‡ These values are characterized but not currently tested. § Only applies when data is automatically read (see Figure 5) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION tc(R) tw(RL) tw(RH) ta ta R ten(R-QX) Q0 – Q8 tv(RH) ÎÎ ÎÎ ÎÎÎ ÎÎÎ Valid tdis(R) Valid ÎÎÎ ÎÎÎ (a) READ tc(W) tw(WH) tw(WL) W tsu(D) D0 – D8 th(D) Valid Valid (b) WRITE Figure 1. Asynchronous Waveforms Ignored Write Last Write First Read R W tpd(W-F) tpd(R-F) FF Figure 2. Full-Flag Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Additional Reads SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION Ignored Read Last Read First Write Additional Writes W R tpd(R-E) tpd(W-E) EF ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ta D0 – D8 Valid Figure 3. Empty-Flag Waveforms tc(RT) tw(RT) FL / RT ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W, R tsu(RT) th(RT) XO/HF, EF, FF Valid Flag tpd(RT-FL) NOTE A: The EF, FF, and XO/HF status flags are valid after completion of the retransmit cycle. Figure 4. Retransmit Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION W th(E-R) R EF tw(EH) tpd(W-E) ten(W-QX) Q0 – Q8 ta ÎÎÎÎÎÎ ÎÎÎÎÎÎ Valid Figure 5. Automatic-Read Waveforms R th(F-W) W tpd(R-F) FF tw(FH) th(D) D0 – D8 Valid tsu(D) Figure 6. Automatic-Write Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION tc(RS) tw(RS) RS W R ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ tsu(RS) EF th(RS) tpd(RS-E) XO/HF, FF tpd(RS-HF) tpd(RS-F) Figure 7. Master-Reset Waveforms Half Full or Less More Than Half Full Half Full or Less W tpd(R-HF) R tpd(W-HF) XO/HF Figure 8. Half-Full Flag Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION W R Write to Last Physical Location Read From Last Physical Location tpd(W-XOH) tpd(W-XOL) tpd(R-XOH) tpd(R-XOL) XO/HF Figure 9. Expansion-Out Waveforms tw(XIL) tw(XIH) XI tsu(XI-W) W Write to First Physical Location tsu(XI-R) Read From First Physical Location R Figure 10. Expansion-In Waveforms W tpd(W-E) EF ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(E-R) R Figure 11. Minimum Timing for an Empty-Flag Coincident-Read Pulse 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION R tpd(R-F) FF ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ th(F-W) W Figure 12. Minimum Timing for a Full-Flag Coincident-Write Pulse POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V 1100 Ω From Output Under Test 680 Ω 30 pF (see Note A) LOAD CIRCUIT 3V Timing Input 3V High-Level Input 1.5 V 1.5 V 1.5 V GND GND th tsu Data, Enable Input tw 3V 1.5 V 3V 1.5 V Low-Level Input GND 1.5 V GND VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5 V 3V 1.5 V 1.5 V GND tPLZ tPZL Low-Level Output ≈3V 1.5 V VOL 3V GND tPZH 1.5 V ≈0V tpd tpd VOH High-Level Output 1.5 V 1.5 V Input VOH In-Phase Output 1.5 V 1.5 V VOL tPHZ VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE A: Includes probe and jig capacitance Figure 13. Load Circuit and Voltage Waveforms 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 APPLICATION INFORMATION Combining two or more devices to create one FIFO with a greater number of memory bits is accomplished in two different ways. Width expansion increases the number of bits in each word by connecting FIFOs with the same depth in parallel. Depth expansion uses the built-in expansion logic to daisy-chain two or more devices for applications requiring more than 256, 512, or 1024 words of storage. Width expansion and depth expansion can be used together. width expansion Word-width expansion is achieved by connecting the corresponding input control to multiple devices with the same depth. Status flags (EF, FF, and HF) can be monitored from any one device. Figure 14 shows two FIFOs in a width-expansion configuration. Both devices have their expansion-in (XI) inputs tied to ground. This disables the depth-expansion function of the device, allowing the first-load/retransmit (FL/RT) input to function as a retransmit (RT) input and the expansion-out/half-full (XO/HF) output to function as a half-full (HF) flag. depth expansion The SN74ACT7200L / 7201LA/ 7202LA is easily expanded in depth. Figure 15 shows the connections used to depth expand three SN74ACT7200L / 7201LA/ 7202LA devices. Any depth can be attained by adding additional devices to the chain. The SN74ACT7200L / 7201LA/ 7202LA operates in depth expansion under the following conditions: D D D D D The first device in the chain is designated by tying FL to ground. All other devices must have their FL inputs at a high logic level. XO of each device must be tied to XI of the next device. External logic is needed to generate a composite FF and EF. All FF outputs must be ORed together and all EF outputs must be ORed together. RT and HF functions are not available in the depth-expanded configuration. combined depth and width expansion Both expansion techniques can be used together to increase depth and width. This is done by first creating depth-expanded units and then connecting them in a width-expanded configuration (see Figure 16). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 APPLICATION INFORMATION SN74ACT7200L / 7201LA / 7202LA 18 D0 – D18 D0 – D8 Q0 – Q8 D0 – D8 Q0 – Q8 9 9 18 Q0 – Q18 W W R R EF EF RT FL/RT FF FF RS RS XO/HF HF XI SN74ACT7200L / 7201LA / 7202LA D9 – D18 Q9 – Q18 D0 – D8 Q0 – Q8 9 9 W R EF EF FL/RT FF FF XO/HF HF RS XI Figure 14. Word-Width Expansion: 256/512/1024 Words × 18 Bits 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 APPLICATION INFORMATION SN74ACT7200L / 7201LA / 7202LA D0 – D8 9 9 9 D0 – D8 W W R R RS 9 Q0 – Q8 Q0 – Q8 XO/HF RS EF FL/RT FF XI SN74ACT7200L / 7201LA / 7202LA 9 D0 – D8 Q0 – Q8 9 W EF R VCC XO/HF RS EF FL/RT FF XI FF SN74ACT7200L / 7201LA / 7202LA 9 D0 – D8 Q0 – Q8 9 W R XO/HF RS EF FL/RT FF XI Figure 15. Word-Depth Expansion: 768 / 1536 / 3072 Words × 9 Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA 256 × 9, 512 × 9, 1024 × 9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995 APPLICATION INFORMATION Q0 – Q17 Q0 – Q26 18 9 Q0 – Q8 9 27 D0 – D26 Q9 – Q17 ′ACT7200L, ′ACT7201LA, or ′ACT7202LA Depth Expansion Block ′ACT7200L, ′ACT7201LA, or ′ACT7202LA Depth Expansion Block W, R, RS 9 D0 – D8 9 D9 – D17 27 9 Q18 – Q26 ′ACT7200L, ′ACT7201LA, or ′ACT7202LA Depth Expansion Block 9 D18 – D26 18 D9 – D26 Figure 16. Word-Depth Plus Word-Width Expansion 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) SN74ACT7200L15DV SN74ACT7200L15NP Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) Package Type Package Drawing OBSOLETE SOP DV 28 TBD Call TI Call TI OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7200L15RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7200L20DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7200L20NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7200L20RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7200L25DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7200L25NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7200L25RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7200L35DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7200L35NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7200L35RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7200L50DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7200L50NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7200L50RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7201LA15DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7201LA15NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7201LA15RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7201LA20DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7201LA20NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7201LA20RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7201LA25DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7201LA25NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7201LA25RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7201LA35DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7201LA35NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7201LA35RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7201LA50DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7201LA50NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7201LA50RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7202LA15DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7202LA15NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7202LA15RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7202LA25DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7202LA25NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7202LA25RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7202LA35RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7202LA35RJR OBSOLETE PLCC RJ 32 TBD Call TI Call TI SN74ACT7202LA50DV OBSOLETE SOP DV 28 TBD Call TI Call TI SN74ACT7202LA50NP OBSOLETE PDIP NP 28 TBD Call TI Call TI SN74ACT7202LA50RJ OBSOLETE PLCC RJ 32 TBD Call TI Call TI Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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