TI PTH12010LAS

PTH12010W, PTH12010L
www.ti.com
SLTS205E – JUNE 2003 – REVISED APRIL 2006
12-A, 12-V INPUT NON-ISOLATED WIDE-OUTPUT
ADJUST POWER MODULE
FEATURES
•
•
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•
•
•
•
•
•
•
•
•
•
•
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Up to 12-A Output Current
12-V Input Voltage
Wide-Output Voltage Adjust
(1.2 V to 5.5 V)/(0.8 V to 1.8 V)
Efficiencies up to 94%
200 W/in3 Power Density
On/Off Inhibit
Output Voltage Sense
Prebias Startup
Undervoltage Lockout
Auto-Track™ Sequencing
Margin Up/Down Controls
Output Overcurrent Protection (Nonlatching,
Auto-Reset)
Operating Temperature: –40°C to 85°C
Safety Agency Approvals:
UL /cUL 60950, EN60950 VDE
Point of Load Alliance (POLA™) Compatible
APPLICATIONS
•
Complex Multivoltage, Multiprocessor
Systems
Nominal Size = 1.37 in x 0.62 in
(34,8 mm x 15,75 mm)
DESCRIPTION
The PTH12010 series of non-isolated power modules that are small in size but big on performance and
flexibility. The high output current, compact footprint, and industry-leading features offers system designers a
versatile module for powering complex multi-processor digital systems.
The series employs double-sided surface mount construction and provides high-performance step-down power
conversion for up to 12 A of output current. The output voltage of the W-suffix parts can be set to any value over
the range, 1.2 V to 5.5 V. The L-suffix devices have an adjustment range of 0.8 V to 1.8 V. The output voltage is
set using a single external resistor.
This series includes Auto-Track™ sequencing. Auto-Track simplifies the task of supply voltage sequencing in a
power system by enabling modules to track each other, or any external voltage, during power up and power
down.
Other operating features include an on/off inhibit, output voltage adjust (trim), margin up/down controls, and the
ability to start up into an existing output voltage or prebias. For improved load regulation, an output voltage
sense is also provided. A nonlatching overcurrent trip serves as load fault protection.
Target applications include complex multivoltage, multiprocessor systems that incorporate the industry’s
high-speed TMS320™ DSP family, microprocessors, and bus drivers.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Auto-Track, TMS320, POLA are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2006, Texas Instruments Incorporated
PTH12010W, PTH12010L
www.ti.com
SLTS205E – JUNE 2003 – REVISED APRIL 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
STANDARD APPLICATION
Track
Margin Down
Margin Up
1
10 9
8
7
PTH12010x
(Top View)
2
VI
VO
6
3
4
5
VOSense
CI
RSET, 1 %
(Required)
+
Inhibit
L
O
A
D
CO
330 mF
(Optional)
+
560 mF
(Required)
GND
GND
A.RSET = Required to set the output voltage to a value higher than the lowest value (see the electrical characteristics table
for values).
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see
the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Voltages are with respect to GND
MIN
Vtrack
Track Input Voltage
TA
Operating Temperature
Range
Over Vin Range
Twave
Wave solder
temperature
Surface temperature of module body or pins
(5 seconds)
Treflow
Solder reflow
temperature
Surface temperature of module body or pins
Tstg
Storage Temperature
(1)
(2)
2
VI + 0.3
V
85
°C
260
(2)
PTH12010WAS
235
(2)
PTH12010WAZ
260
(2)
–40
Mechanical Vibration
Mil-STD-883D, Method 2007.2
20-2000 Hz
UNIT
(1)
PTH12010WAH
Per Mil-STD-883D, Method 2002.3, 1 msec, 1/2 Sine, mounted
Weight
MAX
–0.3
–40
Mechanical Shock
Flammability
TYP
125
°C
°C
500
G
20
G
5
grams
Meets UL 94V-O
For operation below 0°C the external capacitors must have stable characteristics. Use either a low-ESR tantalum, Os-Con, or ceramic
capacitor.
During soldering of package version, do not elevate peak temperature of the module, pins or internal components above the stated
maximum.
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ELECTRICAL CHARACTERISTICS
TA = 25°C, Vi = 12 V, VO = 3.3 V, Ci = 560 µF, CO = 0 µF, and IO = IO max (Unless otherwise stated)
PTH12010W
CHARACTERISTICS
Io
CONDITIONS
Output current
1.2 V ≤ Vo≤ 5.5 V
VI
Input voltage range
Over Io range
Vo tol
Set-point voltage tolerance
¨Regtemp Temperature variation
MIN
TYP
MAX
60 °C, 200 LFM airflow
0
12 (3)
25 °C, natural convection
0
12 (1)
10.8
UNIT
A
13.2
V
±2 (4)
%Vo
–40 °C < TA < 85 °C
±0.5
%Vo
¨Regline
Line regulation
Over VI range
±10
mV
¨Regload
Load regulation
Over Io range
±12
¨Regtot
Total output variation
Includes set-point, line, load,
–40 °C ≤ TA ≤ 85 °C
¨Vadj
Output voltage adjust range
Over VI range
Efficiency
η
IO = 8 A
1.2
94
RSET = 2.0 kΩ, Vo = 3.3 V
93
RSET = 4.32 kΩ, Vo = 2.5 V
91
RSET = 11.5 kΩ, Vo = 1.8 V
89
RSET = 24.3 kΩ, Vo = 1.5 V
88
RSET = OPEN, Vo = 1.2 V
86
V
%
25
mVpp
Vo ≤ 2.5 V
1
% VO
20
A
Recovery Time
70
µSec
Vo over/undershoot
100
mV
±5
%
–8 (5)
µA
20-MHz bandwidth
Io trip
Overcurrent threshold
Reset, followed by auto-recovery
1 A/µs load step, 50 to 100 % Iomax,
CO = 330 µF
¨Vtr
Vo adj
%Vo
Vo ≤ 2.5 V
VO ripple (peak-to-peak)
Transient response
5.5
RSET = 280 Ω, Vo = 5 V
Vr
ttr
mV
±3 (2)
Margin up/down adjust
IIL
margin
Margin input current (pins 9 /10)
Pin to GND
IIL track
Track input current (pin 8)
Pin to GND
dVtrack/dt
Track slew rate capability
CO≤ CO(max)
UVLO
Undervoltage lockout
–0.13 (6)
1
Vi increasing
Vi decreasing
9.5
8.8
10.4
9
mA
V/ms
V
Inhibit control (pin3)
VIH
Input high voltage
VIL
Input low voltage
IIL inhibit
Input low current
Pin to GND
Iin inh
Input standby current
Inhibit (pin 3) to GND, Track (pin 8) open
fs
Switching frequency
Over Vi and Io ranges
Ci
External input capacitance
(3)
(4)
(5)
(6)
(7)
Referenced to GND
VI– 0.5
Open (4)
–0.2
0.5
300
560 (7)
V
0.24
mA
10
mA
350
400
kHz
µF
See SOA curves or consult factory for appropriate derating.
The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1%, with 100 ppm/°C (or better) temperature stability.
A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 8). If it is left open-circuit the module operates when input
power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do
not place an external pull-up on this pin. For further information, see the related application section.
A 560 µF electrolytic input capacitor is required for proper operation. The capacitor must be rated for a minimum of 800 mA rms of ripple
current.
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ELECTRICAL CHARACTERISTICS (continued)
TA = 25°C, Vi = 12 V, VO = 3.3 V, Ci = 560 µF, CO = 0 µF, and IO = IO max (Unless otherwise stated)
PTH12010W
CHARACTERISTICS
CO
External output capacitance
CONDITIONS
nonceramic
Capacitance value
ceramic
Equivalent series resistance (nonceramic)
MTBF
Reliability
Per Bellcore TR-332
50% stress, Ta = 40 °C, ground benign
MIN
TYP
MAX
0 (8)
330 (9)
6,600 (10)
0
300
UNIT
µF
4 (11)
mΩ
6.4
106 Hr
(8)
(9)
When operating at an output voltage ≥ 3.3 V, 47-µF of external output capacitance is required for proper operation.
An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the
transient response.
(10) This is the calculated maximum. The minimum ESR limitation often results in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 3300 µF. See the application notes for further guidance.
(11) This is the typical ESR for all the electrolytic (nonceramic) ouput capacitance. Use 7 mΩ as the minimum when using max-ESR values
to calculate.
ELECTRICAL CHARACTERISTICS
TA = 25°C, Vi = 12 V, VO = 1.8 V, Ci = 560 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated)
PTH12010L
CHARACTERISTICS
Io
CONDITIONS
MIN
60 °C, 200 LFM airflow
0
25 °C, natural convection
0
TYP
MAX
-
12 (12)
UNIT
Output current
0.8 V ≤ VO≤ 1.8 V
VI
Input voltage range
Over IO range
Vo tol
Set-point voltage tolerance
∆Regtemp
Temperature variation
–40 °C <TA < 85 °C
±0.5
%Vo
∆Regline
Line regulation
Over Vi range
±10
mV
∆Regload
Load regulation
Over IO range
±12
10.8
∆Regtot
Total output variation
Includes set-point, line, load,
– 40°C ≤ TA≤ 85 °C
¨Vadj
Output voltage adjust range
Over Vi range
η
Efficiency
IO= 8 A
0.8
89
RSET = 3.57 kΩ, Vo = 1.5
V
88
RSET = 12.1 kΩ, Vo = 1.2
V
86
RSET = 32.4 kΩ, Vo = 1 V
84
Vo≤ 1 V
Vr
VO ripple (peak-to-peak)
20 MHz bandwidth
Io trip
Overcurrent threshold
Reset, followed by auto-recovery
Transient response
Vo≤ 1 V
mV
%Vo
V
%
82
25
mVpp
1
%VO
20
A
Recovery Time
70
µSec
VO over/undershoot
100
mV
Margin up/down adjust
IIL margin Margin input current (pins 9 /10)
V
%Vo
1 A/µs load step, 50 to 100 % Iomax, CO = 330
µF
∆Vtr
VO adj
13.2
1.8
RSET = 130 Ω, Vo = 1.8 V
A
±2 (13)
±3 (2)
RSET = OPEN, Vo = 0.8 V
ttr
12 (1)
±5%
Pin to GND
–8 (14)
µA
(12) See SOA curves or consult factory for appropriate derating.
(13) The set-point voltage tolerance is affected by the tolerance and stability of RSET. The stated limit is unconditionally met if RSET has a
tolerance of 1%, with 100 ppm/°C (or better) temperature stability.
(14) A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
4
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ELECTRICAL CHARACTERISTICS (continued)
TA = 25°C, Vi = 12 V, VO = 1.8 V, Ci = 560 µF, CO = 0 µF, and IO = IOmax (Unless otherwise stated)
PTH12010L
CHARACTERISTICS
CONDITIONS
IIL track
Track input current (pin 8)
Pin to GND
dVtrack/dt
Track slew rate capability
CO≤ CO(max)
UVLO
Undervoltage lockout
MIN
TYP
MAX
–0.13 (15)
1
Vi increasing
9.5
Vi decreasing
8.8
10.4
9
UNIT
mA
V/ms
V
Inhibit control (pin3)
VIH
Input high voltage
VIL
Input low voltage
Referenced to GND
IIL
Input low current
Pin to GND
Ii inh
Input standby current
Inhibit (pin 3) to GND, Track (pin 8) open
fs
Switching frequency
Over Vi and Io ranges
CI
External input capacitance
CO
MTBF
External output capacitance
Reliability
VI– 0.5
Open(4)
–0.2
0.5
200
0.24
mA
10
mA
250
300
330 (17)
6,600 (18)
560 (16)
nonceramic
0
ceramic
0
Equivalent series resistance (nonceramic)
4 (19)
Capacitance value
Per Bellcore TR-332
50% stress, Ta = 40°C, ground benign
6.4
V
kHz
µF
300
µF
mΩ
106 Hrs
(15) This control pin has an internal pull-up to the input voltage VI (7.5 V for pin 8). If it is left open-circuit the module operates when input
power is applied. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do
not place an external pull-up on this pin. For further information, see the related application section.
(16) A 560 µF electrolytic input capacitor is required for proper operation. The capacitor must be rated for a minimum of 800 mA rms of ripple
current.
(17) An external output capacitor is not required for basic operation. Adding 330 µF of distributed capacitance at the load improves the
transient response.
(18) This is the calculated maximum. The minimum ESR limitation oftens result in a lower value. When controlling the Track pin using a
voltage supervisor, CO(max) is reduced to 3300 µF. See the application notes for further guidance.
(19) This is the typical ESR for all the electrolytic (nonceramic) ouput capacitance. Use 7 mΩ as the minimum when using max-ESR values
to calculate.
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DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
GND
1,7
DESCRIPTION
This is the common ground connection for the VI and VO power connections. It is also the 0 Vdc
reference for the control inputs.
2
The positive input voltage power node to the module, which is referenced to common GND.
3
The Inhibit pin is an open-collector/drain negative logic input that is referenced to GND. Applying a
low-level ground signal to this input disables the module’s output and turns off the output voltage.
When the Inhibit control is active, the input current drawn by the regulator is significantly reduced. If
the inhibit feature is not used, the control pin should be left open-circuit. The module then produces an
output whenever a valid input source is applied.
VO Adjust
4
A 1% resistor must be directly connected between this pin and GND (pin 1) to set the output voltage of
the module higher than its lowest value. The temperature stability of the resistor should be 100 ppm/°C
(or better). The set-point range is 1.2 V to 5.5 V for W-suffix devices, and 0.8 V to 1.8 V for L-suffix
devices. The resistor value required for a given output voltage may be calculated using a formula. If
left open circuit, the output voltage defaults to its lowest value. For further information on output
voltage adjustment, see the related application section. The specification table gives the preferred
resistor values for a number of standard output voltages.
VO Sense
5
The sense input allows the regulation circuit to compensate for voltage drop between the module and
the load. For optimal voltage accuracy, VO Sense should be connected to VO. It can also be left
disconnected.
VO
6
The regulated positive power output with respect to the GND node.
Track
8
This is an analog control input that enables the output voltage to follow an external voltage. This pin
becomes active typically 20 ms after the input voltage has been applied, and allows direct control of
the output voltage from 0 V up to the nominal set-point voltage. Within this range the output will follow
the voltage at the Track pin on a volt-for-volt basis. When the control voltage is raised above this
range, the module regulates at its set-point voltage. The feature allows the output voltage to rise
simultaneously with other modules powered from the same input bus. If unused, this input should be
connected to Vi. Note: Due to the undervoltage lockout feature, the output of the module cannot follow
its own input voltage during power up.
Margin Down (1)
9
When this input is asserted to GND, the output voltage is decreased by 5% from the nominal. The
input requires an open-collector (open-drain) interface. It is not TTL compatible. A lower percent
change can be accomodated with a series resistor. For further information, see the related application
section.
Margin Up (1)
10
When this input is asserted to GND, the output voltage is increased by 5%. The input requires an
open-collector (open-drain) interface. It is not TTL compatible. The percent change can be reduced
with a series resistor. For further information, see the related application section.
VI
Inhibit (20)
(20) Denotes negative logic:
Open = Normal operation
Ground = Function active
1
10
9
8
7
PTHXX010
(Top View)
2
6
3
6
4
5
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PTH12010W TYPICAL CHARACTERISTICS (VI = 12 V) (21) (22)
EFFICIENCY
vs
LOAD CURRENT
VO = 3.3 V
80
70
Output Ripple − mV
VO = 2.5 V
VO = 2 V
VO = 1.2 V
VOUT = 5 V
VOUT = 2 V
60
VOUT = 3.3 V
40
20
60
0
2
4
6
8
10
0
12
VOUT = 5 V
VOUT = 3.3 V
3
VOUT = 1.8 V
2
VOUT = 1.5 V
1
0
2
4
6
8
10
0
12
0
2
4
6
8
10
Figure 1.
Figure 2.
Figure 3.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TA− Ambient Temperature −5 C
80
400 LFM
70
200 LFM
100 LFM
60
Nat Conv
50
40
30
VO = 5 V
2
4
6
8
10
12
90
Nat Conv
80
100 LFM
70
200 LFM
400 LFM
60
50
40
30
20 0
VO = 3.3 V
2
4
6
8
10
12
IL − Load Current − A
90
0
VOUT = 2 V
IL − Load Current − A
90
20
VOUT = 2.5 V
4
VOUT = 1.2 V
VOUT = 1.5 V
VOUT = 1.2 V
IO − Output Current − A
TA− Ambient Temperature −5 C
VOUT = 2.5 V
VOUT = 1.8 V
TA− Ambient Temperature −5 C
Efficiency − %
VO = 1.8 V
VO = 1.5 V
50
5
100
VO = 5 V
90
80
POWER DISSIPATION
vs
LOAD CURRENT
PD − Power Dissipation − W
100
OUTPUT RIPPLE
vs
LOAD CURRENT
400 LFM
Nat Conv
80
100 LFM
200 LFM
70
60
50
40
30
VO = ≤1.8 V
12
20
0
2
4
6
8
IO − Output Current − A
IO − Output Current − A
IO − Output Current − A
Figure 4.
Figure 5.
Figure 6.
10
12
(21) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 1, Figure 2, and Figure 3.
(22) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to modules soldered directly to a 4 inch × 4 inch double-sided PCB with 2 oz. copper. For
surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 4, Figure 5, and Figure 6.
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PTH12010L TYPICAL CHARACTERISTICS (VI = 12 V) (25) (26)
EFFICIENCY
vs
LOAD CURRENT
50
VO = 1.5 V
VO = 1.8 V
VO = 1.2 V
Output Ripple − mV
80
VO = 1 V
VO = 0.8 V
70
5
40
90
Efficiency − %
POWER DISSIPATION
vs
LOAD CURRENT
VOUT = 1 V
VOUT = 0.8 V
VOUT = 1.2 V
30
20
10
60
PD − Power Dissipation − W
100
OUTPUT RIPPLE
vs
LOAD CURRENT
VOUT = 1.8 V
VOUT = 1.5 V
4
VOUT = 1.8 V
VOUT = 1.5 V
3
VOUT = 1.2 V
2
1
VOUT = 1 V
VOUT = 0.8 V
50
0
2
4
6
8
10
0
12
0
2
IO − Output Current − A
4
6
8
10
12
0
2
4
6
8
10
12
IL − Load Current − A
IL − Load Current − A
Figure 7.
0
Figure 8.
Figure 9.
TEMPERATURE DERATING
vs
OUTPUT CURRENT
TA− Ambient Temperature −5 C
90
80
Nat Conv
100 LFM
70
60
50
40
30
20
VO = ≤1.8 V
0
2
4
6
8
10
12
IO − Output Current − A
Figure 10.
(25) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the
converter. Applies to Figure 7, Figure 8, and Figure 9.
(26) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum
operating temperatures. Derating limits apply to modules soldered directly to a 4 inch x 4 inch double-sided PCB with 2 oz. copper. For
surface mount packages (AS and AZ suffix), multiple vias (plated through holes) are required to add thermal paths around the power
pins. Please refer to the mechanical specification for more information. Applies to Figure 10.
8
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APPLICATION INFORMATION
CAPACITOR RECOMMENDATIONS FOR THE PTH12010 SERIES OF POWER MODULES
INPUT CAPACITOR
The recommended input capacitance is determined by the 560 µF minimum capacitance and 800 mArms
minimum ripple current rating. A 10 µF X5R/X7R ceramic capacitor may also be added to reduce the reflected
input ripple current. The ceramic capacitor should be located between the input electrolytic and the module.
Ripple current, less than 100 mΩ equivalent series resistance (ESR) and temperature are major considerations
when selecting input capacitors. Unlike polymer-tantalum capacitors, regular tantalum capacitors have a
recommended minimum voltage rating of 2 × (max dc voltage + ac ripple). This is standard practice to ensure
reliability. No tantalum capacitors were found with sufficient voltage rating to meet this requirement. At
temperatures below 0°C, the ESR of aluminum electrolytic capacitors increases. For these applications, Os-Con,
polymer-tantalum, and polymer-aluminum types should be considered.
OUTPUT CAPACITORS (OPTIONAL)
For applications with load transients (sudden changes in load current), regulator response benefits from external
output capacitance. The value of 330 µF is used to define the transient response specification (see data sheet).
For most applications, a high quality computer-grade aluminum electrolytic capacitor is adequate. These
capacitors provide decoupling over the frequency range, 2 kHz to 150 kHz, and are suitable for ambient
temperatures above 0°C. Below 0°C, tantalum, ceramic or Os-Con type capacitors are recommended. When
using one or more nonceramic capacitors, the calculated equivalent ESR should be no lower than 4 mΩ (7 mΩ
using the manufacturer’s maximum ESR for a single capacitor). A list of preferred low-ESR type capacitors are
identified in Table 1.
In addition to electrolytic capacitance, adding a 10 µF X5R/X7R ceramic capacitor to the output reduces the
output ripple voltage and improve the regulator’s transient response. The measurement of both the output ripple
and transient response is also best achieved across a 10 µF ceramic capacitor.
CERAMIC CAPACITORS
Above 150 kHz the performance of aluminum electrolytic capacitors is less effective. Multilayer ceramic
capacitors have very low ESR and a resonant frequency higher than the bandwidth of the regulator. They can
be used to reduce the reflected ripple current at the input as well as improve the transient response of the
output. When used on the output, their combined ESR is not critical as long as the total value of ceramic
capacitance does not exceed 300 µF. Also, to prevent the formation of local resonances, do not place more than
five identical ceramic capacitors in parallel with values of 10 µF or greater.
TANTALUM CAPACITORS
Tantalum type capacitors are most suited for use on the output bus, and are recommended for applications
where the ambient operating temperature can be less than 0°C. The AVX TPS, Sprague 593D/594/595 and
Kemet T495/T510 capacitor series are suggested over other tantalum types due to their higher rated surge,
power dissipation, and ripple current capability. As a caution, many general purpose tantalum capacitors have
considerably higher ESR, reduced power dissipation and lower ripple current capability. These capacitors are
also less reliable as they have lower power dissipation and surge current ratings. Tantalum capacitors that do
not have a stated ESR or surge current rating are not recommended for power applications.
When specifying Os-con and polymer tantalum capacitors for the output, the minimum ESR limit are
encountered well before the maximum capacitance value is reached.
CAPACITOR TABLE
Table 1 identifies the characteristics of capacitors from a number of vendors with acceptable ESR and ripple
current (rms) ratings. The recommended number of capacitors required at both the input and output buses is
identified for each capacitor type.
This is not an extensive capacitor list. Capacitors from other vendors are available with comparable
specifications. Those listed are for guidance. The RMS ripple current rating and ESR (at 100 kHz) are critical
parameters necessary to insure both optimum regulator performance and long capacitor life.
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APPLICATION INFORMATION (continued)
DESIGNING FOR VERY FAST LOAD TRANSIENTS
The transient response of the DC/DC converter has been characterized using a load transient with a di/dt of
1 A/µs. The typical voltage deviation for this load transient is given in the data sheet specification table using the
optional value of output capacitance. As the di/dt of a transient is increased, the response of a converter’s
regulation circuit ultimately depends on its output capacitor decoupling network. This is an inherent limitation
with any dc/dc converter once the speed of the transient exceeds its bandwidth capability. If the target
application specifies a higher di/dt or lower voltage deviation, the requirement can only be met with additional
output capacitor decoupling. In these cases special attention must be paid to the type, value and ESR of the
capacitors selected.
If the transient performance requirements exceed that specified in the data sheet, or the total amount of load
capacitance is above 3000 µF, the selection of output capacitors becomes more important.
Table 1. Input/Output Capacitors (29)
CAPACITOR CHARACTERISTICS
CAPACITOR VENDOR,
TYPE/SERIES, (STYLE)
QUANTITY
WORKING
VOLTAGE
VALUE
(µF)
MAX. ESR
AT 100 kHz
MAX RIPPLE
CURRENT AT
85°C (lrms)
PHYSICAL
SIZE (mm)
INPUT
BUS
OPTIONAL
OUTPUT
BUS
VENDOR PART
NUMBER
Panasonic, Aluminum
(FC)
25 V
560
0.065 Ω
1205 mA
12,5 x 15
1
1
EEUFC1E561S
FC, Radial
25 V
1000
0.060 Ω
1100 mA
12,5 x 13,5
1
1
EEVFK1E102Q
FK, (SMD)
35 V
680
0.060 Ω
1100 mA
12,5 x 13,5
1
1
EEVFK1V681Q
PS, Poly-Aluminum
(Radial)
16 V
330
0.014 Ω
5050 mA
10 x 12,5
2
≤2
16PS330MJ12
United Chemi-Con
LXZ, Aluminium (Radial)
16 V
680
0.068 Ω
1050 mA
10 x 16
1
1
LXZ16VB681M10X16LL
PXA, Poly-Aluminum
(SMD)
16 V
330
0.014 Ω
5050 mA
10 x 12,2
2
≤2
PXA16VC331MJ12TP
Nichicon, Aluminum
(PM)
25 V
560
0.060 Ω
1060 mA
12,5 x 15
1
1
UPM1E561MHH6
HD, (Radial)
16 V
680
0.038 Ω
1430 mA
10 x 16
1
1
UHD1C681MPR
PM, (Radial)
35 V
560
0.048 Ω
1360 mA
16 x 15
1
1
UPM1V561MHH6
6.3 V
180
0.005 Ω
4000 mA
7,3 x 4,3 x 4,2
N/R (30)
≤1 (31)
TPE Poscap (SMD)
10 V
330
0.025 Ω
3000 mA
7,3 x 5,7
N/R (2)
≤4
10TPE330M
SEQP, Os-Con (Radial)
16 V
330
0.016 Ω
>4720 mA
10 x 13
2
≤2
16SEQP330M
SVP, Os-Con (SMD)
16 V
330
0.016 Ω
4700 mA
11 x 12
2
≤3
16SVP330M
10 V
470
0.045 Ω
>1723 mA
N/R (2)
≤5 (3)
TPSE477M010R0045
(VO ≤ 5.1 V)
10 V
330
0.045 Ω
>1723 mA
N/R (2)
≤5 (3)
TPSE377M010R0045
(VO ≤ 5.1 V)
Panasonic,
Poly-Aluminum
S/SE,
(SMD)Poly-Aluminum
EEFSEOJ181R
(VO ≤ 5.1 V)
Sanyo
AVX, Tantalum Series III
TPS (SMD)
7,3 x 5,7 x 4,1
Kemet
(29) Capacitor Supplier Verification
Please verify availability of capacitors identified in this table. Capacitor suppliers may recommend alternative part numbers because of
limited availability or obsolete products. In some instances, the capacitor product life cycle may be in decline and have short-term
consideration for obsolescence.
RoHS, Lead-free and Material Details
Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process
requirements. Component designators or part number deviations can occur when material composition or soldering requirements are
updated.
(30) N/R –Not recommended. The capacitor voltage rating does not meet the minimum derated operating limits.
(31) The voltage rating of this capacitor only allows it to be used for output voltages that are equal to or less than 5.1 V.
10
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APPLICATION INFORMATION (continued)
Table 1. Input/Output Capacitors (continued)
CAPACITOR CHARACTERISTICS
CAPACITOR VENDOR,
TYPE/SERIES, (STYLE)
QUANTITY
WORKING
VOLTAGE
VALUE
(µF)
MAX. ESR
AT 100 kHz
MAX RIPPLE
CURRENT AT
85°C (lrms)
PHYSICAL
SIZE (mm)
T520, Poly-Tantalum
(SMD)
10 V
330
0.040 Ω
1800 mA
T530, Poly-Tant/Organic
10 V
330
0.010 Ω
>3800 mA
6.3 V
470
0.005 Ω
4200 mA
595D, Tantalum (SMD)
10 V
470
0.100 Ω
1440 mA
94SA, Os-con (Radial)
16 V
1000
0.015Ω
9750 mA
16 x 25
1
≤2
94SA108X0016HBP
94SVP, Os-CON(SMD)
16V
330
0.017Ω
4580 mA
10 x 12,7
2 (32)
≤2
94SVP337X0016F12
Kemet, Ceramic X5R
(SMD)
16 V
10
0.002 Ω
-
1210 Case
1 (33)
≤5
C1210C106M4PAC
6.3 V
47
0.002 Ω
3225 mm
N/R (2)
≤5
C1210C476K9PAC
6.3 V
100
0.002 Ω
1210 Case
N/R (2)
≤3
GRM32ER60J107M
3225 mm
4,3 x 7,3 x 4,0
INPUT
BUS
OPTIONAL
OUTPUT
BUS
VENDOR PART
NUMBER
N/R (2)
≤5
T520X337M010AS
N/R (2)
≤2
T530X337M010ASE010
N/R (2)
≤1 (3)
T530X477M006AS E005
(VO ≤ 5.1 V)
N/R (2)
≤5 (3)
595D477X0010R2T
(VO ≤ 5.1 V)
Vishay-Sprague
Murata, Ceramic X5R
(SMD)
TDK, Ceramic X5R
(SMD)
(32)
(33)
(34)
(35)
-
7,2 x 6,0 x 4,1
16 V
47
1 (5)
≤5
GRM32ER61CJ476K
16 V
22
1 (5)
≤5
GRM32ER61C226K
16 V
10
1 (5)
≤5
GRM32DR61C106K
6.3 V
100
1210 Case
N/R (2)
≤3
C3225X5R0J107MT
6.3 V
47
3225 mm
N/R (34)
≤5
C3225X5R0J476MT
16 V
22
1 (35)
≤5
C3225X5R1C226MT
16 V
10
1 (7)
≤5
C3225X5R1C106MT
0.002 Ω
-
A total capacitance of 540 µF is acceptable based on the combined ripple current rating.
A ceramic capacitor may be used to complement electrolytic types at the input to further reduce high-frequency ripple current.
N/R –Not recommended. The capacitor voltage rating does not meet the minimum derated operating limits.
A ceramic capacitor may be used to complement electrolytic types at the input to further reduce high-frequency ripple current.
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ADJUSTING THE OUTPUT VOLTAGE OF THE PTH12010X SERIES OF WIDE-OUTPUT ADJUST
POWER MODULES
The VO Adjust control (pin 4) sets the output voltage of the PTH12010 product. The adjustment range is from 1.2
V to 5.5 V for the W-suffix modules, and 0.8 V to 1.8 V for L-suffix modules. The adjustment method requires the
addition of a single external resistor, RSET, that must be connected directly between the VO Adjust and GND
pins.Table 2 gives the preferred value of the external resistor for a number of standard voltages, along with the
actual output voltage that this resistance value provides. Figure 11 shows the placement of the required resistor.
Table 2. Preferred Values of Rset for Standard Output Voltages
PTH12010W
VO (Required)
PTH12010L
RSET
VO (Actual)
RSET
VO(Actual)
5V
280 Ω
5.009 V
N/A
N/A
3.3 V
2.0 kΩ
3.294 V
N/A
N/A
2.5 V
4.32 kΩ
2.503 V
N/A
N/A
2V
8.06 kΩ
2.010 V
N/A
N/A
1.8 V
11.5 kΩ
1.081 V
130 Ω
1.800 V
1.5 V
24.3 kΩ
1.506 V
3.57 kΩ
1.499 V
1.2 V
Open
1.200 V
12.1 kΩ
1.201 V
1.1 V
N/A
N/A
18.7 kΩ
1.101 V
1.0 V
N/A
N/A
32.4 kΩ
0.999 V
0.9 V
N/A
N/A
71.5 kΩ
0.901 V
0.8 V
N/A
N/A
Open
0.800 V
For other output voltages, the value of the required resistor can either be calculated, or simply selected from the
range of values given in Table 4. The following formula may be used for calculating the adjust resistor value.
Select the appropriate value for the parameters, RS and Vmin, from Table 3.
RSET = 10 kW x
0.8 V
- RS kW
VO - Vmin
(1)
Table 3. Adjust Formula Parameters
PT. NO.
PTH12010W
PTH12010L
Vmin
1.2 V
0.8 V
Vmax
5.5 V
1.8 V
RS
1.82 kΩ
7.87 kΩ
VOSense
VI
2
5
3
CI
560 mF
(Required)
1
7
VO
6
PTH12010x
4
RSET
1%
0.1 W
+
8
10 9
+
GND
CO
330 mF
(Optional)
GND
Figure 11. Vo Adjust Resistor Placement
NOTES
1. A 0.05 W rated resistor may be used. The tolerance should be 1%, with temperature stability of 100 ppm/°C
(or better). Place the resistor as close to the regulator as possible. Connect the resistor directly between
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pins 4 and 7 using dedicated PCB traces.
2. Never connect capacitors from VO Adjust to either GND or VO. Any capacitance added to the VO Adjust pin
affects the stability of the regulator.
Table 4. Output Voltage Set-Point Resistor Values
PTH12010W
PTH12010L
VO
RSET
VO
RSET
VO
RSET
1.2
Open
2.7
3.51 kΩ
0.8
Open
1.225
318 kΩ
2.75
3.34 kΩ
0.825
312 kΩ
1.25
158 kΩ
2.8
3.18 kΩ
0.85
152 kΩ
1.275
105 kΩ
2.85
3.03 kΩ
0.875
98.8 kΩ
1.3
78.2 kΩ
2.9
2.89 kΩ
0.9
72.1 kΩ
1.325
62.2 kΩ
2.95
2.75 kΩ
0.925
56.1 kΩ
1.35
51.5 kΩ
3
2.62 kΩ
0.95
45.5 kΩ
1.375
43.9 kΩ
3.05
2.5 kΩ
0.975
37.8 kΩ
1.4
38.2 kΩ
3.1
2.39 kΩ
1
32.1 kΩ
1.425
33.7 kΩ
3.15
2.28 kΩ
1.025
27.7 kΩ
1.45
30.2 kΩ
3.2
2.18 kΩ
1.05
24.1 kΩ
1.475
27.3 kΩ
3.25
2.08 kΩ
1.075
21.2 kΩ
1.5
24.8 kΩ
3.3
1.99 kΩ
1.1
18.8 kΩ
1.55
21 kΩ
3.35
1.90 kΩ
1.125
16.7 kΩ
1.6
18.2 kΩ
3.4
1.82 kΩ
1.15
15 kΩ
1.65
16 kΩ
3.5
1.66 kΩ
1.175
13.5 kΩ
12.1 kΩ
1.7
14.2 kΩ
3.6
1.51 kΩ
1.2
1.75
12.7 kΩ
3.7
1.38 kΩ
1.225
11 kΩ
1.8
11.5 kΩ
3.8
1.26 kΩ
1.25
9.91 kΩ
1.85
10.5 kΩ
3.9
1.14 kΩ
1.275
8.97 kΩ
1.9
9.61 kΩ
4
1.04 kΩ
1.3
8.13 kΩ
1.95
8.85 kΩ
4.1
939 Ω
1.325
7.37 kΩ
2
8.18 kΩ
4.2
847 Ω
1.35
6.68 kΩ
2.05
7.59 kΩ
4.3
761 Ω
1.375
6.04 kΩ
2.1
7.07 kΩ
4.4
680 Ω
1.4
5.46 kΩ
2.15
6.6 kΩ
4.5
604 Ω
1.425
4.93 kΩ
2.2
6.18 kΩ
4.6
533 Ω
1.45
4.44 kΩ
2.25
5.80 kΩ
4.7
466 Ω
1.475
3.98 kΩ
2.3
5.45 kΩ
4.8
402 Ω
1.5
3.56 kΩ
2.35
5.14 kΩ
4.9
342 Ω
1.55
2.8 kΩ
2.4
4.85 kΩ
5
285 Ω
1.6
2.13 kΩ
2.45
4.58 kΩ
5.1
231 Ω
1.65
1.54 kΩ
2.5
4.33 kΩ
5.2
180 Ω
1.7
1.02 kΩ
2.55
4.11 kΩ
5.3
131 Ω
1.75
551 Ω
2.6
3.89 kΩ
5.4
85 Ω
1.8
130 Ω
2.65
3.70kΩ
5.5
41 Ω
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FEATURES OF THE PTH FAMILY OF NON-ISOLATED WIDE OUTPUT ADJUST POWER
MODULES
POLA™ COMPATIBILITY
The PTH/PTV family of nonisolated, wide-output adjustable power modules are optimized for applications that
require a flexible, high performance module that is small in size. Each of these products are POLA™ compatible.
POLA compatible products are produced by a number of manufacturers, and offer customers advanced,
nonisolated modules with the same footprint and form factor. POLA parts are also ensured to be interoperable,
thereby providing customers with second-source availability.
From the basic, Just Plug it In functionality of the 6-A modules, to the 30-A rated feature-rich PTHxx030, these
products were designed to be very flexible, yet simple to use. The features vary with each product. Table 5
provides a quick reference to the features by product series and input bus voltage.
Table 5. Operating Features by Series and Input Bus Voltage
Series
PTHxx050
PTHxx060
PTHxx010
PTVxx010
PTHxx020
PTVxx020
PTHxx030
Input Bus
IO
Adjust
(Trim)
On/Off
Inhibit
OverCurrent
Prebias
Startup
AutoTrack™
Margin
Up/Down
Output
Sense
Thermal
Shutdown
3.3 V
6A
•
•
•
•
•
5V
6A
•
•
•
•
•
12 V
6A
•
•
•
•
•
3.3 V / 5 V 10 A
•
•
•
•
•
•
•
12 V
•
•
•
•
•
•
•
3.3 V / 5 V 15 A
•
•
•
•
•
•
•
12 V
12 A
•
•
•
•
•
•
•
5V
8A
•
•
•
•
•
12 V
8A
•
•
•
•
•
3.3 V / 5 V 22 A
•
•
•
•
•
•
•
•
12 V
18 A
•
•
•
•
•
•
•
•
5V
18 A
•
•
•
•
•
•
•
12 V
16 A
•
•
•
•
•
•
•
3.3 V/ 5 V
30 A
•
•
•
•
•
•
•
•
12 V
26 A
•
•
•
•
•
•
•
•
8A
•
•
For simple point-of-use applications, the PTH12050 (6 A) provides operating features such as an on/off inhibit,
output voltage trim, prebias start-up and overcurrent protection. The PTH12060 (10 A), and PTH12010 (12 A)
include an output voltage sense, and margin up/down controls. Then the higher output current, PTH12020 (18
A) and PTH12030 (26 A) products incorporate overtemperature shutdown protection.
The PTV12010 and PTV12020 are similar parts offered in a vertical, single in-line pin (SIP) profile, at slightly
lower current ratings.
All of the products referenced in Table 5 include Auto-Track™. This feature was specifically designed to simplify
the task of sequencing the supply voltages in a power system. This and other features are described in the
following sections.
SOFT-START POWER UP
The Auto-Track feature allows the power-up of multiple PTH modules to be directly controlled from the Track
pin. However in a stand-alone configuration, or when the Auto-Track feature is not being used, the Track pin
should be directly connected to the input voltage, VI, see Figure 12.
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8
10 9
Up Dn Track
2
VI
PTH12020W
Inhibit
3
CI
1000 mF
VO
3.3 V
6
GND
Adjust
7
1
4
RSET
2 kW
0.1 W, 1 %
+
12 V
5
Sense
CO
330 mF
GND
+
GND
Figure 12. Power-Up Application Circuit
When the Track pin is connected to the input voltage the Auto-Track function is permanently disengaged. This
allows the module to power up entirely under the control of its internal soft-start circuitry. When power up is
under soft-start control, the output voltage rises to the set-point at a quicker and more linear rate.
VI (5 V/div)
VO (1 V/div)
II (5 V/div)
t − Time − 5 ms/div
Figure 13. Power-Up Waveforms
From the moment a valid input voltage is applied, the soft-start control introduces a short time delay (typically
8 ms-15 ms) before allowing the output voltage to rise. The output then progressively rises to the module’s
setpoint voltage. Figure 13 shows the soft-start power-up characteristic of the 18-A output product
(PTH12020W), operating from a 12-V input bus and configured for a 3.3-V output. The waveforms were
measured with a 5-A resistive load and the Auto-Track feature disabled. The initial rise in input current when the
input voltage first starts to rise is the charge current drawn by the input capacitors. Power-up is complete within
25 ms.
OVERCURRENT PROTECTION
For protection against load faults, all modules incorporate output overcurrent protection. Applying a load that
exceeds the regulator’s overcurrent threshold causes the regulated output to shut down. Following shutdown a
module periodically attempts to recover by initiating a soft-start power-up. This is described as a hiccup mode of
operation, whereby the module continues in a cycle of successive shutdown and power up until the load fault is
removed. During this period, the average current flowing into the fault is significantly reduced. Once the fault is
removed, the module automatically recovers and returns to normal operation.
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OUTPUT ON/OFF INHIBIT
Inhibit for applications requiring output voltage on/off control, each series of the PTH family incorporates an
output Inhibit control pin. The inhibit feature can be used wherever there is a requirement for the output voltage
from the regulator to be turned off.
The power modules function normally when the Inhibit pin is left open-circuit, providing a regulated output
whenever a valid source voltage is connected to VI with respect to GND.
Figure 14 shows the typical application of the inhibit function. Note the discrete transistor (Q1). The Inhibit input
has its own internal pull-up to a potential of 5 V to 13.2 V (see footnotes to specification table). The input is not
compatible with TTL logic devices. An open-collector (or open-drain) discrete transistor is recommended for
control.
VOSense
VI
2
+
1 = Inhibit
8
5
Q1
BSS138
7
VO
6
PTH12060W
3 1
CI
560 mF
9
4
CO
RSET
2 kW 330 mF
1%
0.1 W
+
10
L
O
A
D
GND
GND
Figure 14. Inhibit Control Circuit
Turning Q1 on applies a low voltage to the Inhibit control pin and disables the output of the module. If Q1 is then
turned off, the module executes a soft-start power-up sequence. A regulated output voltage is produced within
25 ms Figure 15 shows the typical rise in both the output voltage and input current, following the turn-off of Q1.
The turn off of Q1 corresponds to the rise in the waveform, Q1 Vds. The waveforms were measured with a 5-A
constant current load.
Q1VDS (5 V/div)
VO (2 V/div)
II (2 V/div)
t − Time − 10 ms/div
Figure 15. Power-Up from Inhibit Control
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Auto-Track™ Function
The Auto-Track function is unique to the PTH/PTV family, and is available with all POLA products. Auto-Track
was designed to simplify the amount of circuitry required to make the output voltage from each module power up
and power down in sequence. The sequencing of two or more supply voltages during power up is a common
requirement for complex mixed-signal applications that use dual-voltage VLSI ICs such as the TMS320™ DSP
family, microprocessors, and ASICs.
How Auto-Track™ Works
Auto-Track works by forcing the module output voltage to follow a voltage presented at the Track control pin (1).
This control range is limited to between 0 V and the module set-point voltage. Once the Track pin voltage is
raised above the set-point voltage, the module output remains at its set-point (2). As an example, if the Track pin
of a 2.5-V regulator is at 1 V, the regulated output is 1 V. If the voltage at the Track pin rises to 3 V, the
regulated output does not go higher than 2.5 V.
When under Auto-Track control, the regulated output from the module follows the voltage at its Track pin on a
volt-for-volt basis. By connecting the Track pin of a number of these modules together, the output voltages follow
a common signal during power up and power down. The control signal can be an externally generated master
ramp waveform, or the output voltage from another power supply circuit (3). For convenience, the Track input
incorporates an internal RC-charge circuit. This operates off the module input voltage to produce a suitable
rising waveform at power up.
Typical Application
The basic implementation of Auto-Track allows for simultaneous voltage sequencing of a number of Auto-Track
compliant modules. Connecting the Track inputs of two or more modules forces their Track input to follow the
same collective RC-ramp waveform, and allows their power-up sequence to be coordinated from a common
Track control signal. This can be an open-collector (or open-drain) device, such as a power-up reset voltage
supervisor IC. See U3 in Figure 16.
To coordinate a power-up sequence, the Track control must first be pulled to ground potential. This should be
done at or before input power is applied to the modules. The ground signal should be maintained for at least
40 ms after input power has been applied. This brief period gives the modules time to complete their internal
soft-start initialization (4), enabling them to produce an output voltage. A low-cost supply voltage supervisor IC,
with a built-in time delay, is an ideal component for automatically controlling the Track inputs at power up.
Figure 16 shows how the TL7712A supply voltage supervisor IC (U3) can be used to coordinate the sequenced
power up of two 12-V input Auto-Track modules. The output of the TL7712A supervisor becomes active above
an input voltage of 3.6 V, enabling it to assert a ground signal to the common Track control well before the input
voltage has reached the module's undervoltage lockout threshold. The ground signal is maintained until
approximately 43 ms after the input voltage has risen above U3's voltage threshold, which is 10.95 V. The
43-ms time period is controlled by the capacitor C3. The value of 3.3 µF provides sufficient time delay for the
modules to complete their internal soft-start initialization. The output voltage of each module remains at zero
until the Track control voltage is allowed to rise. When U3 removes the ground signal, the Track control voltage
automatically rises. This causes the output voltage of each module to rise simultaneously with the other
modules, until each reaches its respective set-point voltage.
Figure 17 shows the output voltage waveforms from the circuit of Figure 16 after input voltage is applied to the
circuit. The waveforms, VO1 and VO2, represent the output voltages from the two power modules, U1 (3.3 V) and
U2 (1.8 V), respectively. VTRK, VO1, and VO2 are shown rising together to produce the desired simultaneous
power-up characteristic.
The same circuit also provides a power-down sequence. When the input voltage falls below U3's voltage
threshold, the ground signal is re-applied to the common Track control. This pulls the Track inputs to zero volts,
forcing the output of each module to follow, as shown in Figure 18. In order for a simultaneous power-down to
occur, the Track inputs must be pulled low before the input voltage has fallen below the modules' undervoltage
lockout. This is an important constraint. Once the modules recognize that a valid input voltage is no longer
present, their outputs can no longer follow the voltage applied at their Track input. During a power-down
sequence, the fall in the output voltage from the modules is limited by the maximum output capacitance and the
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Auto-Track slew rate. If the Track pin is pulled low at a slew rate greater than 1 V/ms, the discharge of the
output capacitors will induce large currents which could exceed the peak current rating of the module. This will
result in a reduction in the maximum allowable output capacitance as listed in the Electrical Characteristics
table. When controlling the Track pin of the PTH12010W using a voltage supervisor IC, the slew rate is
increased, therefore COmax is reduced to 3300 µF.
Notes on Use of Auto-Track™
1. The Track pin voltage must be allowed to rise above the module set-point voltage before the module
regulates at its adjusted set-point voltage.
2. The Auto-Track function tracks almost any voltage ramp during power up, and is compatible with ramp
speeds of up to 1 V/ms.
3. The absolute maximum voltage that may be applied to the Track pin is the input voltage VI.
4. The module cannot follow a voltage at its Track control input until it has completed its soft-start initialization.
This takes about 40 ms from the time that a valid voltage has been applied to its input. During this period, it
is recommended that the Track pin be held at ground potential.
5. The Auto-Track function is disabled by connecting the Track pin to the input voltage (VI). When Auto-Track
is disabled, the output voltage rises at a quicker and more linear rate after input power has been applied.
2
U1
Track
VI = 12 V
3
+
VI
Inhibit
GND
4
1
Vo 1 = 3.3 V
6
VO
PTH12050W
Adjust
5
CI1
+
RSET1
CO1
2.0 kΩ
8
U3
7
2
1
3
VCC
SENSE
RESET
5
RTRK #
RESIN
TL7712A
REF
RESET
50 Ω
0.1 µF
9
Up Dn
8
5
Track
Sense
CT
2
GND
CREF
10
U2
6
CT
3.3 µF
4
PTH12060W
VI
VO
RRST
10 kΩ
# RTRK = 100 Ω / N
N = Number of Track pins connected together
Inhibit
+
3
C I2
Adjust
GND
1
7
4
RSET2
11.5 kΩ
Figure 16. Sequenced Power Up and Power Down Using Auto-Track
18
Vo 2 = 1.8 V
6
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VTRK (1 V/div)
VTRK (1 V/div)
V01 (1 V/div)
V01 (1 V/div)
V02 (1 V/div)
V02 (1 V/div)
t − Time − 400 µs/div
t − Time − 20 ms/div
Figure 17. Simultaneous Power Up with Auto-Track
Control
Figure 18. Simultaneous Power Down with Auto-Track
Control
MARGIN UP/DOWN CONTROLS
The PTH12060, PTH12010, PTH12020, and PTH12030 products incorporate Margin Up and Margin Down
control inputs. These controls allow the output voltage to be momentarily adjusted[1], either up or down, by a
nominal 5%. This provides a convenient method for dynamically testing the operation of the load circuit over its
supply margin or range. It can also be used to verify the function of supply voltage supervisors. The ±5% change
is applied to the adjusted output voltage, as set by the external resistor, RSET at the VO Adjust pin.
The 5% adjustment is made by pulling the appropriate margin control input directly to the GND terminal[2]. A
low-leakage open-drain device, such as an N-channel MOSFET or P-channel JFET is recommended for this
purpose[3]. Adjustments of less than 5% can also be accommodated by adding series resistors to the control
inputs. The value of the resistor can be selected from Table 6, calculated using the following formula.
UP/DOWN ADJUST RESISTANCE CALCULATION
To reduce the margin adjustment to a value less than 5%, series resistors are required (See RD and RU in
Figure 19). For the same amount of adjustment, the resistor value calculated for RU and RD are the same. The
formula is as follows.
RU or RD =
499
- 99.8 kW
D%
(2)
Where ∆% = The desired amount of margin adjust percent.
NOTES
1. The Margin Up and Margin Down controls were not intended to be activated simultaneously. If they are their
affects on the output voltage may not completely cancel, resulting in the possibility of a slightly higher error
in the output voltage set point.
2. The ground reference should be a direct connection to the module GND at pin 7 (pin 1 for the PTHxx050).
This will produce a more accurate adjustment at the load circuit terminals. The transistors Q1 and Q2 should
be located close to the regulator.
3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This
includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device
(preferably a discrete MOSFET transistor). The device selected should have low off-state leakage current.
Each input sources 8 µA when grounded, and has an open-circuit voltage of 0.8 V.
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Table 6. Margin Up/Down Resistor Values
% ADJUST
RU / RD
5
0 kΩ
4
24.9 kΩ
3
66.5 kΩ
2
150 kΩ
1
397 kΩ
1
10 9
8
7
VI
2
+
+VO
6
3
RD
+VO
0V
PT H12010W
(Top View)
4
5
RU
RSET
0.1 W, 1%
CI
+
CO
L
O
A
D
Q1
Margin Down
Q2
Margin Up
GND
GND
Figure 19. Margin Up/Down Application Schematic
PREBIAS STARTUP CAPABILITY
The capability to start up into an output prebias condition is now available to all the 12-V input, PTH series of
power modules. (Note that this is a feature enhancement for the many of the W-suffix products).[1]
A prebias startup condition occurs as a result of an external voltage being present at the output of a power
module prior to its output becoming active. This often occurs in complex digital systems when current from
another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another
path might be via clamp diodes, sometimes used as part of a dual-supply power-up sequencing arrangement. A
prebias can cause problems with power modules that incorporate synchronous rectifiers. This is because under
most operating conditions, such modules can sink as well as source output current. The 12-V input PTH
modules all incorporate synchronous rectifiers, but does not sink current during startup, or whenever the Inhibit
pin is held low. Startup includes an initial delay (approx. 8–15 ms), followed by the rise of the output voltage
under the control of the module’s internal soft-start mechanism; see Figure 20.
CONDITIONS FOR PREBIAS HOLDOFF
In order for the module to allow an output prebias voltage to exist (and not sink current), certain conditions must
be maintained. The module holds off a prebias voltage when theInhibit pin is held low, and whenver the output is
allowed to rise under soft-start control. Power up under soft-start control occurs upon the removal of the ground
signal to the Inhibit pin (with input voltage applied), or when input power is applied with Auto-Track disabled.[ 2]
To further ensure that the regulator doesn’t sink output current, (even with a ground signal applied to its Inhibit),
the input voltage must always be greater than the applied pre-bias source. This condition must exist throughout
the power-up sequence.[3]
The soft-start period is complete when the output begins rising above the pre-bias voltage. Once it is complete
the module functions as normal, and sinks current if voltage higher than the nominal regulation value is applied
to its output.
Note: If a prebias condition is not present, the soft-start period is complete when the output voltage has risen to
either the set-point voltage, or the voltage applied at the module’s Track control pin, whichever is lowest.
20
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DEMONSTRATION CIRCUIT
Figure 21 shows the startup waveforms for the demonstration circuit shown in Figure 22. The initial rise in VO2 is
the prebias voltage, which is passed from the VCCIO to the VCORE voltage rail through the ASIC. Note that the
output current from the PTH12010L module (IO2) is negligible until its output voltage rises above the applied
prebias.
UVLO Threshold
VO1 (1 V/div)
VI (5 V/div)
VO (1 V/div)
VO2 (1 V/div)
IO2 (5 V/div)
Startup
Period
t − Time − 5 ms/div
Figure 20. PTH12020W Startup
t − Time − 10 ms/div
Figure 21. Prebias Startup Waveforms
NOTES
1. Output prebias holdoff is an inherent feature to all PTH120x0L and PTV120x0W/L modules. It has now been
incorporated into all modules (including W-suffix modules with part numbers of the form PTH120x0W), with
a production lot date code of 0423 or later.
2. The prebias start-up feature is not compatible with Auto-Track. If the rise in the output is limited by the
voltage applied to the Track control pin, the output sinks current during the period that the track control
voltage is below that of the back-feeding source. For this reason, it is recommended that Auto-Track be
disabled when not being used. This is accomplished by connecting the Track pin to the input voltage, VI.
This raises the Track pin voltage well above the set-point voltage prior to the module’s start up, thereby
defeating the Auto-Track feature.
3. To further ensure that the regulator’s output does not sink current when power is first applied (even with a
ground signal applied to the Inhibit control pin), the input voltage must always be greater than the applied
pre-bias source. This condition must exist throughout the power-up sequence of the power system.
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10 9
Up
VI = 12 V
2
VI
GND
7
1
C1
330 mF
10 9
2
R4
100 k
TL7702B
C5
0.1 mF
8
VCC
7 SENSE
5
RESET
2
RESIN
1
REF
6
RESET
3 CT
GND
4
C6
R5
10 k0
0.68 mF
VO
VI
Inhibit
3
VO1 = 3.3 V
+
C2
330 mF
5
Sense
PTH12010L
GND
7
1
6
Adjust
4
R1
2k
8
Track
R3
11 k0
Sense
PTH12020W
Inhibit
3
+
5
8
Dn Track
VO
6
Vadj
4
VO2 = 1.8 V
+
IO2
R2
130 W
+ C3
330 mF
VC ORE
+ C4
330 mF
VC CI O
ASIC
Figure 22. Application Circuit Demonstrating Prebias Startup
REMOTE SENSE
Products with this feature incorporate an output voltage sense pin, VO Sense. A remote sense improves the load
regulation performance of the module by allowing it to compensate for any IR voltage drop between its output
and the load. An IR drop is caused by the high output current flowing through the small amount of pin and trace
resistance.
To use this feature simply connect the VO Sense pin to the VO node, close to the load circuit (see data sheet
standard application). If a sense pin is left open-circuit, an internal low-value resistor (15-Ω or less) connected
between the pin and and the output node, ensures the output remains in regulation.
With the sense pin connected, the difference between the voltage measured directly between the VO and GND
pins, and that measured from VO Sense to GND, is the amount of IR drop being compensated by the regulator.
This should be limited to a maximum of 0.3 V.
Note: The remote sense feature is not designed to compensate for the forward drop of non-inear or frequency
dependent components that may be placed in series with the converter output. Examples include OR-ing diodes,
filter inductors, ferrite beads, and fuses. When these components are enclosed by the remote sense connection
they are effectively placed inside the regulation control loop, which can adversely affect the stability of the
regulator.
22
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TAPE AND REEL SPECIFICATIONS
TRAY SPECIFICATIONS
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PTH12010LAH
ACTIVE
DIP MOD
ULE
EUH
10
25
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
PTH12010LAS
ACTIVE
DIP MOD
ULE
EUJ
10
25
TBD
Call TI
Level-1-235C-UNLIM
PTH12010LAST
ACTIVE
DIP MOD
ULE
EUJ
10
250
TBD
Call TI
Level-1-235C-UNLIM
PTH12010LAZ
ACTIVE
DIP MOD
ULE
EUJ
10
25
Pb-Free
(RoHS)
Call TI
Level-3-260C-168 HR
PTH12010LAZT
ACTIVE
DIP MOD
ULE
EUJ
10
250
Pb-Free
(RoHS)
Call TI
Level-3-260C-168 HR
PTH12010WAH
ACTIVE
DIP MOD
ULE
EUH
10
25
Pb-Free
(RoHS)
Call TI
N / A for Pkg Type
PTH12010WAS
ACTIVE
DIP MOD
ULE
EUJ
10
25
TBD
Call TI
Level-1-235C-UNLIM
PTH12010WAST
ACTIVE
DIP MOD
ULE
EUJ
10
250
TBD
Call TI
Level-1-235C-UNLIM
PTH12010WAZ
ACTIVE
DIP MOD
ULE
EUJ
10
25
Pb-Free
(RoHS)
Call TI
Level-3-260C-168 HR
PTH12010WAZT
ACTIVE
DIP MOD
ULE
EUJ
10
250
Pb-Free
(RoHS)
Call TI
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 1
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