MICROCHIP MCP6S92

MCP6S91/2/3
Single-Ended, Rail-to-Rail I/O, Low-Gain PGA
Features
Description
• Multiplexed Inputs: 1 or 2 channels
• 8 Gain Selections:
- +1, +2, +4, +5, +8, +10, +16 or +32 V/V
• Serial Peripheral Interface (SPI™)
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max.)
• Offset Mismatch Between Channels: 0 µV
• High Bandwidth: 1 to 18 MHz (typ.)
• Low Noise: 10 nV/√Hz @ 10 kHz (typ.)
• Low Supply Current: 1.0 mA (typ.)
• Single Supply: 2.5V to 5.5V
• Extended Temperature Range: -40°C to +125°C
The Microchip Technology Inc. MCP6S91/2/3 are
analog Programmable Gain Amplifiers (PGAs). They
can be configured for gains from +1 V/V to +32 V/V and
the input multiplexer can select one of up to two channels through a SPI port. The serial interface can also
put the PGA into shutdown to conserve power. These
PGAs are optimized for high-speed, low offset voltage
and single-supply operation with rail-to-rail input and
output capability. These specifications support singlesupply applications needing flexible performance or
multiple inputs.
Typical Applications
•
•
•
•
•
•
A/D Converter Driver
Multiplexed Analog Applications
Data Acquisition
Industrial Instrumentation
Test Equipment
Medical Instrumentation
Package Types
MCP6S91
PDIP, SOIC, MSOP
Block Diagram
VDD
CH0
CH1
MUX
VOUT
SPI™
Logic
RF
8
Gain
Switches
RG
VSS
 2004 Microchip Technology Inc.
MCP6S93
MSOP
VOUT 1
8 VDD
VOUT 1
10 VDD
CH0 2
7 SCK
CH0 2
9 SCK
VREF 3
VSS 4
6 SI
CH1 3
8 SO
5 CS
VREF 4
7 SI
VSS 5
6 CS
MCP6S92
PDIP, SOIC, MSOP
Resistor Ladder (RLAD)
CS
SI
SO
SCK
The one-channel MCP6S91 and the two-channel
MCP6S92 are available in 8-pin PDIP, SOIC and MSOP
packages. The two-channel MCP6S93 is available in a
10-pin MSOP package. All parts are fully specified from
-40°C to +125°C.
VOUT 1
8 VDD
CH0 2
7 SCK
CH1 3
VSS 4
6 SI
5 CS
VREF
DS21908A-page 1
MCP6S91/2/3
1.0
ELECTRICAL
CHARACTERISTICS
PIN FUNCTION TABLE
Name
VOUT
Absolute Maximum Ratings †
Function
Analog Output
CH0, CH1 Analog Inputs
VDD – VSS ........................................................................7.0V
VREF
External Reference Pin
VSS
Negative Power Supply
Output Short Circuit Current ..................................continuous
CS
SPI Chip Select
Current at Input Pin .............................................................±2 mA
SI
SPI Serial Data Input
All inputs and outputs..................... VSS – 0.3V to VDD + 0.3V
Difference Input voltage ....................................... |VDD – VSS|
Current at Output and Supply Pins ................................ ±30 mA
SO
Storage temperature .....................................-65°C to +150°C
SCK
SPI Clock Input
Junction temperature .................................................. +150°C
VDD
Positive Power Supply
SPI Serial Data Output
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2, SI and SCK are tied low and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
VOS
-4
—
+4
mV
Conditions
Amplifier Inputs (CH0, CH1)
Input Offset Voltage
Input Offset Voltage Mismatch
Input Offset Voltage Drift
Power Supply Rejection Ratio
∆VOS
—
0
—
µV
∆VOS/∆TA
—
±1.8
—
µV/°C
G = +1
Between inputs (CH0, CH1)
TA = -40°C to +125°C
PSRR
70
90
—
dB
G = +1 (Note 1)
Input Bias Current
IB
—
±1
—
pA
CHx = VDD/2
Input Bias Current at
Temperature
IB
—
30
—
pA
CHx = VDD/2, TA = +85°C
IB
—
600
—
pA
CHx = VDD/2, TA = +125°C
ZIN
—
1013||7
—
Ω||pF
VIVR
VSS − 0.3
—
VDD + 0.3
V
Input Impedance
Input Voltage Range
(Note 2)
Reference Input (VREF)
Input Impedance
ZIN_REF
—
(5/G)||6
—
kΩ||pF
Voltage Range
VIVR_REF
VSS
—
VDD
V
(Note 2)
Amplifier Gain
Nominal Gains
G
—
1 to 32
—
V/V
gE
-0.2
—
+0.2
%
G ≥ +2
gE
-1.0
—
+1.0
%
G = +1
∆G/∆TA
—
±0.0002
—
%/°C
TA = -40°C to +125°C
∆G/∆TA
—
±0.0004
—
%/°C
TA = -40°C to +125°C
DC Gain Error
G = +1
DC Gain Drift
G ≥ +2
Note 1:
2:
3:
+1, +2, +4, +5, +8, +10, +16 or +32
VOUT ≈ 0.3V to VDD − 0.3V
VOUT ≈ 0.3V to VDD − 0.3V
RLAD (RF+RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S92 has
VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
recommended that the MCP6S92’s VSS pin be tied directly to ground to avoid noise problems.
The MCP6S92’s VIVR and VIVR_REF are not tested in production; they are set by design and characterization.
IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.
 2004 Microchip Technology Inc.
DS21908A-page 2
MCP6S91/2/3
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2, SI and SCK are tied low and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Ladder Resistance
Ladder Resistance
RLAD
3.4
4.9
6.4
kΩ
∆RLAD/∆TA
—
+0.028
—
%/°C
DC Output Non-linearity G = +1
VONL
—
±0.18
G ≥ +2
VONL
—
±0.050
VOH_ANA,
VOL_ANA
VSS + 20
—
% of FSR VOUT ≈ 0.3V to VDD − 0.3V, VDD = 5.0V
VDD – 100
mV
G ≥ +2; 0.5V output overdrive
VSS + 60
—
VDD – 60
ISC
—
±25
—
Ladder Resistance across
Temperature
(Note 1)
TA = -40°C to +125°C (Note 1)
Amplifier Output
Maximum Output Voltage Swing
Short Circuit Current
—
% of FSR VOUT ≈ 0.3V to VDD − 0.3V, VDD = 5.0V
—
G ≥ +2; 0.5V output overdrive,
VREF = VDD/2
mA
Power Supply
Supply Voltage
Minimum Valid Supply Voltage
Quiescent Current
Quiescent Current, Shutdown
Mode
Note 1:
2:
3:
VDD
2.5
—
5.5
V
VDD_VAL
—
0.4
2.0
V
IQ
0.4
1.0
1.6
mA
IO = 0 (Note 3)
IQ_SHDN
—
30
—
pA
IO = 0 (Note 3)
Register data still valid
RLAD (RF+RG in Figure 4-1) connects VREF, VOUT and the inverting input of the internal amplifier. The MCP6S92 has
VREF tied internally to VSS, so VSS is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. It is
recommended that the MCP6S92’s VSS pin be tied directly to ground to avoid noise problems.
The MCP6S92’s VIVR and VIVR_REF are not tested in production; they are set by design and characterization.
IQ includes current in RLAD (typically 60 µA at VOUT = 0.3V). Both IQ and IQ_SHDN exclude digital switching currents.
 2004 Microchip Technology Inc.
DS21908A-page 3
MCP6S91/2/3
AC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Frequency Response
All gains; VOUT < 100 mVP-P (Note 1)
-3 dB Bandwidth
BW
—
1 to 18
—
MHz
Gain Peaking
GPK
—
0
—
dB
All gains; VOUT < 100 mVP-P
f = 20 kHz, G = +1 V/V
THD+N
—
0.0011
—
%
VOUT = 1.5V ± 1.0 VPK, VDD = 5.0V,
BW = 80 kHz, RL = 10 kΩ to 1.5V
f = 20 kHz, G = +1 V/V
THD+N
—
0.0089
—
%
VOUT = 2.5V ± 1.0 VPK, VDD = 5.0V,
BW = 80 kHz
f = 20 kHz, G = +4 V/V
THD+N
—
0.0045
—
%
VOUT = 2.5V ± 1.0 VPK, VDD = 5.0V,
BW = 80 kHz
f = 20 kHz, G = +16 V/V
THD+N
—
0.028
—
%
VOUT = 2.5V ± 1.0 VPK, VDD = 5.0V,
BW = 80 kHz
SR
—
4.0
—
V/µs
—
11
—
V/µs
G = 4, 5, 8, 10
—
22
—
V/µs
G = 16, 32
—
4.5
—
µVP-P
f = 0.1 Hz to 10 Hz (Note 2)
—
30
—
Total Harmonic Distortion plus Noise
Step Response
Slew Rate
G = 1, 2
Noise
Input Noise Voltage
Eni
f = 0.1 Hz to 200 kHz (Note 2)
Input Noise Voltage Density
eni
—
10
—
nV/√Hz f = 10 kHz (Note 2)
Input Noise Current Density
ini
—
4
—
fA/√Hz f = 10 kHz
Note 1:
2:
See Table 4-1 for a list of typical numbers and Figure 2-25 for the frequency response versus gain.
Eni and eni include ladder resistance noise. See Figure 2-12 for eni versus G data.
 2004 Microchip Technology Inc.
DS21908A-page 4
MCP6S91/2/3
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = 25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2, CL = 60 pF, SI and SCK are tied low and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
VIL
0
—
0.3VDD
V
Input Leakage Current
IIL
-1.0
—
+1.0
µA
Logic Threshold, High
VIH
0.7 VDD
—
VDD
V
Amplifier Output Leakage Current
—
-1.0
—
1.0
µA
In Shutdown mode
Logic Threshold, Low
VOL_DIG
VSS
—
VSS+0.4
V
IOL = 2.1 mA, VDD = 5V
Logic Threshold, High
VOH_DIG
VDD – 0.5
—
VDD
V
IOH = -400 µA
SPI Output (SO, for MCP6S93)
SPI Timing
Pin Capacitance
CPIN
—
10
—
pF
All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
tRFI
—
—
2
µs
(Note 1)
Output Rise/Fall Times (SO)
tRFO
—
5
—
ns
MCP6S93
CS High Time
tCSH
40
—
—
ns
SCK Edge to CS Fall Setup Time
tCS0
10
—
—
ns
CS Fall to First SCK Edge Setup Time
tCSSC
40
—
—
ns
SCK Frequency
fSCK
—
—
10
MHz
SCK High Time
tHI
40
—
—
ns
SCK edge when CS is high
VDD = 5V (Note 2)
tLO
40
—
—
ns
tSCCS
30
—
—
ns
CS Rise to SCK Edge Setup Time
tCS1
100
—
—
ns
SI Setup Time
tSU
40
—
—
ns
SI Hold Time
tHD
10
—
—
ns
SCK to SO Valid Propagation Delay
tDO
—
—
80
ns
MCP6S93
CS Rise to SO Forced to Zero
tSOZ
—
—
80
ns
MCP6S93
Channel Select Time
tCH
—
1.5
—
µs
CHx = 0.6V, CHy = 0.3V, G = 1,
CHx to CHy select,
CS = 0.7 VDD to VOUT 90% point
Gain Select Time
tG
—
1
—
µs
CHx = CHy = 0.3V,
G = 5 to G = 1 select,
CS = 0.7 VDD to VOUT 90% point
Out of Shutdown mode (CS goes high)
to Amplifier Output Turn-on Time
tON
—
3.5
10
µs
CS = 0.7 VDD to VOUT 90% point
Into Shutdown mode (CS goes high) to
Amplifier Output High-Z Turn-off Time
tOFF
—
1.5
—
µs
CS = 0.7 VDD to VOUT 90% point
SCK Low Time
SCK Last Edge to CS Rise Setup Time
SCK edge when CS is high
Channel and Gain Select Timing
Shutdown Mode Timing
Note 1:
2:
Not tested in production. Set by design and characterization.
When using the device in the daisy-chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (tDO ≤ 80 ns), data input set-up time (tSU ≥ 40 ns), SCK high time (tHI ≥ 40 ns) and SCK rise and
fall times of 5 ns. Maximum fSCK is therefore ≈ 5.8 MHz.
 2004 Microchip Technology Inc.
DS21908A-page 5
MCP6S91/2/3
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
(Note 1)
Thermal Package Resistances
Thermal Resistance, 8L-PDIP
θJA
—
85
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
163
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 10L-MSOP
θJA
—
143
—
°C/W
Note 1:
Operation in this range must not cause TJ to exceed Maximum Junction Temperature (+150°C).
 2004 Microchip Technology Inc.
DS21908A-page 6
MCP6S91/2/3
CS
CS
tCH
VOUT
tG
0.6V
FIGURE 1-1:
Diagram.
1.5V
VOUT
0.3V
0.3V
FIGURE 1-3:
Diagram.
Channel Select Timing
Gain Select Timing
CS
tON
tOFF
Hi-Z
VOUT
Hi-Z
0.3V
1.0 mA (typ.)
ISS
30 pA (typ.)
FIGURE 1-2:
PGA Shutdown Timing
Diagram (must enter correct commands before
CS goes high).
tCSH
CS
tCSSC
tSCCS tCS1
tLO
tCS0
tHI
SCK
tSU tHD
1/fSCK
SI
tDO
tSOZ
SO
(first 16 bits out are always zeros)
FIGURE 1-4:
Detailed SPI™ Serial Interface Timing; SPI 0,0 Mode.
 2004 Microchip Technology Inc.
DS21908A-page 7
MCP6S91/2/3
tCSH
CS
tCSSC
tSCCS tCS1
tHI
tCS0
tLO
SCK
tSU tHD
1/fSCK
SI
tSOZ
tDO
SO
(first 16 bits out are always zeros)
FIGURE 1-5:
1.1
Detailed SPI™ Serial Interface Timing; SPI 1,1 Mode.
DC Output Voltage Specs / Model
1.1.1
IDEAL MODEL
The ideal PGA output voltage (VOUT) is:
EQUATION 1-3:
EQUATION 1-1:
VO_ID = G VIN
The end points of this line are at VO_ID = 0.3V and
VDD – 0.3V. Figure 1-6 shows the relationship between
the gain and offset specifications referred to in the
electrical specifications as follows:
V REF = V SS = 0V
Where:
G is the nominal gain
V2 – V1
g E = 100% -------------------------------------G ( VDD – 0.6V )
V1
VOS = ------------------------G ( 1 + gE )
G = +1
(see Figure 1-6). This equation holds when there are
no gain or offset errors and when the VREF pin is tied to
a low-impedance source (<< 0.1Ω) at ground potential
(VSS = 0V).
The DC Gain Drift (∆G/∆TA) can be calculated from the
change in gE across temperature. This is shown in the
following equation:
1.1.2
EQUATION 1-4:
LINEAR MODEL
The PGA’s linear region of operation, including offset
and gain errors, is modeled by the line VO_LIN shown in
Figure 1-6.
∆g E
∆G ⁄ ∆T A = ---------∆T A
EQUATION 1-2:
0.3V
V O_LIN = G ( 1 + g E )  VIN – ----------- + V OS + 0.3V


G
VREF = V SS = 0V
 2004 Microchip Technology Inc.
DS21908A-page 8
MCP6S91/2/3
1.1.4
VOUT (V)
VDD
V2
VDD – 0.3
DIFFERENT VREF CONDITIONS
Some of the plots in Section 2.0 “Typical Performance
Curves”, have the conditions VREF = VDD/2 or
VREF = VDD. The equations and figures above are easily
modified for these conditions. The ideal VOUT equation
becomes:
O
V _LIN
O
_I
D
V O_ID = VREF + G ( VIN – VREF )
V DD ≥ V REF > V SS = 0V
V
V
O
UT
EQUATION 1-7:
V1
0.3
0
VIN (V)
0.3
G
0
VDD – 0.3 VDD
G
G
FIGURE 1-6:
Output Voltage Model with
the standard condition VREF = VSS = 0V.
1.1.3
The complete linear model is:
EQUATION 1-8:
V ON_LIN = G ( 1 + g E ) ( V IN – VIN_L + VOS ) + 0.3V
V REF = VSS = 0V
where the new VIN end points are:
OUTPUT NON-LINEARITY
Figure 1-7 shows the Integral Non-Linearity (INL) of the
output voltage.
EQUATION 1-5:
EQUATION 1-9:
0.3V – VREF
V IN_L = ------------------------------ + V REF
G
INL = V OUT – V O_LIN
VDD – 0.3V – VREF
V IN_H = ----------------------------------------------- + V REF
G
The output non-linearity specification in the Electrical
Specifications (with units of: % of FSR) is related to
Figure 1-7 by:
The equations for extracting the specifications do not
change.
EQUATION 1-6:
max ( V3, V4 )
V ONL = ------------------------------- ⋅ 100%
V DD – 0.6V
The Full-Scale Range (FSR) is VDD – 0.6V
(0.3V to VDD – 0.3V).
INL (V)
V4
0
V3
0
0.3
G
VDD – 0.3 VDD
G
G
VIN (V)
FIGURE 1-7:
Output Voltage INL with the
standard condition VREF = VSS = 0 V.
 2004 Microchip Technology Inc.
DS21908A-page 9
MCP6S91/2/3
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
600 Samples
G = +1
TA = -40 to +125°C
30%
25%
20%
15%
10%
5%
DC Gain Error (%)
DC Gain Error, G ≥ +2.
10%
8%
6%
4%
2%
Ladder Resistance Drift (%/°C)
Ladder Resistance Drift.
 2004 Microchip Technology Inc.
0.030
0.029
0.028
0.027
0.026
0.025
0.024
0.023
0.022
0.021
0.020
0%
Crosstalk, Input Referred (dB)
FIGURE 2-5:
12%
FIGURE 2-3:
0.0006
0.0005
0.0004
0.0003
0.0002
0.0000
0.0001
0.0020
0.0016
0.0012
0.0008
0.0004
0.0000
-0.0004
DC Gain Drift (%/°C)
597 Samples
TA = -40 to +125°C
0.019
Percentage of Occurrences
14%
-0.0008
-0.0012
600 Samples
G ≥ +2
TA = -40 to +125°C
DC Gain Error (%)
16%
-0.0001
DC Gain Drift, G = +1.
-0.0016
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
26%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-0.0020
Percentage of Occurrences
FIGURE 2-4:
600 Samples
G ≥ +2
FIGURE 2-2:
-0.0002
DC Gain Drift (%/°C)
DC Gain Error, G = +1.
-0.5
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-0.6
Percentage of Occurrences
FIGURE 2-1:
-0.0003
-0.0004
-0.0005
0%
-0.0006
Percentage of Occurrences
35%
0.10
0.08
0.06
0.04
0.02
0.00
-0.02
-0.04
-0.06
600 Samples
G = +1
-0.08
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
-0.10
Percentage of Occurrences
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
-10
DC Gain Drift, G ≥ +2.
VDD = 5.0V
G = +32 V/V
CH0 selected
RS = 10 kΩ
-20
-30
-40
-50
RS = 1 kΩ
-60
RS = 100 Ω
-70
-80
-90
-100
100k
1.E+05
RS = 0 Ω
1.E+06
1.E+07
1M
10M
Frequency (Hz)
1.E+08
100M
FIGURE 2-6:
Crosstalk vs. Frequency
(circuit in Figure 6-4).
DS21908A-page 10
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
-1
0
1
2
Input Offset Voltage (mV)
35%
25%
FIGURE 2-10:
σ = 10.0 µVRMS
Measurement
Repeatability:
10.4 µVRMS
20%
15%
10%
5%
30
20
10
0
-10
-20
0%
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
Input Offset Voltage
Input Noise Voltage Density
(nV/—Hz)
Input Noise Voltage Density
(nV/—Hz)
100
10
0.1
0.1
FIGURE 2-9:
vs. Frequency.
1
1
10
100
1000
10
100
1k
Frequency (Hz)
10000
10k
8
6
4
VDD = 5.5V
VDD = 2.5V
Input Offset Voltage vs.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
f = 10 kHz
100000
100k
Input Noise Voltage Density
 2004 Microchip Technology Inc.
G = +1
VIN = VREF
FIGURE 2-11:
VREF Voltage.
1000
1
Input Offset Voltage Drift.
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VREF Voltage (V)
Input Offset Voltage Mismatch (µV)
FIGURE 2-8:
Mismatch.
2
Input Offset Voltage Drift (µV/°C)
Input Offset Voltage,
32 Samples
VDD = 5.5V
VIN = 0.3V
30%
-30
Percentage of Occurrences
FIGURE 2-7:
VDD = 4.0V.
3
10
-2
Input Offset Voltage (mV)
-3
-10
0%
0
5%
-2
10%
-4
15%
-6
20%
600 Samples
TA = -40 to +125°C
G = +1
-8
600 Samples
G = +1
VDD = 4.0V
25%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Percentage of Occurrences
Percentage of Occurrences
30%
1
FIGURE 2-12:
vs. Gain.
2
4
5
8
Gain (V/V)
10
16
32
Input Noise Voltage Density
DS21908A-page 11
MCP6S91/2/3
120
Power Supply Rejection Ratio
(dB)
110
100
90
80
70
-50
-25
0
25
50
75
100
125
100
VDD = 2.5V
90
70
60
50
40
30
20
10
100
10
1000
100
PSRR vs. Ambient
FIGURE 2-16:
10,000
VDD = 5.5V
CH0 = 5.0V
100
MCP6S91
1000000
100k
1M
MCP6S92/3
10
PSRR vs. Frequency.
MCP6S92/3
VDD = 5.5V
1,000
TA = +125°C
100
TA = +85°C
10
1
1
50
75
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
125
Ambient Temperature (°C)
Input Voltage (V)
VDD = 5.5V
1.E-09
1n
100p
1.E-10
VDD = 2.5V
10p
1.E-11
1p
1.E-12
25%
20%
Input Bias Current vs. Input
39 Samples
VDD = 5.5V
CH0 = VDD/2
15%
10%
5%
75
100
Ambient Temperature (°C)
FIGURE 2-15:
Quiescent Current in
Shutdown Mode vs. Ambient Temperature.
 2004 Microchip Technology Inc.
125
42
50
38
25
34
0
30
-25
26
-50
18
0%
100f
1.E-13
14
1.E-08
10n
In Shutdown Mode
CH0 = VDD/2
10
1.E-07
100n
FIGURE 2-17:
Voltage.
Percentage of Occurrences
FIGURE 2-14:
Input Bias Current vs.
Ambient Temperature.
Quiescent Current in
Shutdown (A)
100000
10k
Frequency (Hz)
Input Bias Current (pA)
Input Bias Current (pA)
1,000
10000
1k
Ambient Temperature (°C)
FIGURE 2-13:
Temperature.
Input Referred
VDD = 5.5V
80
22
Power Supply Rejection Ratio
(dB)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
Quiescent Current in Shutdown (pA)
FIGURE 2-18:
Shutdown Mode.
Quiescent Current in
DS21908A-page 12
MCP6S91/2/3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
35
Output Short Circuit Current
Magnitude (mA)
Quiescent Current (mA)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
30
25
20
10
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Quiescent Current vs.
DC Output Non-Linearity,
Input Referred (% of FSR)
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
FIGURE 2-22:
Output Short Circuit Current
vs. Supply Voltage.
VOUT = 0.3V to VDD - 0.3V
0.1
0.01
VONL/G, G = +1
G = +2
G ≥ +4
1
DC Output Non-Linearity,
Input Referred (% of FSR)
FIGURE 2-19:
Supply Voltage.
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
15
0.001
VDD = 5.5V
0.1
VONL/G:
G = +1
G = +2
G ≥ +4
0.01
0.001
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
FIGURE 2-20:
Supply Voltage.
DC Output Non-Linearity vs.
FIGURE 2-23:
Output Swing.
10
Output Voltage Swing (V P-P)
Output Voltage Headroom;
VDD-VOH and VOL-VSS (mV)
1000
VDD = 5.5V
100
VDD = 2.5V
10
1
1
10
VDD = 2.5V
1
G = 1, 2
G = 4 to 10
G = 16, 32
0.1
100k
 2004 Microchip Technology Inc.
1.E+06
1.E+07
1M
10M
Frequency (Hz)
Output Plus Ladder Current Magnitude (mA)
FIGURE 2-21:
Output Voltage Headroom
vs. Output Plus Ladder Current (circuit in
Figure 4-2).
DC Output Non-Linearity vs.
VDD = 5.5V
1.E+05
0.1
10
Output Voltage Swing (VP-P)
Power Supply Voltage (V)
FIGURE 2-24:
Frequency.
Output Voltage Swing vs.
DS21908A-page 13
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
40
6
Gain Peaking (dB)
30
Gain (dB)
7
G = +32
G = +16
20
10
0
G = +10
G = +8
G = +5
G = +4
-10
-20
100k
1.E+05
G = +2
G = +1
G = +16
G = +4
G = +1
4
3
2
1
0
1.E+06
1.E+07
1.E+08
1M
10M
Frequency (Hz)
FIGURE 2-25:
5
10
100M
100
1000
Capacitive Load (pF)
FIGURE 2-28:
Load.
Gain vs. Frequency.
100
Gain Peaking vs. Capacitive
6
Input, Output Voltage (V)
Bandwidth (MHz)
VIN
G = +1
G = +4
G = +16
10
1
10
100
Capacitive Load (pF)
FIGURE 2-26:
Load.
4
3
2
1
0
0
1
2
3
4
Bandwidth vs. Capacitive
THD + Noise (%)
Measurement BW = 80 kHz
VOUT = 2.0VP-P
VDD = 5.0V
G = +16
G = +1
0.01
G = +4
0.001
1.E+02
1.E+03
8
9
10
0.1
G = +16
0.01
0.001
G = +4
G = +1
1.E+04
1k
10k
Frequency (Hz)
FIGURE 2-27:
THD plus Noise vs.
Frequency, VOUT = 2 VP-P.
 2004 Microchip Technology Inc.
7
Measurement BW = 80 kHz
VOUT = 4 VP-P
VDD = 5.0V
G = +1, RL = 10 kΩ to 1.5V
0.0001
100
6
FIGURE 2-29:
The MCP6S91/2/3 family
shows no phase reversal under overdrive.
1
0.1
5
Time (1 µs/div)
1
THD + Noise (%)
VOUT
-1
1000
VDD = 5.0V
G = +1 V/V
5
1.E+05
100k
0.0001
100
1.E+02
1.E+03
1k
1.E+04
10k
1.E+05
100k
Frequency (Hz)
FIGURE 2-30:
THD plus Noise vs.
Frequency, VOUT = 4 VP-P.
DS21908A-page 14
MCP6S91/2/3
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
60
300
150
20
100
10
50
GVIN
0
0
-10
-50
VOUT
G = +1
G = +5
G = +32
-150
-200
-50
0.200
0.400
0.600
0.800
1.000
1.200
1.400
1.600
1.0
0.0
0.5
1.0
1.5
Time (200 ns/div)
Small-Signal Pulse
FIGURE 2-34:
Response.
0.65
10
5
CS
CS
0.45
0
0.40
-5
0.35
-10
VOUT
(CH1 = 0.3V, G = +1)
0.30
0.25
0.00
0.50
1.00
1.50
2.00
5
0
-15
2.50
3.00
3.50
4.00
-20
5.00
4.50
5
CS
1.5
0
1.0
-5
VOUT is "ON"
0.5
-10
1.E+00
2.E+00
3.E+00
4.E+00
5.E+00
6.E+00
7.E+00
8.E+00
9.E+00
1.E+01
1.E+01
Time (1 µs/div)
FIGURE 2-33:
Shutdown Mode.
Output Voltage vs.
 2004 Microchip Technology Inc.
-2.5
15
10
1.0
5
CS
0.8
CS
0
0.6
-5
0.4
-10
VOUT
(CH0 = 0.3V, G = +1)
0
500
1000
1500
2000
2500
-15
3000
3500
4000
4500
5000
-20
1.E+01
-15
Gain Select Timing.
90%
32 Samples
1st Wafer Lot
80%
70%
60%
50%
40%
30%
20%
10%
0%
0.0
10
CS
0.E+00
5.0
Large-Signal Pulse
FIGURE 2-35:
Percentage of Occurrences
Shutdown
2.0
0.0
4.5
Time (500 ns/div)
Chip Select Voltage (V)
Output Voltage (mV)
2.5
4.0
1.2
0.0
15
VDD = 5.0V
CH0 = 0.3V
G = +1
Shutdown
3.5
20
0.2
Channel Select Timing.
3.0
3.0
VOUT
(CH0 = 0.3V, G = +5)
Time (500 ns/div)
FIGURE 2-32:
-1.5
2.5
1.4
Output Voltage (V)
0.50
15
Chip Select Voltage (V)
Output Voltage (V)
0.55
-0.5
1.6
20
VOUT
(CH0 = 0.6V,
G = +1)
0.60
2.0
0.5
Time (500 ns/div)
0.5
FIGURE 2-31:
Response.
1.5
VOUT
G = +1
G = +5
G = +32
1.5
0.0
-300
2.000
1.800
2.5
2.0
Chip Select Voltage (V)
-60
0.000
3.5
2.5
0.5
-250
4.5
GVIN
3.0
2.0
-40
-100
5.5
3.5
1.5
-30
4.0
1.0
-20
6.5
Normalized Input Voltage
(1V/div)
30
4.5
Output Voltage (V)
200
7.5
VDD = 5.0V
250
40
Normalized Input Voltage
(50 mV/div)
Output Voltage
(10 mV/div)
5.0
VDD = 5.0V
50
Minimum Valid Supply Voltage (V)
FIGURE 2-36:
Minimum Valid Supply
Voltage (register data still valid).
DS21908A-page 15
MCP6S91/2/3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
G = 1 V/V
VDD = 2.5V
0.0
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.5
1.0
Input Offset Voltage (mV)
Input Offset Voltage (mV)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VREF = VSS, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 = 0.3V, RL = 10 kΩ to VDD/2 and CL = 60 pF.
1.5
2.0
2.5
Input Voltage (V)
Output Voltage Headroom;
VDD–VOH and VOL–VSS (mV)
G = 1 V/V
VDD = 5.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
FIGURE 2-37:
Input Offset Voltage vs.
Input Voltage, VDD = 2.5V.
35
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
FIGURE 2-39:
Input Offset Voltage vs.
Input Voltage, VDD = 5.5V.
VREF = VSS
30
VDD = 5.5V: VDD–VOH
VOL–VSS
VDD = 2.5V: VDD–VOH
VOL–VSS
25
20
15
10
5
0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 2-38:
Output Voltage Headroom
vs. Ambient Temperature.
 2004 Microchip Technology Inc.
DS21908A-page 16
MCP6S91/2/3
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6S91
MCP6S92
MCP6S93
Symbol
1
1
1
VOUT
Analog Output
2
2
2
CH0
Analog Input
—
3
3
CH1
Analog Input
3
—
4
VREF
External Reference Pin
4
4
5
VSS
Negative Power Supply
5
5
6
CS
SPI™ Chip Select
6
6
7
SI
SPI Serial Data Input
—
—
8
SO
7
7
9
SCK
SPI Clock Input
8
8
10
VDD
Positive Power Supply
3.1
Analog Output
Description
SPI Serial Data Output
3.4
Power Supply (VSS and VDD)
The output pin (VOUT) is a low-impedance voltage
source. The selected gain (G), selected input (CH0,
CH1) and voltage at VREF determine its value.
The Positive Power Supply Pin (VDD) is 2.5V to 5.5V
higher than the Negative Power Supply Pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
3.2
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts can
share a bulk capacitor with analog parts (typically
2.2 µF to 10 µF) within 100 mm of the VDD pin.
Analog Inputs (CH0, CH1)
The inputs CH0 and CH1 connect to the signal
sources. They are high-impedance CMOS inputs with
low bias currents. The internal MUX selects which one
is amplified to the output.
3.3
External Reference Voltage (VREF)
The VREF pin, which is an analog input, should be at a
voltage between VSS and VDD (the MCP6S92 has
VREF tied internally to VSS). The voltage at this pin
shifts the output voltage.
3.5
Digital Inputs
The SPI interface inputs are: Chip Select (CS), Serial
Input (SI) and Serial Clock (SCK). These are Schmitttriggered, CMOS logic inputs.
3.6
Digital Output
The MCP6S93 device has a SPI interface Serial Output
(SO) pin. This is a CMOS push-pull output and does
not ever go High-Z. Once the device is deselected (CS
goes high), SO is forced low. This feature supports
daisy-chaining, as explained in Section 5.3 “DaisyChain Configuration”.
 2004 Microchip Technology Inc.
DS21908A-page 17
MCP6S91/2/3
4.0
ANALOG FUNCTIONS
4.2
The MCP6S91/2/3 family of Programmable Gain
Amplifiers (PGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
VDD
MUX
CS
SI
SO
SCK
SPI™
Logic
VOUT
RF
8
Gain
Switches
RG
Resistor Ladder (RLAD)
CH0
CH1
VREF
VSS
MCP6S91 – One input (CH0), no SO pin
MCP6S92 – Two inputs (CH0, CH1), VREF tied
internally to VSS, no SO pin
MCP6S93 – Two inputs (CH0, CH1)
FIGURE 4-1:
4.1
PGA Block Diagram.
Input MUX
Internal Op Amp
The internal op amp gives the right combination of
bandwidth, accuracy and flexibility.
4.2.1
COMPENSATION CAPACITORS
The internal op amp has three compensation capacitors (comp. caps.) connected to a switching network.
They are selected to give good small-signal bandwidth
at high gains and good slew rates (full-power bandwidth) at low gains. The change in bandwidth as gain
changes is between 2 and 12 MHz. Refer to Table 4-1
for more information.
TABLE 4-1:
Gain
(V/V)
Internal
Comp.
Cap.
GBWP
(MHz)
Typ.
SR
(V/µs)
Typ.
FPBW
(MHz)
Typ.
BW
(MHz)
Typ.
1
Large
12
4.0
0.30
12
2
Large
12
4.0
0.30
6
4
Medium
20
11
0.70
10
5
Medium
20
11
0.70
7
8
Medium
20
11
0.70
2.4
10
Medium
20
11
0.70
2.0
16
Small
64
22
1.6
5
32
Small
64
22
1.6
2.0
Note 1:
The MCP6S91 has one input, while the MCP6S92 and
MCP6S93 have two inputs (see Figure 4-1).
2:
For the lowest input current, float unused inputs. Tying
these pins to a voltage near the active channel’s bias
voltage also works well. For simplicity, they can be tied
to VSS or VDD, but the input current may increase.
3:
The one-channel MCP6S91 has approximately the
same input bias current as the two-channel MCP6S92
and MCP6S93.
The input offset voltage mismatch between channels
(∆VOS) is, ideally, 0 µV. The input MUX uses CMOS
transmission gates that have drain-source (channel)
resistance, but no offset voltage. The histogram in
Figure 2-8 reflects the measurement repeatability
(i.e., noise power bandwidth) rather than the actual
mismatch. Reducing the measurement bandwidth will
produce a more narrow histogram and give an average closer to 0 µV.
 2004 Microchip Technology Inc.
GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
4.2.2
FPBW is the Full-Power Bandwidth.
These numbers are based on VDD = 5.0V.
No changes in DC performance
(e.g., VOS) accompany a change in
compensation capacitor.
BW is the closed-loop, small signal -3 dB
bandwidth.
RAIL-TO-RAIL CHANNEL INPUTS
The input stage of the internal op amp uses two differential input stages in parallel; one operates at low VIN
(input voltage), while the other operates at high VIN.
With this topology, the internal inputs can operate to
0.3V past either supply rail. The input offset voltage is
measured at both VIN = VSS – 0.3V and VDD + 0.3V to
ensure proper operation.
The transition between the two input stages occurs
when VIN ≈ VDD – 1.5V. For the best distortion and gain
linearity, avoid this region of operation.
DS21908A-page 18
MCP6S91/2/3
4.2.3
RAIL-TO-RAIL OUTPUT
The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (IOUT) and the current through the ladder
resistance (ILAD); see Figure 4-2.
MCP6S9X
RIN
VIN
EQUATION 4-1:
RIN ≥
Amplifier Load Current = I OUT + I LAD
Where:
RIN ≥
( VOUT – VREF )
I LAD = ------------------------------------RLAD
VOUT
ILAD
RLAD
VREF
FIGURE 4-2:
Amplifier Load Current.
See Figure 2-21 for the typical output headroom
(VDD – VOH or VOL – VSS) as a function of amplifier
load current.
The specification table states the output can reach
within 60 mV of either supply rail when RL = 10 kΩ and
VREF = VDD/2.
4.2.4
(Maximum expected VIN) – VDD
2 mA
VSS – (Maximum expected VIN)
FIGURE 4-3:
into an input pin.
4.3
IOUT
VOUT
CHx
2 mA
RIN limits the current flow
Resistor Ladder
The
resistor
ladder
shown
in
Figure 4-1
(RLAD = RF + RG) sets the gain. Placing the gain
switches in series with the inverting input reduces the
parasitic capacitance, distortion and gain mismatch.
RLAD is an additional load on the output of the PGA and
causes additional current draw from the supplies. It is
also a load (ZIN_REF) on the external circuitry driving
the VREF pin.
In Shutdown mode, RLAD is still attached to the VOUT
and VREF pins. Thus, these pins and the internal amplifier’s inverting input are all connected through RLAD
and the output is not High-Z (unlike the internal op
amp).
While RLAD contributes to the output noise, its effect is
small. Refer to Figure 2-12.
INPUT VOLTAGE AND PHASE
REVERSAL
The MCP6S91/2/3 amplifier family is designed with
CMOS input devices. It is designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-29 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
The maximum voltage that can be applied to the input
pins (CHx) is VSS – 0.3V to VDD + 0.3V. Voltages on
the inputs that exceed this absolute maximum rating
can cause excessive current to flow into or out of the
input pins. Current beyond ±2 mA can cause possible
reliability problems. Applications that exceed this rating
must be externally limited with an input resistor, as
shown in Figure 4-3.
 2004 Microchip Technology Inc.
DS21908A-page 19
MCP6S91/2/3
4.4
Rail-to-Rail VREF Input
The VREF input is intended to be driven by a lowimpedance voltage source. The source driving the
VREF pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy. The supply
voltage VSS and VDD usually meet this requirement.
RLAD presents a load at the VREF pin to the external
circuit (ZIN_REF ≈ (5 kΩ/G)||(6 pF)), which depends on
the gain. Any source driving the VREF pin must be
capable of driving a load as heavy as 0.16 kΩ||6 pF
(G = 32).
The absolute maximum voltages that can be applied to
the reference input pin (VREF) are VSS – 0.3V and
VDD + 0.3V. Voltages on the inputs that exceed this
absolute maximum rating can cause excessive current
to flow into or out of this pin. Current beyond ±2 mA can
cause possible reliability problems. Because an
external series resistor cannot be used (for low gain
error), the external circuit must ensure that VREF is
between VSS – 0.3V and VDD + 0.3V.
The VIVR_REF spec shows the region of normal
operation for the VREF pin (VSS to VDD). Staying within
this region ensures proper operation of the PGA and its
surrounding circuitry.
4.5
Shutdown Mode
These PGAs use a software shutdown command.
When the SPI interface sends a shutdown command,
the internal op amp is shut down and its output placed
in a High-Z state.
The resistive ladder is always connected between
VREF and VOUT; even in shutdown. This means that the
output resistance will be on the order of 5 kΩ, with a
path for output signals to appear at the input.
 2004 Microchip Technology Inc.
DS21908A-page 20
MCP6S91/2/3
5.0
DIGITAL FUNCTIONS
Chain Configuration”, covers applications using
multiple 16-bit words. SO goes low after CS goes
high; it has a push-pull output that does not go into a
high-Z state.
The MCP6S91/2/3 PGAs use a standard SPI
compatible serial interface to receive instructions from
a controller. This interface is configured to allow daisychaining with other SPI devices.
5.1
The MCP6S91/2/3 devices operate in SPI modes 0,0
and 1,1. In 0,0 mode, the clock idles in the low state
(Figure 5-1). In 1,1 mode, the clock idles in the high
state (Figure 5-2). In both modes, SI data is loaded into
the PGA on the rising edge of SCK, while SO data is
clocked out on the falling edge of SCK. In 0,0 mode, the
falling edge of CS also acts as the first falling edge of
SCK (see Figure 5-1). There must be multiples of 16
clocks (SCK) while CS is low or commands will abort
(see Section 5.3 “Daisy-Chain Configuration”).
SPI Timing
Chip Select (CS) toggles low to initiate communication with these devices. The first byte of each SI word
(two bytes long) is the instruction byte, which goes
into the Instruction register. The Instruction register
points the second byte to its destination. In a typical
application, CS is raised after one word (16 bits) to
implement the desired changes. Section 5.3 “Daisy-
2
3
4
5
6
7
8
9
bit 7
1
bit 0
CS
10
11
12
13
14
15
16
SCK
bit 0
bit 7
SI
Instruction Byte
Data Byte
SO
(first 16 bits out are always zeros)
FIGURE 5-1:
Serial Bus Sequence for the PGA; SPI™ 0,0 Mode (see Figure 1-4).
2
3
4
5
6
7
8
9
bit 7
1
bit 0
CS
10
11
12
13
14
15
16
SCK
Instruction Byte
bit 0
bit 7
SI
Data Byte
SO
(first 16 bits out are always zeros)
FIGURE 5-2:
Serial Bus Sequence for the PGA; SPI™ 1,1 Mode (see Figure 1-5).
 2004 Microchip Technology Inc.
DS21908A-page 21
MCP6S91/2/3
5.2
Registers
The analog functions are programmed through the SPI
interface using 16-bit words (see Figure 5-1 and
Figure 5-2). This data is sent to two of three 8-bit registers: Instruction register (Register 5-1), Gain register
(Register 5-2) and Channel register (Register 5-3).
There are no power-up defaults for these three
registers.
5.2.1
ENSURING VALID DATA IN THE
REGISTERS
A 0.1 µF bypass capacitor mounted as close as
possible to the VDD pin provides additional transient
immunity.
5.2.2
After power up, the registers contain random data that
must be initialized. Sending valid gain and channel
selection commands to the internal registers puts valid
data into those registers. Also, the internal state
machine starts in an arbitrary state. Toggling the Chip
Select pin (CS) from high to low, then back to high
again, puts the internal state machine in a known, valid
condition (this can be done by entering any valid
command).
REGISTER 5-1:
After power-up, and when the power supply voltage
dips below the minimum valid VDD (VDD_VAL), the internal register data and state machine may need to be
reset. This is accomplished as described before. Use
an external system supervisor to detect these events
so that the microcontroller will reset the PGA state and
registers.
INSTRUCTION REGISTER
The Instruction register has 3 command bits and 1 indirect address bit; see Register 5-1. The command bits
include a NOP (000) to support daisy-chaining (see
Section 5.3 “Daisy-Chain Configuration”); the other
NOP commands shown should not be used (they are
reserved for future use). The device is brought out of
Shutdown mode when a valid command, other than
NOP or Shutdown, is sent and CS is raised.
INSTRUCTION REGISTER
W-0
W-0
W-0
U-x
U-x
U-x
U-x
W-0
M2
M1
M0
—
—
—
—
A0
bit 7
bit 0
bit 7-5
M2-M0: Command bits
000 = NOP (Note 1)
001 = PGA enters Shutdown mode as soon as a full 16-bit word is sent and CS is raised.
(Notes 1 and 2)
010 = Write to register.
011 = NOP (reserved for future use) (Note 1)
1XX = NOP (reserved for future use) (Note 1)
bit 4-1
Unimplemented: Read as ‘0’ (reserved for future use)
bit 0
A0: Indirect Address bit
1 = Addresses the Channel register
0 = Addresses the Gain register
Note 1:
2:
All other bits in the 16-bit word (including A0) are “don’t cares.”
The device exits Shutdown mode when a valid command (other than NOP or
Shutdown) is sent and CS is raised; that valid command will be executed.
Shutdown does not toggle.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2004 Microchip Technology Inc.
x = Bit is unknown
DS21908A-page 22
MCP6S91/2/3
5.2.3
SETTING THE GAIN
The amplifier can be programmed to produce binary
and decimal gain settings between +1 V/V and +32 V/V.
Register 5-2 shows the details. At the same time, different compensation capacitors are selected to optimize
the bandwidth vs. slew rate trade-off (see Table 4-1).
REGISTER 5-2:
GAIN REGISTER
U-x
U-x
U-x
U-x
U-x
W-0
W-0
W-0
—
—
—
—
—
G2
G1
G0
bit 7
bit 0
bit 7-3
Unimplemented: Read as ‘0’ (reserved for future use)
bit 2-0
G2-G0: Gain Select bits
000 = Gain of +1
001 = Gain of +2
010 = Gain of +4
011 = Gain of +5
100 = Gain of +8
101 = Gain of +10
110 = Gain of +16
111 = Gain of +32
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2004 Microchip Technology Inc.
x = Bit is unknown
DS21908A-page 23
MCP6S91/2/3
5.2.4
CHANGING THE CHANNEL
If the Instruction register is programmed to address the
Channel register, the multiplexed inputs of the
MCP6S92 and MCP6S93 can be changed using
Register 5-3.
REGISTER 5-3:
CHANNEL REGISTER
U-x
U-x
U-x
U-x
U-x
U-x
U-x
W-0
—
—
—
—
—
—
—
C0
bit 7
bit 0
bit 7-1
Unimplemented: Read as ‘0’ (reserved for future use)
bit 0
C0: Channel Select bit
0=
1=
MCP6S91
CH0
CH0
MCP6S92
CH0
CH1
MCP6S93
CH0
CH1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2004 Microchip Technology Inc.
x = Bit is unknown
DS21908A-page 24
MCP6S91/2/3
5.2.5
SHUTDOWN COMMAND
The example in Figure 5-3 shows a daisy-chain
configuration with two devices, although any number of
devices can be configured this way. The MCP6S91 and
MCP6S92 can only be used at the far end of the daisychain, because they do not have a serial data out (SO)
pin. As shown in Figure 5-4 and Figure 5-5, both SI and
SO data are sent in 16-bit (2 byte) words. These
devices abort any command that is not a multiple of 16
bits.
The software shutdown command allows the user to
put the amplifier into a low-power mode (see
Register 5-1). In this Shutdown mode, most pins are
high-impedance (Section 4.5 “Shutdown Mode” and
Section 5.1 “SPI Timing” cover the exceptions at pins
VREF, VOUT and SO).
Once the PGA has entered Shutdown mode, it will
remain in this mode until either a valid command is sent
to the device (other than NOP or Shutdown) or the
device is powered down and back up again. The
internal registers maintain their values while in
shutdown.
When using the daisy-chain configuration, the maximum clock speed possible is reduced to ≈ 5.8 MHz due
to the SO pin’s propagation delay (see Electrical
Specifications).
The internal SPI shift register is automatically loaded
with zeros whenever CS goes high (a command is
executed). Thus, the first 16-bits out of the SO pin after
the CS line goes low are always zeros. This means that
the first command loaded into the next device in the
daisy-chain is a NOP. This feature makes it possible to
send shorter command and data byte strings when the
farthest devices do not need to change. For example, if
there were three devices on the chain, and only the
middle device needed changing, then only 32 bytes of
data need to be transmitted (for the first and middle
devices). The last device on the chain would receive a
NOP when the CS pin is raised to execute the
command.
Once brought out of Shutdown mode, the part returns
to its previous state (see Section 5.2.1 “Ensuring
Valid Data in the Registers” for exceptions to this
rule). This makes it possible to bring the device out of
shutdown mode using one command; send a command to select the current channel (or gain) and the
device will exit shutdown with the same state that
existed before shutdown.
5.3
Daisy-Chain Configuration
Multiple MCP6S91/2/3 devices can be connected in a
daisy-chain configuration by connecting the SO pin
from one device to the SI pin on the next device and
using common SCK and CS lines (Figure 5-3). This
approach reduces PCB layout complexity and uses
fewer PICmicro® microcontroller I/O pins.
CS
SCK
SO
PICmicro®
Microcontroller
CS
SCK
SO
SI
Device 1
1. Set CS low.
2. Clock out the instruction and data
for device 2 (16 clocks) to Device 1.
3. Device 1 automatically clocks out all
zeros (first 16 clocks) to Device 2.
4. Clock out the instruction and data
for Device 1 (16 clocks) to Device 1.
5. Device 1 automatically shifts data
from Device 1 to Device 2 (16 clocks).
6. Raise CS.
FIGURE 5-3:
CS
SCK
SO
SI
Device 2
Device 1
Device 2
00100000 00000000
00000000 00000000
Device 1
Device 2
01000001 00000111
00100000 00000000
Daisy-Chain Configuration.
 2004 Microchip Technology Inc.
DS21908A-page 25
MCP6S91/2/3
CS
1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
SCK
Instruction Byte
for Device 2
Instruction Byte
for Device 1
Data Byte
for Device 2
bit 0
bit 0
bit 7
bit 0
bit 7
bit 0
bit 7
bit 7
SI
Data Byte
for Device 1
Instruction Byte
for Device 2
FIGURE 5-4:
bit 0
bit 0
bit 7
(first 16 bits out are always zeros)
bit 7
SO
Data Byte
for Device 2
Serial Bus Sequence for Daisy-Chain Configuration; SPI™ 0,0 Mode.
CS
1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
SCK
Instruction Byte
for Device 2
Data Byte
for Device 2
Instruction Byte
for Device 1
bit 0
bit 0
bit 7
bit 0
bit 7
bit 0
bit 7
bit 7
SI
Data Byte
for Device 1
Instruction Byte
for Device 2
FIGURE 5-5:
bit 0
bit 0
bit 7
(first 16 bits out are always zeros)
bit 7
SO
Data Byte
for Device 2
Serial Bus Sequence for Daisy-Chain Configuration; SPI™ 1,1 Mode.
 2004 Microchip Technology Inc.
DS21908A-page 26
MCP6S91/2/3
APPLICATIONS INFORMATION
6.1
Changing External Reference
Voltage
Figure 6-1 shows a MCP6S91 with the VREF pin at
2.5V and VDD = 5.0V. This allows the PGA to amplify
signals centered on 2.5V, instead of ground-referenced
signals. The voltage reference MCP1525 is buffered by
a MCP6021, which gives a low output impedance
reference voltage from DC to high frequencies. The
source driving the VREF pin should have an output
impedance less than 0.1Ω to maintain reasonable gain
accuracy.
VDD
VIN
MCP6S91
VREF
VOUT
VDD
MCP1525
2.5V
REF
VDD
RISO
VIN
FIGURE 6-2:
Capacitive Loads.
1,000
100
10
10p
10
FIGURE 6-3:
6.2
Capacitive Load and Stability
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6S91/2/3 family of
PGAs (Figure 2-26 and Figure 2-28). As the load
capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
When driving large capacitive loads with these PGAs
(i.e., > 60 pF), a small series resistor at the output
(RISO in Figure 6-2) improves the internal amplifier’s
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
 2004 Microchip Technology Inc.
PGA Circuit for Large
Figure 6-3 gives recommended RISO values for
different capacitive loads. After selecting RISO for your
circuit, double-check the resulting frequency response
peaking and step response overshoot on the bench.
Modify RISO’s value until the response is reasonable at
all gains.
1µF MCP6021
FIGURE 6-1:
PGA with Different External
Reference Voltage.
VOUT
MCP6S9X
CL
Recommended R ISO (Ω)
6.0
6.3
100
1,000
100p
1n
Load Capacitance (F)
10,000
10n
Recommended RISO.
Layout Considerations
Good PC board layout techniques will help achieve the
performance shown in the Electrical Characteristics
and Typical Performance Curves. It will also help
minimize Electromagnetic Compatibility (EMC) issues.
6.3.1
COMPONENT PLACEMENT
Separate different circuit functions: digital from analog,
low-speed from high-speed, and low-power from highpower. This will reduce crosstalk.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
DS21908A-page 27
MCP6S91/2/3
6.3.2
SUPPLY BYPASS
6.3.4
SIGNAL COUPLING
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the VDD pin. It must connect directly to the
ground plane. A multi-layer ceramic chip capacitor, or
high-frequency equivalent, works best.
The input pins of the MCP6S91/2/3 family of PGAs are
high-impedance. This makes them especially susceptible to capacitively-coupled noise. Using a ground plane
helps reduce this problem.
Use a bulk bypass capacitor (2.2 µF to 10 µF) within
100 mm of the VDD pin. It needs to connect to the
ground plane. A multi-layer ceramic chip capacitor,
tantalum or high-frequency equivalent, works best.
This capacitor may be shared with other nearby analog
parts.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
6.3.3
INPUT SOURCE IMPEDANCE
The sources driving the inputs of the PGAs need to
have reasonably low source impedance at higher
frequencies. Figure 6-4 shows how the external source
impedance (RS), PGA package pin capacitance (CP1)
and PGA package pin-to-pin capacitance (CP2) form a
positive feedback voltage divider network. Feedback to
the selected channel may cause frequency response
peaking and step response overshoot and ringing.
Feedback to an unselected channel will produce
crosstalk.
CP2
RS
VIN
MCP6S9X
VOUT
CP1
FIGURE 6-4:
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
6.3.5
HIGH-FREQUENCY ISSUES
Because the MCP6S91/2/3 PGAs’ frequency response
reaches unity gain at 64 MHz when G = 16 and 32, it is
important to use good PCB layout techniques. Any
parasitic-coupling at high-frequency might cause
undesired peaking. Filtering high-frequency signals
(i.e., fast edge rates) can help. To minimize highfrequency problems:
•
•
•
•
•
Use complete ground and power planes
Use HF, surface-mount components
Provide clean supply voltages and bypassing
Keep traces short and straight
Try a linear power supply (e.g., a LDO)
Positive Feedback Path.
Figure 2-6 shows the crosstalk (referred to input) that
results when a hostile signal is connected to CH1, input
CH0 is selected and RS is connected from CH0 to
GND. A gain of +32 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing RS
increases the crosstalk as expected. At a source
impedance of 10 kΩ, there is noticeable peaking in the
response; this is due to positive feedback.
Most designs should use a source resistance (RS) no
larger than 10 kΩ. Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 kΩ
must be used, place a capacitor in parallel to CP1 to
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk) peaking, yet small enough to allow a reasonable signal
bandwidth.
 2004 Microchip Technology Inc.
DS21908A-page 28
MCP6S91/2/3
6.4
Typical Applications
VIN
6.4.1
GAIN RANGING
MCP6291
Figure 6-5 shows a circuit that measures the current IX.
The circuit’s performance benefits from changing the
gain on the PGA. Just as a hand-held multimeter uses
different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the PGA’s output
is less than at its input (by up to 30 dB).
MCP6S9X
IX
VOUT
RS
VOUT
MCP6S91
1.11 kΩ
FIGURE 6-7:
Range.
6.4.3
PGA with Lower Gain
EXTENDED GAIN RANGE PGA
Figure 6-8 gives a +1 V/V to +1024 V/V gain range,
which is much greater than the range for a single PGA
(+1 V/V to +32 V/V). The first PGA provides input
multiplexing capability, while the second PGA only
needs one input. These devices can be daisy-chained
(Section 5.3 “Daisy-Chain Configuration”).
FIGURE 6-5:
Wide Dynamic Range
Current Measurement Circuit.
6.4.2
10.0 kΩ
SHIFTED GAIN RANGE PGA
Figure 6-6 shows a circuit using a MCP6291 at a gain
of +10 in front of a MCP6S91. This shifts the overall
gain range to +10 V/V to +320 V/V (from +1 V/V to
+32 V/V).
VIN
MCP6S92
MCP6S91
VOUT
VIN
MCP6291
MCP6S91
VOUT
FIGURE 6-8:
Range.
6.4.4
MULTIPLE SENSOR AMPLIFIER
The multiple-channel PGAs (MCP6S92 and MCP6S93)
allow the user to select which sensor appears on the
output (see Figure 6-9). These devices can also change
the gain to optimize performance for each sensor.
10.0 kΩ
1.11 kΩ
FIGURE 6-6:
Range.
PGA with Extended Gain
PGA with Higher Gain
It is also easy to shift the gain range to lower gains (see
Figure 6-7). The MCP6291 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +3.2 V/V (from +1 V/V to +32 V/V).
 2004 Microchip Technology Inc.
Sensor # 0
MCP6S93
VOUT
Sensor # 1
FIGURE 6-9:
Inputs.
PGA with Multiple Sensor
DS21908A-page 29
MCP6S91/2/3
6.4.5
6.4.7
EXPANDED INPUT PGA
Figure 6-10 shows cascaded MCP6S28 and
MCP6S92s PGAs that provide up to 9 input channels.
Obviously, Sensors #1-8 have a high total gain range
available, as explained in Section 6.4.3 “Extended
Gain Range PGA”. These devices can be daisychained (Section 5.3 “Daisy-Chain Configuration”).
ADC DRIVER
This family of PGAs is well suited for driving Analog-toDigital Converters (ADCs). The binary gains (1, 2, 4, 8,
16 and 32) effectively add five more bits to the input
range (see Figure 6-12). This works well for applications needing relative accuracy more than absolute
accuracy (e.g., power monitoring).
Low-pass
Filter
Sensor
#0
MCP6S92
Sensors
# 1-8
VOUT
VIN
MCP6S92
MCP6S28
FIGURE 6-12:
FIGURE 6-10:
6.4.6
PGA with Expanded Inputs.
PICmicro® MCU WITH EXPANDED
INPUT CAPABILITY
Figure 6-11 shows a MCP6S93 driving an analog input
to a PICmicro microcontroller. This greatly expands the
input capacity of the microcontroller, while adding the
ability to select the appropriate gain for each source.
VIN
PICmicro®
Microcontroller
MCP6S93
MCP3201 3
12-bit
ADC
OUT
PGA as an ADC driver.
At low gains, the ADC’s Signal-to-Noise Ratio (SNR)
will dominate since the PGA’s input noise voltage
density is so low (10 nV/√Hz @ 10 kHz, typ.). At high
gains, the PGA’s noise will dominate the SNR, but it is
low enough to support most applications. These PGAs
add the flexibility of selecting the best gain for an
application.
The low-pass filter in the block diagram reduces the
integrated noise at the MCP6S92’s output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip’s FilterLab® software, available at
www.microchip.com.
SPI™
FIGURE 6-11:
Expanded Input for a
PICmicro® Microcontroller.
 2004 Microchip Technology Inc.
DS21908A-page 30
MCP6S91/2/3
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
8-Lead PDIP (300 mil) (MCP6S91, MCP6S92)
XXXXXXXX
XXXXXNNN
YYWW
MCP6S91
E/P256
0424
8-Lead SOIC (150 mil) (MCP6S91, MCP6S92)
XXXXXXXX
XXXXYYWW
NNN
10-Lead MSOP (MCP6S93)
XXXXX
YWWNNN
Note:
*
Example:
6S91E
424256
XXXXX
YWWNNN
XX...X
YY
WW
NNN
Example:
MCP6S91
E/SN0424
256
8-Lead MSOP (MCP6S91, MCP6S92)
Legend:
Example:
Example:
6S93E
424256
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office.
 2004 Microchip Technology Inc.
DS21908A-page 31
MCP6S91/2/3
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
p
eB
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
§
A
A2
A1
E
E1
D
L
c
B1
B
eB
α
β
MIN
.140
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
5
INCHES*
NOM
MAX
8
.100
.155
.130
.170
.145
.313
.250
.373
.130
.012
.058
.018
.370
10
10
.325
.260
.385
.135
.015
.070
.022
.430
15
15
MILLIMETERS
NOM
8
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
9.14
9.46
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
MAX
4.32
3.68
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
 2004 Microchip Technology Inc.
DS21908A-page 32
MCP6S91/2/3
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
α
h
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.053
.052
.004
.228
.146
.189
.010
.019
0
.008
.013
0
0
A1
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
.069
.061
.010
.244
.157
.197
.020
.030
8
.010
.020
15
15
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MIN
MAX
1.75
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
0.25
0.51
15
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
 2004 Microchip Technology Inc.
DS21908A-page 33
MCP6S91/2/3
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
p
E1
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Number of Pins
Pitch
Overall Height
MILLIMETERS*
INCHES
Units
Dimension Limits
n
p
MAX
NOM
MIN
MIN
NOM
0.65
.026
.044
A
1.18
.038
0.76
0.86
.006
0.05
0.97
.193
.200
4.67
4.90
.5.08
.114
.118
.114
.118
.122
2.90
3.00
3.10
.122
2.90
3.00
L
.016
3.10
.022
.028
0.40
0.55
.035
Foot Angle
F
φ
0.70
.037
.039
0.90
0.95
1.00
Lead Thickness
c
6
0
.004
.006
.008
0.10
0.15
0.20
Lead Width
Mold Draft Angle Top
B
α
.010
.012
.016
0.25
0.30
0.40
Mold Draft Angle Bottom
β
Molded Package Thickness
A2
.030
Standoff
A1
.002
E
.184
Molded Package Width
E1
Overall Length
D
Foot Length
Footprint (Reference)
§
Overall Width
MAX
8
8
.034
0
0.15
6
7
7
7
7
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Drawing No. C04-111
 2004 Microchip Technology Inc.
DS21908A-page 34
MCP6S91/2/3
10-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A
φ
c
A2
A1
L
(F)
β
L1
Units
Dimension Limits
n
p
MIN
INCHES
NOM
10
.020 TYP
.033
.193 BSC
.118 BSC
.118 BSC
.024
.037 REF
.009
-
MAX
MILLIMETERS*
NOM
10
0.50 TYP.
0.85
0.75
0.00
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.40
0.95 REF
0°
0.08
0.15
0.23
5°
5°
MIN
Number of Pins
Pitch
.043
Overall Height
A
Molded Package Thickness
.037
A2
.030
Standoff
.006
A1
.000
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
.031
L
.016
Footprint
F
φ
0°
8°
Foot Angle
c
.009
Lead Thickness
.003
.012
Lead Width
B
.006
α
5°
15°
Mold Draft Angle Top
β
5°
15°
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.30
15°
15°
JEDEC Equivalent: MO-187
Drawing No. C04-021
 2004 Microchip Technology Inc.
DS21908A-page 35
MCP6S91/2/3
NOTES:
 2004 Microchip Technology Inc.
DS21908A-page 36
MCP6S91/2/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-X
/XX
Device
Temperature
Range
Package
Device:
MCP6S91: One-channel PGA
MCP6S91T: One-channel PGA
(Tape and Reel for SOIC and MSOP-8)
MCP6S92: Two-channel PGA
MCP6S92T: Two-channel PGA
(Tape and Reel for SOIC and MSOP-8)
MCP6S93: Two-channel PGA
MCP6S93T: Two-channel PGA
(Tape and Reel for MSOP-10)
Examples:
a)
MCP6S91-E/P:
b)
MCP6S91-E/SN:
c)
MCP6S91-E/MS:
a)
MCP6S92-E/MS:
b)
Two-channel PGA,
MSOP-8 package.
MCP6S92T-E/MS: Tape and Reel,
Two-channel PGA,
MSOP-8 package.
a)
MCP6S93-E/UN:
b)
Temperature Range:
E
= -40°C to +125°C
Package:
MS
P
SN
UN
=
=
=
=
One-channel PGA,
PDIP package.
One-channel PGA,
SOIC package.
One-channel PGA,
MSOP package.
Two-channel PGA,
MSOP-10 package.
MCP6S93T-E/UN: Tape and Reel,
Two-channel PGA,
MSOP-10 package.
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead
Plastic SOIC (150 mil Body), 8-lead
Plastic Micro Small Outline (MSOP), 10-lead
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2004 Microchip Technology Inc.
DS21908A-page 37
MCP6S91/2/3
NOTES:
DS21908A-page 38
 2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21908A-page 39
 2004 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http:\\support.microchip.com
Web Address:
www.microchip.com
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
India - Bangalore
Tel: 91-80-2229-0061
Fax: 91-80-2229-0062
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
India - New Delhi
Tel: 91-11-5160-8632
Fax: 91-11-5160-8632
Austria - Weis
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark - Ballerup
Tel: 45-4420-9895
Fax: 45-4420-9910
China - Chengdu
Tel: 86-28-8676-6200
Fax: 86-28-8676-6599
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Tel: 81-45-471- 6166
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Tel: 33-1-69-53-63-20
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Tel: 86-755-8203-2660
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Tel: 886-2-2500-6610
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Italy - Milan
Tel: 39-0331-742611
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Netherlands - Drunen
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Canada
Tel: 905-673-0699
Fax: 905-673-6509
09/27/04
DS21908A-page 40
 2004 Microchip Technology Inc.