STMICROELECTRONICS 54AC164245

54AC164245
Rad-hard 16-bit transceiver, 3.3 V to 5 V bidirectional level shifter
Datasheet − production data
Features
■
Fully compatible with 54ACS164245
■
Dual supply bidirectional level shifter
■
Extended voltage range from 2.3 V to 5.5 V
■
Separated enable pin for 3-state output
■
Schmidt-triggered I/Os: 100 mV hysteresis
■
Internal 26 Ω limiting resistor on each I/O
■
High speed: Tpd = 8 ns maximum
■
Bus hold
■
Fail safe
■
Cold spare
■
Hermetic package
■
100 krad (Si) at any Mil1019 dose rate
■
SEL immune to 110MeV.cm2/mg LET ions
■
RHA QML-V qualified
Ceramic Flat-48
The upper metallic lid is not electrically connected to
any pins, nor to the IC die inside the package
All pins have cold spare buffers to change them to
high impedance when VDD is tied to ground.
Description
The 54AC164245 is a rad-hard advanced highspeed CMOS, Schmitt trigger 16-bit bidirectional
multi-purpose transceiver with 3-state outputs and
cold sparing.
Designed for use as an interface between a 5 V
bus and a 3.3 V bus in mixed 5 V/3.3 V supply
systems, it achieves high-speed operation while
maintaining the CMOS low-power dissipation.
Table 1.
This IC is intended for two-way asynchronous
communication between the data buses and the
direction of the data transmission is determined
by the nDIR inputs.
The A port interfaces with the 3.3 V bus but can
also operate at 2.3 V. The B port operates with the
5 V bus.
Device summary
Reference
SMD pin
Quality
level
RHRAC164245K1
-
Engineering
model
Package
Lead
finish
Gold
Flat-48
RHRAC164245K01V
Note:
5962R9858008VYC
Mass
QMLVFlight
EPPL
-
-55 °C
to +125 °C
1.50 g
Gold
Temp range
Target
Contact your ST sales office for information on the specific conditions for products in die form.
April 2012
This is information on a product in full production.
Doc ID 18093 Rev 2
1/22
www.st.com
22
Functional description
54AC164245
1
Functional description
Figure 1.
Logic diagram
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6PORT
6PORT
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6PORT
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Table 2.
2/22
Function table
Enable, OEx
Direction, DIRx
Operation
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Doc ID 18093 Rev 2
54AC164245
1.1
Functional description
Cold spare
The 54AC164245 features a cold spare input and output buffers. In high reliability
applications, cold sparing enables a redundant device to be tied to the data bus with its
power supply at 0 V (VDD = VSS, VDD - VSS = 0 V) without affecting the bus signals or
injecting current from the I/Os to the power supplies. Cold sparing also allows to keep
unpowered redundant devices so that they can be switched on only when required. Power
consumption is therefore reduced by switching off the redundant circuit. This has no impact
on the application. Cold spare is achieved by implementing a high impedance between I/Os
and VDD. The ESD protection is ensured through a non-conventional dedicated structure.
1.2
Power-up
During power up, all outputs are forced to high impedance. The high-impedance state is
maintained approximately until VDD is high, thus avoiding any transient and erroneous
signals during power-up.
1.3
Pin connections
Figure 2.
Pin connections
!-V
Doc ID 18093 Rev 2
3/22
Functional description
Table 3.
54AC164245
Pin descriptions
Pin n°
4/22
Symbol
Name and function
1
DIR1
Direction control inputs
2, 3, 5, 6, 8, 9, 11, 12
1B1 to 1B8
Side B inputs or 3-state outputs (5 V port)
4,10, 15, 21, 28, 34, 39, 45
VSS
Reference voltage to ground
7, 18
VDD1
Supply voltage (5 V)
13, 14, 16, 17, 19, 20, 22, 23
2B1 to 2B8
Side B inputs or 3-state outputs (5 V port)
24
DIR2
Direction control inputs
25
nG2
Output enable inputs (active low)
31, 42
VDD2
Supply voltage (3.3 V)
47, 46, 44, 43, 41, 40, 38, 37
1A1 to 1A8
Side A inputs or 3-state outputs (3.3 V port)
36, 35, 33, 32, 30, 29, 27, 26
2A1 to 2A8
Side A inputs or 3-state outputs (3.3 V port)
48
nG1
Output enable inputs (active low)
Doc ID 18093 Rev 2
54AC164245
2
Absolute maximum ratings and operating conditions
Absolute maximum ratings and operating conditions
Absolute maximum ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Symbol
Absolute maximum ratings (1) (2) (3)
Parameter
VDD1
5 V supply voltage
VDD2
3 V supply voltage
(4)
Value
Unit
-0.3 to +6.0
V
-0.3 to +6.0
V
VIA
DC input voltage range port A
-0.3 to VDD1+0.3 V
V
VIB
DC input voltage range port B
-0.3 to VDD1+0.3 V
V
VOA
DC output voltage range port A
-0.3 to VDD1+0.3 V
V
VOB
DC output voltage range port B
-0.3 to VDD1+0.3 V
V
IIA
DC input currents port A, anyone input
± 10
mA
IIB
DC input currents port B, anyone input
± 10
mA
Tstg
Storage temperature range
-65 to +150
°C
TL
Lead temperature (10 sec)
300
°C
TJ
Junction temperature range
175
°C
TBD
°C/W
TBD
°C/W
2
kV
Rthja
Thermal resistance junction to ambient
Flat package, 48 pins
Rthjc
Thermal resistance junction to case(5)
Flat package, 48 pins
ESD
HBM: human body model(6)
(5)
1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended
operation at the maximum levels may degrade performance and affect reliability.
2. Unless otherwise noted, all voltages are referenced to VSS.
3. The limits for the parameters specified herein shall apply over the full specified VDD range and case
temperature range of -55°C to +125°C.
4. VDD1 (5 V) may remain disconnected.
5. Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
6. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
Doc ID 18093 Rev 2
5/22
Absolute maximum ratings and operating conditions
Table 5.
Operating conditions (1)
Symbol
Parameter
54AC164245
Value
Unit
VDD1
Supply voltage
4.5 to 5.5 or 2.3 to 3.6
V
VDD2
Supply voltage
2.3 to 3.6 or 4.5 to 5.5
V
VI
Input voltage
0 to VDD1
V
VO
Output voltage
0 to VDD1
V
Top
Operating temperature
-55 to +125
°C
0 to 8
ns / V
dt / dv
Input rise and fall time VCC = 3.0, 4.5 or 5.5
(2)
1. Unless otherwise noted, all voltages are referenced to VSS.
2. Derate system propagation delays by difference in rise time to switch point for tr or tf > 1 ns/V.
6/22
Doc ID 18093 Rev 2
54AC164245
3
Electrical characteristics
Electrical characteristics
Top = -55°C to +125°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 2.7 V to 3.6 V, unless otherwise
specified.
Table 6.
DC specifications (1)
Symbol
Parameter
Test condition (VDD) (2)
3.3 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
0.7 VDD2
5.0 V
VDD1 = 4.5 and 5.5 V
VDD2 = 4.5 and 5.5 V
0.7 VDD2
3.3 V
VDD2 = 2.7 and 3.6 V
VDD1 = 2.7 and 3.6 V
0.7 VDD1
5.0 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
0.7 VDD1
3.3 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
0.3 VDD2
5.0 V
VDD1 = 4.5 and 5.5 V
VDD2 = 4.5 and 5.5 V
0.3 VDD2
3.3 V
VDD1 = 2.7 and 3.6 V
VDD2 = 2.7 and 3.6 V
0.3 VDD1
5.0 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
0.3 VDD1
3.3 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
0.4
5.0 V
VDD1 = 4.5 and 5.5 V
VDD2 = 4.5 and 5.5 V
0.6
3.3 V
VDD1 = 2.7 and 3.6 V
VDD2 = 2.7 and 3.6 V
0.4
5.0 V
VDD1 = 4.5 and 5.5 V
VDD2 = 2.7 and 3.6 V
0.6
3.3 V
VDD1 = 5.5 V
VDD2 = 3.6 V
3
5.0 V
VDD1 = 5.5 V
VDD2 = 5.5 V
3
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
3
5.0 V
VDD1 = 5.5 V
VDD2 = 3.6 V
3
Schmitt trigger positive going
threshold port A
VT+
Schmitt trigger positive going
threshold port B
Schmitt trigger positive going
threshold port A
VTSchmitt trigger positive going
threshold port B
Schmitt trigger range of
hysteresis port A
VH
Schmitt trigger range of
hysteresis port B
Input current high port A (for
input under test VI = VDD2 other
inputs, VI = VDD2 or VSS)
IIH
Input current high port B (for
input under test VI = VDD1 other
inputs, VI = VDD1 or VSS)
Limits
Port
voltage
Unit
Min.
Doc ID 18093 Rev 2
Max.
V
V
V
µA
7/22
Electrical characteristics
Table 6.
Symbol
54AC164245
DC specifications (1) (continued)
Test condition (VDD) (2)
3.3 V
VDD1 = 5.5 V
VDD2 = 3.6 V
-1
5V
VDD1 = 5.5 V
VDD2 = 5.5 V
-1
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
-1
5V
VDD1 = 5.5 V
VDD2 = 3.6 V
-1
Input current cold spare mode
port A = port B = 5.5 V = VI
DIRn = 5.5 V, OEn = 5.5 V
VDD1 = 0 V
-1
5
Input current cold spare mode
port A = port B = 5.5 V = VI
DIRn = 0V, OEn = 5.5 V
VDD1 = 0 V
-1
5
Input current low port A (for
input under test VI =VSS other
inputs, VI = VDD2 or VSS
IIL
Input current low port B (for
input under test VI =VSS other
inputs, VI = VDD1 or VSS
ICS
Max.
µA
µA
VDD1 = 0 V
-1
5
Input current cold spare mode
port A = port B = 5.5 V = VI
DIRn = 0 V, OEn = 0 V
VDD1 = 0 V
-1
5
3.3 V
VDD1 = 4.5 V
VDD2 = 2.7 V
0.5
5V
VDD1 = 4.5 V
VDD2 = 4.5 V
0.4
Low level output voltage
Port B, IOL = 8 mA for all inputs
affecting output under test,
VI = VDD1 or VSS
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
0.5
5V
VDD1 = 4.5 V
VDD2 = 2.7 V
0.4
Low level output voltage
3.3 V
VDD1 = 4.5 V
VDD2 = 2.7 V
0.2
5V
VDD1 = 4.5 V
VDD2 = 4.5 V
0.2
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
0.2
5V
VDD1 = 4.5 V
VDD2 = 2.7 V
0.2
VOL1
Port A, IOL = 100 µA for all
inputs affecting output under
test, VI = VDD2 or VSS
Low level output voltage
Port B, IOL = 100 µA For all
inputs affecting output under
test, VI =VDD1 or VSS
8/22
Unit
Min.
Input current cold spare mode
port A = port B = 5.5 V = VI
DIRn = 5.5 V, OEn = 0 V
Low level output voltage
Port A, IOL = 8 mA for all inputs
affecting output under test,
VI = VDD2 or VSS
VOL2
Limits
Port
voltage
Parameter
V
V
Doc ID 18093 Rev 2
54AC164245
Table 6.
Symbol
Electrical characteristics
DC specifications (1) (continued)
Limits
Port
voltage
Test condition (VDD) (2)
High level output voltage port A,
IOH = -8 mA for all inputs
affecting output under test,
VI = VDD2 or VSS
3.3 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VDD2-0.9
5V
VDD1 = 4.5 V
VDD2 = 4.5 V
VDD2-0.7
High level output voltage port B,
IOH = -8 mA for all inputs
affecting output under test,
VI = VDD1 or VSS
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
VDD1-0.9
5V
VDD1 = 4.5 V
VDD2 = 2.7 V
VDD1-0.7
High level output voltage
port A, IOH = - 100 µA for all
inputs affecting output under
test, VI = VDD2 or VSS
3.3 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VDD2-0.2
5V
VDD1 = 4.5 V
VDD2 = 4.5 V
VDD2-0.2
High level output voltage
port B, IOH = - 100 µA for all
inputs affecting output under
test, VI = VDD1 or VSS
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
VDD1-0.2
5V
VDD1 = 4.5 V
VDD2 = 2.7 V
VDD1-0.2
3.3 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOL = 0.5 V
8.0
5V
VDD1 = 4.5 V
VDD2 = 4.5 V
VOL = 0.4 V
8.0
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
VOL = 0.5 V
8.0
5V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOL = 0.4 V
8.0
Parameter
VOH1
VOH2
Output current (sink)
port A, VI = VSS
IOL (3)
Output current (sink)
port B, VI = VSS
Unit
Min.
Doc ID 18093 Rev 2
Max.
V
mA
9/22
Electrical characteristics
Table 6.
Symbol
54AC164245
DC specifications (1) (continued)
Parameter
Test condition (VDD) (2)
3.3 V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOH = VDD2 -0.9 V
-8.0
5V
VDD1 = 4.5 V
VDD2 = 4.5 V
VOH = VDD2 -0.7 V
-8.0
3.3 V
VDD1 = 2.7 V
VDD2 = 2.7 V
VOH = VDD2 -0.9 V
-8.0
5V
VDD1 = 4.5 V
VDD2 = 2.7 V
VOH = VDD2 -0.7 V
-8.0
Output current (source) port A,
VI = VDD2 or VSS
IOH (4)
Output current (source) port B,
VI = VDD2 or VSS
IOZH
IOZL
Three-state output leakage
current high port A, for input
under test, VI =VDD2 other
inputs, VO =VDD2 VI =VDD2 or
VSS
Three-state output leakage
current high port B, for input
under test, VI =VDD1 other
inputs, VO = VDD1 VI = VDD1 or
VSS
Three-state output leakage
current low port A, for input
under test, VI = VSS other
inputs, VO = VSS
VI = VDD2 or VSS
Three-state output leakage
current low port B, for input
under test, VI = VSS other
inputs, VO = VSS VI = VDD1 or
VSS
Short circuit output current port
A, VO = VDD2 or VSS
IOS
10/22
Unit
Min.
Max.
mA
VDD1 = 5.5 V
VDD2 = 3.6 V
3.0
VDD1 = 5.5 V
VDD2 = 5.5 V
3.0
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
3.0
5V
VDD1 = 5.5 V
VDD2 = 3.6 V
3.0
3.3 V
VDD1 = 5.5 V
VDD2 = 3.6 V
-1.0
5V
VDD1 = 5.5 V
VDD2 = 5.5 V
-1.0
3.3 V
VDD1 = 3.6 V
VDD2 = 3.6 V
-1.0
5V
VDD1 = 5.5 V
VDD2 = 3.6 V
-1.0
3.3 V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
-100
100
5V
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
-200
200
3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.6 V
-100
100
5V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
-200
200
3.3 V
(3) (4)
Short circuit output current
port B, VO = VDD1 or VSS
Limits
Port
voltage
Doc ID 18093 Rev 2
µA
µA
mA
54AC164245
Table 6.
Symbol
Electrical characteristics
DC specifications (1) (continued)
Parameter
Test condition (VDD) (2)
3.3 V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
1.5
5V
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
2.0
3.3 V
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.6 V
1.5
5V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
2.0
VDD1 = 5.5 V
VDD2 = 5.5 V
at 25°C
10
VDD1 = 5.5 V
VDD2 = 5.5 V
at -55 to +125°C
100
Power dissipation, port A,
CL = 50 pF per switching output
PD
Limits
Port
voltage
(3) (5)
(6)
Power dissipation, port B,
CL = 50 pF per switching output
Quiescent supply current port
A, VI = VDD2 or VSS
Unit
Min.
Max.
mW/
MHz
5V
IDDQ
µA
Quiescent supply current port
B, VI = VDD1 or VSS
VDD1 = 5.5 V
VDD2 = 5.5 V
at 25°C
10
VDD1 = 5.5 V
VDD2 = 5.5 V
at -55 to +125°C
100
5V
CI
Input capacitance
f = 1 MHz VDD1 = VDD2 = 0
V
15
pF
CO
Output capacitance
f = 1 MHz VDD1 = VDD2 = 0
V
15
pF
(7)
Functional test VIH = 0.7 VDD,
VIL = 0.3 VDD
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
L
H
1. Each input/output, as applicable, is tested at the specified temperature, for the specified limits, to the tests specified in
SMD5962-98580 table I. Non-designated output terminals are high level logic, low level logic or open, except for all IDD
tests, where the output terminals are open. When performing these tests, the current meter must be placed in the circuit
such that all current flows through the meter.
2. This device requires both VDD1 and VDD2 power supplies for operation. The power supply is indicated and followed by the
voltage to which the power supply is set to the given test.
3. This parameter is supplied as a design limit but not guaranteed or tested.
4. No more than one output should be shorted at a time for a maximum duration of one second.
5. Power does not include power contribution of any CMOS output sink current.
6. Power dissipation specified per switching output.
7. Tests must be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table must, at minimum, test all the functions of
each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the
function table, Table 2. Functional tests are performed in sequence as approved by the qualifying activity on qualified
devices. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions:
VIH = VIH(min + 20%, -0%); VIL = VIL(max + 0%, -50%), as specified herein, for TTL, CMOS, or Schmitt compatible inputs.
Devices are guaranteed to VIH(min) and VIL(max).
Doc ID 18093 Rev 2
11/22
Electrical characteristics
Table 7.
54AC164245
AC electrical characteristics (1)
Limits
Symbol
Parameter
Propagation delay time, data
to bus (active low) CL = 50 pF
tPLH
Propagation delay time, data
to bus (active low) CL = 50 pF
Propagation delay time, data
to bus (active high) CL = 50 pF
tPHL
Propagation delay time, data
to bus (active high) CL = 50 pF
Propagation delay time, output
enable, OEn to bus (active
low), CL = 50 pF
tPZL
tPLZ
tPHZ
12/22
Max.
1.0
20
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
1.0
20
Port A = Port B = 5 V
VDD1=4.5 to 5.5 V
VDD2=4.5 to 5.5 V
1.0
15
Port A = 3.3V
Port B = 5 V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
1.0
20
Port A = Port B = 3.3 V
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
1.0
20
Port A = Port B = 5 V
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
15
Port A = 3.3 V
Port B = 5V
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
1.0
18
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
1.0
18
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
12
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
1.0
18
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
1.0
18
VDD1 = 4.5 to 5.5V
VDD2 = 4.5 to 5.5V
1.0
12
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.6 V
1.0
20
VDD1 = 2.7 to 3.6 V
VDD2 = 2.7 to 3.6 V
1.0
20
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
15
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.3 V
1.0
18
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
1.0
18
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
12
Port A = 3.3 V
Port B = 5 V
Port A = 3.3 V
Port B = 5 V
Propagation delay time, output Port A = Port B = 3.3 V
disable, OEn to bus (low
impedance), CL= 50 pF
Port A = Port B = 5 V
Propagation delay time, output
disable, OEn to bus (high
impedance), CL = 50 pF
Unit
Min.
VDD1 = 4.5 to 5.5 V
VDD2 =2.7 to 3.6 V
Propagation delay time, output Port A = Port B = 3.3 V
enable, OEn to bus (active
high), CL = 50 pF
Port A = Port B = 5 V
Propagation delay time, output
disable, OEn to bus (low
impedance), CL = 50 pF
Test condition (VDD)
Port A = 3.3 V
Port B = 5 V
Propagation delay time, output Port A = Port B = 3.3 V
enable, OEn to bus (active
low), CL = 50 pF
Port A = Port B = 5 V
Propagation delay time, output
enable, OEn to bus (active
high), CL = 50 pF
tPZH
Port voltage
Port A = 3.3 V
Port B = 5 V
Propagation delay time, output Port A = Port B = 3.3 V
disable, OEn to bus (high
impedance), CL= 50 pF
Port A = Port B = 5 V
Doc ID 18093 Rev 2
ns
ns
ns
ns
ns
ns
54AC164245
Table 7.
Electrical characteristics
AC electrical characteristics (1) (continued)
Limits
Symbol
Parameter
Propagation delay time, output
enable, DIRn to bus (active
low), CL = 50 pF
tPZL (1)
Port A = 3.3 V
Port B = 5 V
Propagation delay time, output Port A = Port B = 3.3 V
disable, DIRn to bus (low
impedance), CL= 50 pF
Port A = Port B = 5 V
Propagation delay time,
output disable, DIRn to bus
(high impedance), CL = 50 pF
tPHZ (1)
Port A = 3.3 V
Port B = 5 V
Propagation delay time, output Port A = Port B = 3.3 V
enable, DIRn to bus (active
high), CL= 50 pF
Port A = Port B = 5 V
Propagation delay time, output
disable, DIRn to bus (low
impedance), CL =50 pF
tPLZ (1)
Port A = 3.3 V
Port B = 5 V
Propagation delay time, output Port A = Port B = 3.3 V
enable, DIRn to bus (active
low), CL= 50 pF
Port A = Port B = 5 V
Propagation delay time, output
enable, DIRn to bus (active
high), CL = 50 pF
tPZH (1)
Port voltage
Port A = 3.3 V
Port B = 5.0 V
Propagation delay time, output Port A = Port B = 3.3 V
disable, DIRn to bus (high
impedance), CL= 50 pF
Port A = Port B = 5 V
Test condition (VDD)
Unit
Min.
Max.
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.3 V
1.0
18
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
1.0
18
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
12
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.3 V
1.0
18
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
1.0
18
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
12
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.3 V
1.0
20
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
1.0
20
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
15
VDD1 = 4.5 to 5.5 V
VDD2 = 2.7 to 3.3 V
1.0
20
VDD1 = 2.7 to 3.3 V
VDD2 = 2.7 to 3.3 V
1.0
20
VDD1 = 4.5 to 5.5 V
VDD2 = 4.5 to 5.5 V
1.0
15
ns
ns
ns
ns
1. Guaranteed by design but not tested.
Doc ID 18093 Rev 2
13/22
Radiations
4
54AC164245
Radiations
Total dose (Mil1019 dose rate): all parameters are post-irradiation guaranteed by wafer-lot
acceptance (after dose, all guaranteed electrical parameters are tested on a sample of units
of each wafer lot). All parameters provided in Table 6 and Table 7 apply to both pre- and
post-irradiation. The 54AC164245 is a pure CMOS product. The irradiation is performed at
high dose rates.
Heavy ions: the behavior of the product when submitted to heavy ions is guaranteed by
qualification and is not tested in production. Heavy-ion trials are performed on qualification
lots only.
Table 8.
Radiations
Type
TID
Features
Total Ionizing dose
High dose rate (50 - 300 rad/sec) up to:
Value
Unit
100
k rad
SEL immune (at 125°C) up to:
110
SEU immune up to:
64
Heavy ions
14/22
MeV.cm²/mg
Doc ID 18093 Rev 2
54AC164245
5
Test circuit
Test circuit
Figure 3.
Test circuit
6##
05,3%
'%.%2!4/2
$
$
$
$
$54
)3.+
#,
24
62%&
)32#
!-V
Note:
CL = 50 pF or equivalent (includes jig and probe capacitance), RT = ZOUT of pulse generator
(typically 50Ω ), VREF = 0.5 VDD. ISRC is set to -1.0 mA and ISNK is set to 1.0 mA for tPHL and
tPLH measurements. Input signal from pulse generator: VI = 0.0 V to VDD; f = 10 MHz;
tr = 1.0 V/ns "0.3 V/ns; tf = 1.0 V/ns "0.3 V/ns; tr and tf are measured from 0.1 VDD to 0.9
VDD and from 0.9 VDD to 0.1 VDD respectively.
Figure 4.
Waveform 1: propagation delay
TR
).054
TF
6$$
'.$
T0(,
T0,(
6/(
/54054
6/,
!-V
Doc ID 18093 Rev 2
15/22
Test circuit
54AC164245
Figure 5.
Waveform 2: enable and disable times (port A = port B, 5 V operation)
6$$
).054
6
T0:,
T0,:
6$$
6$$
/54054
6$$6
6$$
T0:(
T0(:
6$$
6$$6
/54054
6$$
6$$
!-V
Figure 6.
Waveform 3: enable and disable times (port A = port B, 3.3 V operation)
6$$
).054
6
T0:,
T0,:
6$$
6$$
/54054
6$$6
6$$
T0:(
T0(:
6$$
6$$6
/54054
6$$
6$$
!-V
16/22
Doc ID 18093 Rev 2
54AC164245
Test circuit
Figure 7.
Waveform 4: enable and disable times (port A = 3.3 V, port B = 5 V)
6$$
).054
6
T0:,
T0,:
6$$
6$$
/54054
6$$6
6$$
T0:(
T0(:
6$$
6$$6
/54054
6$$
T0:,
6$$
T0,:
6$$
6$$
/54054
6$$6
6$$
T0:(
T0(:
6$$
6$$6
/54054
6$$
6$$
!-V
Doc ID 18093 Rev 2
17/22
Package information
6
54AC164245
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
18/22
Doc ID 18093 Rev 2
54AC164245
Package information
Figure 8.
Flat-48 package mechanical drawing
Note: The upper metallic lid is not electrically connected to any pins, nor to the IC die inside
the package. Connecting any unused pins or the metal lid to ground or to the power supply
will not affect the electrical characteristics.
Table 9.
Flat-48 mechanical data
mm
inch
Dim
Typ
Min
Max
Typ
Min
Max
A
2.47
2.18
2.72
0.097
0.086
0.107
b
0.254
0.20
0.30
0.010
0.008
0.012
c
0.15
0.12
0.18
0.006
0.005
0.007
D
15.75
15.57
15.92
0.620
0.613
0.627
E
9.65
9.52
9.78
0.380
0.375
0.385
E2
6.35
6.22
6.48
0.250
0.245
0.255
E3
1.65
1.52
1.78
0.065
0.060
0.070
e
0.635
0.025
f
0.20
0.008
L
8.38
6.85
9.40
0.330
0.270
0.370
Q
0.79
0.66
0.92
0.031
0.026
0.036
S1
0.43
0.25
0.61
0.017
0.010
0.024
Doc ID 18093 Rev 2
19/22
Ordering information
54AC164245
7
Ordering information
Table 10.
Order codes
Order code
Description
RHRAC164245K1
Engineering
model
RHRAC164245K01V
20/22
QMLVFlight
Temperature
range
Package
-55 °C to
+125 °C
Flat-48
Marking
Packing
RHFAC164245K1
Conductive
strip pack
5962R9858008VYC
Doc ID 18093 Rev 2
54AC164245
8
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
23-Sep-2011
1
Initial release.
06-Apr-2012
2
Added Pin 4 description to Table 3: Pin descriptions.
Doc ID 18093 Rev 2
21/22
54AC164245
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