Data Sheet MARCH 2000 Revision 1.6 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver General Description Features The LXT908 Universal 10BASE-T and AUI Transceiver is designed for IEEE 802.3 physical layer applications. It provides all the active circuitry to interface most standard 802.3 controllers to either the 10BASE-T media or Attachment Unit Interface (AUI). In addition to standard 10 Mbps Ethernet, the LXT908 also supports full-duplex operation at 20 Mbps. Functional Features LXT908 functions include Manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link testing and reversed polarity detection/correction. The LXT908 can be used to drive either the AUI drop cable or the 10BASE-T twisted-pair cable with only a simple isolation transformer. Integrated filters simplify the design work required for FCC-compliant EMI performance. Convenience Features • • • • • • • • • • • • • The LXT908 is fabricated with an advanced CMOS process and requires only a single 3.3V power supply. Applications Improved Filters - Simplifies FCC Compliance Integrated Manchester Encoder/Decoder 10BASE-T compliant Transceiver AUI Transceiver Supports Standard and Full-Duplex Ethernet Automatic/Manual AUI/RJ-45 Selection Automatic Polarity Correction SQE Disable/Enable function Power Down Mode with tristated outputs Four loopback modes Single 3.3V operation Available in 64-pin LQFP and 44-pin PLCC package Commercial (0 to +70°C) and Extended (-40 to +85°C) temperature range Diagnostic Features • 10BASE-T Hub and Switching products • Four LED Drivers • AUI/RJ-45 Loopback • Computer/workstation 10BASE-T LAN adapter boards LXT908 Block Diagram AUTOSEL MD0 MD1 MD2 MODE SELECT LOGIC Controller Compatibility/ Port Select / Loopback / Link test PAUI LBK LI TCLK CLKI WATCHDOG TIMER XTAL OSC CLKO TEN TWISTED PAIR INTERFACE Select: PLS Only or PLS / MAU RC CMOS TX AMP PULSE SHAPER AND FILTER RC DO COLLISION/ POLARITY DETECT CORRECT MANCHESTER ENCODER TPOPB TPOPA TPONA TPONB RX SLICER TPIP TPIN TXD DROP CABLE INTERFACE CD LEDL ECL TX AMP SQUELCH / LINK DETECT + DOP DON LPBK RXD DI MANCHESTER DECODER RCLK DIP RX SLICER DIN CI COLLISION LOGIC COLLISION RECEIVER CIP CIN COL LEDR LEDT/PDN LEDC/FDE DSQE NTH JAB PLR Refer to www.level1.com for most current information. ) LXT908 Universal 3.3V 10BASE-T and AUI Transceiver TABLE OF CONTENTS Pin Assignments and Signal Descriptions .......... 3 Functional Description .......................................... 7 Introduction ......................................................... 7 Controller Compatibility Modes ........................... 7 Transmit Function ............................................... 7 Jabber Control Function ..................................... 8 Receive Function ................................................ 8 SQE Function ..................................................... 8 Polarity Reverse Function................................... 9 Loopback Function ............................................ 9 Collision Detection Function ............................... 9 Link Integrity Test Function .............................. 10 Application Information....................................... 12 External Components ....................................... 12 Layout Requirements........................................ 12 Auto Port Select with External Loopback Control .............................................................. 12 Full - Duplex Support ........................................ 14 Dual Network Support - 10BASE-T and Token Ring .................................................................. 15 Manual Port Select & Link Test Function .......... 16 Three Media Application ................................... 18 AUI Encoder/Decoder Only............................... 19 2 Test Specifications ...............................................20 Absolute Maximum Values................................20 Recommended Operating Conditions ...............20 I/O Electrical Characteristics .............................21 AUI Electrical Characteristics............................21 Twisted-Pair Electrical Characteristics ..............22 Switching Characteristics ..................................23 RCLK/Start-of-Frame Timing.............................23 RCLK/End-of-Frame Timing..............................24 Transmit Timing.................................................24 Collision, COL/CI Output and Loopback Timing 25 Mode 1 Timing Diagrams ..................................26 Mode 2 Timing Diagrams ..................................28 Mode 3 Timing Diagrams ..................................30 Mode 4 Timing Diagrams ..................................32 Mode 5 Timing Diagrams ..................................34 Mechanical Specifications...................................36 Revision history ...................................................38 LXT908 LXT908 Pin Assignments and Signal Descriptions LXT908 PIN ASSIGNMENTS AND SIGNAL DESCRIPTIONS MD1 MD0 NTH CIN CIP VCC1 DON DOP DIN DIP PAUI 6 5 4 3 2 1 44 43 42 41 40 Figure 1: LXT908 Pin Assignments 39 TPIN 38 TPIP 37 DSQE 36 TPONB 35 TPONA 34 VCC2 33 GND2 32 TPOPA CLKI 12 (Date Code) 13 (Trace Code) (Part#) LXT908PC/PE 14 (Lot#) XXXXXX 15 31 TPOPB COL 16 30 PLR AUTOSEL 17 29 n/c 25 26 27 28 MD2 RXD CD RCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 n/c n/c TPIN TPIP n/c DSQE TPONB TPONA VCC2 GND2 TPOPA TPOPB PLR n/c n/c n/c 24 CLKO RBIAS TEN XXXX XXXX 23 TXD GND1 11 22 TCLK 21 10 LEDC/FDE LBK TEST 20 9 19 JAB 18 8 LEDR 7 LI LEDT/PDN LEDL n/c (Date Code) XXXX XXXX (Trace Code) (Part#) LXT908LC/LE (Lot#) XXXXXX 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 n/c RCLK CD RXD MD2 n/c RBIAS n/c GNDA GND1 LBK LEDC/FDE LEDL LEDT/PDN LEDR n/c 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n/c n/c LI n/c JAB TEST TCLK TXD TEN CLKO CLKI COL AUTOSEL n/c n/c n/c n/c n/c PAUI DIP DIN n/c DOP DON VCCA VCC1 CIP CIN NTH MD0 MD1 n/c 3 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Table 1: LXT908 Signal Descriptions Pin# 4 Symbol I/O 10 56 VCC1 VCC2 – – Power 1 and 2. Connect to positive power supply terminal (+3.3V DC). – 9 VCCA – Analog Supply. (+3.3V) 2 3 11 12 CIP CIN I I AUI Collision Pair. Differential input pair connected to the AUI transceiver CI circuit. The input is collision signaling or SQE. 4 13 NTH I Normal Threshold. When NTH is High, the normal TP squelch threshold is in effect. When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB. 5 6 25 14 15 44 MD0 MD1 MD2 I I I Mode Select 0 (MD0), Mode Select 1 (MD1) and Mode Select 2 (MD2). Mode select pins determine the controller compatibility mode as specified in Table 2. 7, 29 1, 2, 6 16, 17 18, 20 30, 31 32, 33 41, 43 48, 49, 50, 51, 60, 63, 64 N/C – No Connect. These pins may be left unconnected or tied to ground. 8 19 LI I Link Test Enable. Controls Link Integrity Test; enabled when High, disabled when Low. 9 21 JAB O Jabber Indicator. Output goes High to indicate Jabber state. 10 22 TEST I Test. This pin must be tied High. 11 23 TCLK O Transmit Clock. A 10 MHz clock output. This clock signal should be directly connected to the transmit clock input of the controller. TCLK goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 12 24 TXD I Transmit Data. Input signal containing NRZ data to be transmitted on the network. TXD is connected directly to the transmit data output of the controller. 13 25 TEN I Transmit Enable. Enables data transmission and starts the Watch-Dog Timer. Synchronous to TCLK (see Test Specifications for details). 14 15 26 27 CLKO CLKI O I Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI with CLKO left open. 16 28 COL O Collision Detect. Output driving the collision detect input of the controller. COL goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. PLCC LQFP 1 34 Description LXT908 LXT908 Pin Assignments and Signal Descriptions Table 1: LXT908 Signal Descriptions – continued Pin# Symbol I/O 29 AUTOSEL I Automatic Port Select. When High, automatic port selection is enabled (the LXT908 defaults to the AUI port only if TP link integrity = Fail). When Low, manual port selection is enabled (the PAUI pin determines the active port). 18 34 LEDR O Receive LED. Open drain driver for the receive indicator LED. Output is pulled Low during receive, except when data is being looped back to DIN/ DIP from a remote transceiver (external MAU). LED “On” time (Low output) is extended by approximately 100 ms. 19 35 LEDT/ PDN O I Transmit LED (LEDT)/Power Down (PDN). Open drain driver for the transmit indicator LED. Output is pulled Low during transmit. Do not allow this pin to float. If unused, tie High. LED “On” time (Low output) is extended by approximately 100 ms. If externally tied Low, the LXT908 goes to power down state. In power down state, TCLK, COL, RXD, CD, and RCLK (pins 11, 16, 26, 27, and 28, respectively) are tri-stated. 20 36 LEDL O I Link LED. Open drain driver for link integrity indicator LED. Output is pulled Low during link test pass. If externally tied Low, internal circuitry is forced to “Link Pass” state and the LXT908 will continue to transmit link test pulses. 21 37 LEDC/ FDE O I Collision LED (LEDC)/Full Duplex Enable (FDE). Open drain driver for the collision indicator LED pulls Low during collision. LED “On” time (Low output) is extended by approximately 100 ms. If externally tied Low, the LXT908 disables the internal TP loopback and collision detection circuits to allow full-duplex operation or external TP loopback. 22 38 LBK I Loopback. Enables internal loopback mode. Refer to Functional Description and Test Specifications for details. 23 33 39 55 GND1 GND2 – – Ground Returns 1 and 2. Connect to negative power supply terminal (ground). – 40 GNDA – Analog Ground. Ground for analog plane. 24 42 RBIAS I Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating circuit bias. 26 45 RXD O Receive Data. Output signal connected directly to the receive data input of the controller. RXD goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 27 46 CD O Carrier Detect. An output to notify the controller of activity on the network. CD goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 28 47 RCLK O Receive Clock. A recovered 10 MHz clock that is synchronous to the received data and connected to the controller receive clock input. RCLK goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 30 52 PLR O Polarity Reverse. Output goes High to indicate reversed polarity at the TP input. PLCC LQFP 17 Description 5 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Table 1: LXT908 Signal Descriptions – continued Pin# 6 Symbol I/O Description 54 57 TPOPA TPONA O O 31 36 53 58 TPOPB TPONB O O Twisted-Pair Transmit Pairs A & B. Two differential driver pair outputs (A and B) to the twisted-pair cable. The outputs are pre-equalized. Each pair must be shorted together with an 11.5 Ω 1% resistor to match an impedance of 100Ω. 37 59 DSQE I Disable SQE. When DSQE is High, the SQE function is disabled. When DSQE is Low, the SQE function is enabled. SQE must be disabled for normal operation in Hub/Switch applications. 38 39 61 62 TPIP TPIN I I Twisted-Pair Receive Pair. A differential input pair from the TP cable. Receive filter is integrated on chip. No external filters are required. 40 3 PAUI I Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the active port. When PAUI is High, the AUI port is selected. When PAUI is Low, the TP port is selected. In Auto Port Select mode, PAUI must be tied to ground. 41 42 4 5 DIP DIN I I AUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The input is Manchester encoded. 43 44 7 8 DOP DON O O AUI Transmit Pair. A differential output driver pair for the AUI transceiver cable. The output is Manchester encoded. PLCC LQFP 32 35 LXT908 LXT908 Functional Description LXT908 FUNCTIONAL DESCRIPTION Introduction Controller Compatibility Modes The LXT908 Universal 10BASE-T and AUI Transceiver performs the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions as an AUI (PLS-Only device) for use with 10BASE-2 or 10BASE-5 coaxial cable networks, or as an Integrated PLS/MAU for use with 10BASE-T twisted-pair (TP) networks. In addition to standard 10 Mbps operation, the LXT908 also supports full-duplex 20 Mbps operation. The LXT908 is compatible with most industry-standard controllers including devices produced by Advanced Micro Devices (AMD), Motorola, Intel, Fujitsu, National Semiconductor, Seeq, and Texas Instruments, as well as custom controllers. Five different control signal timing and polarity schemes (Modes 1 through 5) are required to achieve this compatibility. Mode select pins (MD2:0) determine Controller compatibility modes as listed in Table 2. Refer to Test Specifications for a complete set of timing diagrams for each mode. The LXT908 interfaces a back-end controller to either an AUI drop cable or a TP cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The AUI interface comprises three circuits: Data Output (DO), Data Input (DI), and Collision (CI). The TP interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the LXT908 contains an internal crystal oscillator and four LED drivers for visual status reporting. Functions are defined from the back end controller side of the interface. The LXT908 Transmit function refers to data transmitted by the back end to the AUI cable (PLS-Only mode) or to the TP network (Integrated PLS/MAU mode). The LXT908 Receive function refers to data received by the back end from the AUI cable (PLS-Only) or from the TP network (Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the LXT908 performs all required MAU functions defined by the IEEE 802.3 10BASE–T specification such as collision detection, link integrity testing, signal quality error messaging, jabber control, and loopback. In the PLS-Only mode, the LXT908 receives incoming signals from the AUI DI circuit with ±18 ns of jitter and drives the AUI DO circuit. Transmit Function The LXT908 receives NRZ data from the controller at the TXD input as shown in the block diagram on the first page of this Data Sheet, and passes it through a Manchester encoder. The encoded data is then transferred to either the AUI cable (the DO circuit) or the TP network (the TPO circuit). The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP, shown in Figure 2. The TPO output is pre-distorted and pre-filtered to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters simplify the design work required for FCC-compliant EMI performance. During idle periods, the LXT908 transmits link integrity test pulses on the TPO circuit (if LI is enabled and integrated PLS/ MAU mode is selected). External resistors control the termination impedance. Figure 2: LXT908 TPO Output Waveform 4V 2V 0V -2V -4V Table 2: Controller Compatibility Mode Options Controller Mode MD2 MD1 MD0 Mode 1 - For AMD AM7990, Motorola 68EN360, MPC860 or compatible controllers Low Low Low Mode 2 - For Intel 82596 or compatible controllers Low Low High Mode 3 - For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)1 Low High Low Mode 4 - For National Semiconductor 8390 or compatible controllers (TI TMS380C26) Low High High Mode 5 - For custom controllers (Mode 3 with TCLK, RCLK and COL inverted) High High Low 1. SEEQ controllers require inverters on CLKI, LBK, RCLK, and COL in Mode 3; or on CLKI, LBK, and TCLK in Mode 5. 7 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Jabber Control Function Figure 3 is a state diagram of the LXT908 Jabber control function. The LXT908 on-chip Watch-Dog Timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the Watch-Dog Timer disables the transmit and loopback functions, and activates the JAB pin. Once the LXT908 is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to 0.75 seconds before it will exit the jabber state. Figure 3: Jabber Control Function Power On No Output DO=Active Nonjabber Output Start_XMIT_MAX_Timer DO=Active ∗ XMIT_Max_Timer_Done DO=Idle data streams above the squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the LXT908 receive function enters the idle state. If the polarity of the TPI circuit is reversed, LXT908 detects the polarity reverse and reports it via the PLR output. The LXT908 automatically corrects reversed polarity. SQE Function In the integrated PLS/MAU mode, the LXT908 supports the signal quality error (SQE) function as shown in Figure 3, although the SQE function can be disabled. After every successful transmission on the 10BASE-T network when SQE is enabled, the LXT908 transmits the SQE signal for 10BT ± 5BT over the internal CI circuit, which is indicated on the COL pin of the device. SQE must be disabled for normal operation in hub and switch applications. In TP applications, the SQE function is disabled when DSQE is set High, and enabled when DSQE is Low. When using the 10BASE-2 port of the LXT908, the SQE function is determined by the external MAU attached. Figure 4: SQE Function Jab Power On XMIT=Disable LPBK=Disable CI=SQE Output Idle DO=Idle DO=Active Unjab Wait Start_Unjab_Timer XMIT=Disable LPBK=Disable CI=SQE Output Detected DO=Idle SQE Wait Test Start_SQE_Test__Wait_Timer Unjab_ Timer_Done DO=Active ∗ Unjab_Timer_Not_Done Receive Function The LXT908 receive function acquires timing and data from the TP network (the TPI circuit) or from the AUI (the DI circuit). Valid received signals are passed through the on-chip filters and Manchester decoder then output as decoded NRZ data and recovered clock on the RXD and RCLK pins, respectively. XMIT=Disable SQE_Test__Wait_Timer_Done ∗ XMIT=Enable SQE Test Start_SQE_Test_Timer CI=SQE SQE_Test_Timer_Done An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid 8 LXT908 LXT908 Functional Description Polarity Reverse Function Collision Detection Function The LXT908 polarity reverse function uses both link pulses and end-of-frame data to determine polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the LXT908 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is always enabled. The collision detection function operates on the twisted pair side of the interface. For standard (half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The LXT908 reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 5 is a state diagram of the LXT908 collision detection function. Refer to Test Specifications for collision detection and COL/CI output timing NOTE: For full-duplex operation, the collision detection circuitry must be disabled. Figure 5: Collision Detection Function Loopback Function The LXT908 provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the LXT908 from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. This “normal” loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and jabber states. The LXT908 also provides three additional loopback functions. An external loopback mode, useful for systemlevel testing, is controlled by pin 21 (LEDC). When LEDC is tied Low, the LXT908 disables the collision detection and internal loopback circuits, to allow external loopback or full-duplex operation. “Normal” TP loopback is controlled by pin 22 (LBK). When the TP port is selected and LBK is High, TP loopback is “forced”, overriding collisions on the TP circuit. When LBK is Low, normal loopback is in effect. AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High, data transmitted by the back-end is internally looped back from the TXD pin through the Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs. A DO=Active ∗ TPI=Idle ∗ XMIT=Enable Power On Idle TPI=Active Output Input TPO=DO DI=DO DI=TPI DO=Active ∗ TPI=Active ∗ XMIT=Enable DO=Active ∗ TPI=Active ∗ XMIT=Enable Collision A DO=Idle + XMIT=Disable TPO=DO DI=TPI CI=SQE DO=Active ∗ TPI=Idle A TPI=Idle DO=Idle 9 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Link Pulse Transmission The LXT908 transmits standard link pulses which meet the 10BASE-T specifications. Figure 6 shows the link integrity pulse timing. Figure 6: Transmitted Link Integrity Pulse Timing 10-20 ms 10 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms LXT908 LXT908 Functional Description Link Integrity Test Function Figure 7 is a state diagram of the LXT908 Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when pin 8 (LI) is tied High. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The LXT908 ignores any link integrity pulse with interval less than 2 - 7 ms. The LXT908 will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses. Figure 7: Link Integrity Test Function Power On Idle Test Start_Link_Loss_Timer Start_Link_Test_Min_Timer Link_Loss_Timer_Done ∗ TPI=Idle ∗ Link_Test_Rcvd=False TPI=Active + (Link_Test_Rcvd=True ∗ Link_Test_Min_Timer_Done) Link Test Fail Reset Link Test Fail Wait Link_Count=0 XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active Link_Test_Rcvd=False ∗ TPI=Idle XMIT=Disable RCVR=Disable LPBK=Disable Link_Count=Link_Count + 1 TPI=Active Link_Test_Rcvd=Idle ∗ TPI=Idle Link Test Fail Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active + Link_Count=LC_Max Link_Test_Min_Timer_Done ∗ Link_Test_Rcvd=True Link Test Fail Extended XMIT=Disable RCVR=Disable LPBK=Disable TPI=Idle ∗ DO=Idle (TPI=Idle ∗ Link_Test_Max_Timer_Done) + (Link_Test_Min_Timer_Not_Done ∗ Link_Test_Rcvd=True) 11 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver APPLICATION INFORMATION Figures 8 through 14 show some typical LXT908 applications. Layout Requirements External Components Auto Port Select with External Loopback Control Crystal Information Suitable crystals are available from various manufacturers. Table 3 lists some suitable crystals based on limited evaluation. Designers should test and validate all crystals before using them in production. Table 3: Suitable Crystals Manufacturer Part Number MTRON MP-1 MP-2 Magnetic Information The TP interface requires a 1:1 ratio for the receive transformer and a 1:2 ratio for the transmit transformer. The AUI interface requires a 1:1 ratio for the data-in, dataout, and collision-pair transformers. A cross-reference list of suitable magnetics and part numbers is available in Application Note 73, Magnetic Manufacturers, which can be found on the Level One web site (www.level1.com). Designers should test and validate all magnetics before committing to a specific component. Figure 8 is a typical LXT908 application. The diagram is arranged to group similar pins together; it does not represent the actual LXT908 pin-out. The controller interface pins (TXD, RXD, TEN, TCLK, RCLK, CD, COL, and LBK) are shown at the top left. Programmable option pins are grouped center left. The PAUI pin is tied Low and all other option pins are tied High. This setup selects the following options: • Automatic Port Selection (PAUI Low and AUTOSEL High) • Normal Receive Threshold (NTH High) • Mode 4, compatible with National controllers (MD2:0 = Low, High, High) NS8390 • SQE Disabled (DSQE High) • Link Testing Enabled (LI High) Status outputs are grouped at lower left. Line status outputs drive LED indicators and the Jabber and Polarity status indicators are available as required. Power and ground pins are shown at the bottom of the diagram. A single power supply is used for both VCC1 and VCC2 with a decoupling capacitor installed between the power and ground busses. An additional power and ground pin (VCCA and GNDA) is supported in designs using the 64-pin LQFP package. A single power supply is used for all three power and ground pins (VCC1, VCC2, VCCA) and (GND1, GND2, GNDA). Install a decoupling capacitor between each power and ground buss. The TP and AUI interfaces are shown at upper and lower right, respectively. Impedance matching resistors for 100 UTP are installed in each I/O pair but no external filters are required. 12 LXT908 Application Information Figure 8: LAN Adapter Board - Auto Port Select with External Loopback Control TXE TXC NS8390 BACK-END CONTROLLER INTERFACE RXC RXD CRS COL LOOPBACK ENABLE LBK CLKI CLKO RJ45 TXD 1 TPIN TEN TCLK RCLK RXD CD 1 : 1 16 6 100 Ω 5 14 3 TPIP 4 COL LBK TPONB TPONA 11.5 Ω 1% 6 1:2 3 11 2 PAUI AUTOSEL NTH DSQE LI MD2 MD1 MODE SELECT MD0 330 Green Red 330 Red 78 Ω CIN 9 1 1 1 16 9 2 2 CIP 330 Red 8 10 JAB PLR LINE STATUS 330 TPOPB TPOPA LXT908 PROGRAMMING OPTIONS 220pF 11.5 Ω 1% DON 78 Ω 4 3 15 11 4 13 12 5 LEDC/FDE LEDR LEDT/PDN LEDL 5 12 78 Ω 7 10 DOP DIN D - CONNECTOR to AUI DROP CABLE TXD 20 pF 20 MHz To 10 BASE-T TWISTEDPAIR NETWORK 20 pF 13 6 14 7 15 8 TEST +3.3V DIP RBIAS 1 % GND1 Fuse 9 12.4 kΩ VCC1 VCC2 1 8 GND2 1 Chassis Gnd + 12 V Bias resistor RBIAS should be located close to the pin and isolated from other signals. 13 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Full Duplex Support doubling the available bandwidth of the network. In this application the SQE function is enabled (DSQE tied Low), and the LXT908 AUI port is not used. Figure 9 shows the LXT908 with a Texas Instruments 380C24 CommProcessor. The 380C24 is compatible with Mode 4 (MD2:0 = Low, High, High). When used with the 380C24 or other full duplex-capable controller, the LXT908 supports full-duplex Ethernet, effectively Figure 9: Full-Duplex Operation CLKI 3 20 pF 20 MHz CLKO RJ45 TXD LPBK *TEST0 OUTSEL0 1N914 1 TEN TCLK RCLK TPIN RXD CD TPIP COL LBK LEDC/FDE 10 KΩ AUTOSEL *Open Collector Driver NTH 1 1 : 1 16 6 100 Ω 5 14 3 4 TPONB LXT908 TXD TXEN TXC RXC RXD CSN COLL TPONA 11.5 Ω 1% 6 1:2 11 2 220pF TPOPB TPOPA 11.5 Ω 1% 3 8 To 10 BASE-T TWISTEDPAIR NETWORK 20 pF TMS380C24 9 1 4.7 KΩ PROGRAMMING OPTIONS LI DSQE PAUI MD2 CIN CIP MODE SELECT MD1 MD0 LINE STATUS JAB PLR DON PAUI DOP 330 330 Green R e d Red 330 LEDR LEDT/PDN LEDL 1 Half/Full Duplex Selection controlled by TMS380C24 Pin Test0 and OUTSEL0. 2 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 3 The TMS380C26 may be substituted for dual network support of 10BASE-T and Token Ring. DIN DIP TEST +3.3 V VCC1 2 12.4 kΩ RBIAS 1 % VCC2 GND1 GND2 14 LXT908 Application Information Dual Network Support-10Base T and Token Ring Figure 10 shows the LXT908 with a Texas Instruments 380C26 CommProcessor. The 380C26 is compatible with Mode 4 (MD2:0 = Low, High, High). When used with the 380C26, both the LXT908 and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual network support from a single connector. The LXT908 AUI port is not used. Figure 10: LXT908/380C26 Interface for Dual Network Support of 10BASE-T and Token Ring From TI TMS38054 Token Ring Transceiver To TI TMS38054 Token Ring Transceiver 380C26 CLKI TXD TXD TXE TXC RXC RXD CRS COL LBK CLKO 2 1 TPIN TEN 100 Ω RXD CD COL TPONB JAB LINE STATUS 330 330 Green Red Red Red 11 TPOPA 11.5 Ω 1% 3 2 220pF 8 9 1 TPOPB 18 p F CIN PLR 330 11.5 Ω 1% 6 1 : 2 TPONA LXT908 MODE SELECT 14 4 AUTOSEL NTH DSQE PAUI LI MD1 MD0 5 3 TPIP LBK MD2 RJ45 1 : 1 16 6 TCLK RCLK PROGRAMMING OPTIONS 330 20 pF 20 MHz To 10 BASE-T TWISTEDPAIR NETWORK 20 pF CIP 1 LEDC/FDE LEDR LEDT/PDN LEDL DON 2 DOP Bias resistor RBIAS should be located close to the pin and isolated from other signals. Additional magnetics and switching logic (not shown) is required to implement the dual network solution. DIN DIP TEST +3.3 V 12.4 kΩ VCC1 RBIAS VCC2 1 % GND1 GND2 1 15 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Manual Port Select & Link Test Function With MD2:0 = Low, High, Low, the LXT908 logic and framing are set to Mode 3 (compatible with Fujitsu MB86950 and MB86960, and Seeq 8005 controllers). Figure 11 shows the setup for Fujitsu controllers. Figure 12 on page 17 shows the four inverters required to interface with the Seeq 8005 controller. As in Figure 8 on page 13, both these Mode 3 applications show the LI pin tied High, enabling Link Testing; and the NTH and DSQE pins are both tied High, selecting the standard receiver threshold and disabling SQE. However, in these applications AUTOSEL is tied Low, allowing external port selection through the PAUI pin. Figure 11: LAN Adapter Board - Manual Port Select with Link Test Function 20 pF 20 pF 20 MHz TCKN MB86950 or MB86960 BACK-END/ CONTROLLER INTERFACE RCKN RXD XCD XCOL LBC Port Selection Green Red 6 100 Ω 5 TPIP 4 TPONB 11.5 Ω 1% TPONA 6 Red 1:2 3 11 2 220pF 11.5 Ω 1% 8 9 1 LXT908 TPOPA TPOPB 78 Ω CIN 1 1 16 9 2 10 330 Red 14 3 LBK PAUI AUTOSEL PLR 330 16 CD COL JAB LINE STATUS 1:1 TPIN TCLK RCLK RXD MD2 MD1 MD0 MODE SELECT 330 RJ45 1 NTH DSQE LI PROGRAMMING OPTIONS 330 CLKO 2 CIP LEDC/FDE LEDR LEDT/PDN LEDL 78 Ω DON 3 15 11 4 4 13 12 5 DOP 78 Ω DIN 5 12 7 10 D - CONNECTOR to AUI DROP CABLE TEN CLKI TXD TEN To 10 BASE-T TWISTEDPAIR NETWORK TXD 13 6 14 7 15 8 TEST +3.3 V 8 DIP 12.4 kΩ VCC1 RBIAS VCC2 1 % GND1 GND2 1 1 16 Fuse 9 Chassis Gnd + 12 V Bias resistor RBIAS should be located close to the pin and isolated from other signals. LXT908 Application Information Figure 12: Manual Port Select with Seeq 8005 Controller External 20 MHz Source Left Open CSN 8005 CLKO CLKI LBK CD RxD RJ45 1 COLL 6 100 Ω TxC TxD PROGRAMMING OPTIONS 14 TPIP 4 TPONB PAUI AUTOSEL NTH DSQE LI Port Selection 5 3 COL TEN TCLK TXD TxEN 16 TPIN RXD RCLK RxC 1:1 11.5 Ω 1% 6 TPONA 1:2 3 11 2 220pF 11.5 Ω 1% TPOPA 8 To 10 BASE-T TWISTEDPAIR NETWORK CLKI LPBK 9 1 TPOPB MD1 MD0 LINE STATUS JAB PLR 330 330 330 78 Ω CIN 1 1 Red Red Red 9 2 10 330 2 Green 16 LEDC/FDE LEDR LEDT/PDN LEDL TEST CIP 78 Ω DON 3 15 11 4 4 13 12 5 DOP 78 Ω DIN 5 12 7 10 D - CONNECTOR to AUI DROP CABLE MODE SELECT LXT908 MD2 13 6 14 7 15 8 8 DIP VCC1 +3.3V RBIAS VCC2 12.4 kΩ 1 % GND1 GND2 1 1 Fuse 9 Chassis Gnd + 12 V Bias resistor RBIAS should be located close to the pin and isolated from other signals. 17 18 1 CLKO 12.4 kΩ 1% RBIAS VCC2 VCC1 TEST LEDL LEDT/PDN LEDR LEDC/FDE PLR JAB MD0 MD1 MD2 LI PAUI DSQE NTH AUTOSEL LBK COL CD RXD RCLK TCLK TEN TXD CLKI GND1 LXT908 0.1 µF +3.3 V 10 k Ω LBK CDT CRS RXD RXC RTS TXC CLK TXD GND2 DIP DIN DOP DON CIP CIN TPOPB TPOPA TPONA TPONB TPIP TPIN 11.5 Ω 1% 11.5 Ω 1% 100 Ω 8 6 3 1 1:2 1:1 9 11 14 16 78 Ω 78 Ω 78 Ω 1 2 3 4 5 6 9 8 10 9 8 12 13 15 7 5 4 2 16 10 7 1 12 5 13 15 2 4 16 To 10 BASE-T TWISTEDPAIR NETWORK 1 RJ45 8 7 6 5 4 3 2 Chassis Gnd 15 14 13 12 11 10 9 1 1.5 kΩ + 12 V Fuse D - CONNECTOR to AUI DROP CABLE (Thick Coax) HBE GND RXRX+ RR+ RR- VEE TX+ VEE VEE RXI TXD CD+ TX- CDS CD- DP8392 0.01 µF 1 MΩ 1/2 W -9V 1 kΩ 1% 1N916 0V 9 13 12 V- N/C V+ 24 23 3 1 2 75 µF / 1 kV GND GND EN 5V 5V PM6044 BHC to THIN COAX NETWORK +5 V Figure 13 shows the LXT908 in Mode 2 (compatible with Intel 82596 controllers) with additional media options for the AUI port. Power Down 10 k Ω LINE STATUS MODE SELECT LINK TEST ENABLE PROGRAMMING OPTIONS 82566 BACK-END/ CONTROLLER INTERFACE 20 MHz System Clock Left Open LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Three Media Application Two transformers are used to couple the AUI port to either a D-connector or a BNC connector. (A DP8392 coax transceiver with PM6044 power supply are required to drive the thin coax network through the BNC.) Figure 13: Three Media Application LXT908 Application Information AUI Encoder/Decoder Only In the application shown in Figure 14, the DTE is connected to a coaxial network through the AUI. AUTOSEL is tied Low and PAUI is tied High, manually selecting the AUI port. The twisted-pair port is not used. With MD2:0 all tied Low, the LXT908 logic and framing are set to Mode 1 (compatible with AMD and Motorola controllers). The LI pin is tied Low, disabling the link test function. The DSQE pin is also Low, enabling the SQE function. The LBK input controls loopback. A 20 MHz system clock is supplied at CLKI with CLKO left open. Figure 14: AUI Encoder/Decoder Only Application Left Open 20 MHz TX TENA TCLK RCLK AM7990 BACK-END/ CONTROLLER INTERFACE RX RENA CLSN LOOPBACK CONTROL LBK CLKI CLKO TXD TEN TCLK RCLK RXD CD COL LBK AUTOSEL 78 Ω PAUI MODE SELECT JAB PLR LINE STATUS 330 330 16 9 10 2 CIP LXT908 MD2 MD1 MD0 1 1 2 NTH DSQE LI PROGRAMMING OPTIONS 330 CIN DON 78 Ω 4 3 15 11 4 13 12 5 5 12 78 Ω 7 10 DOP DIN 330 13 6 14 D - CONNECTOR to AUI DROP CABLE SYSTEM CLOCK 7 15 8 GREEN Red Red Red LEDC/FDE LEDR LEDT/PDN LEDL 8 DIP Fuse 9 Chassis Gnd TEST +3.3 V VCC1 + 12 V 1 RBIAS VCC2 12.4 kΩ 1 % GND1 GND2 1 Bias resistor RBIAS should be located close to the pin and isolated from the other signals 19 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver TEST SPECIFICATIONS NOTE Tables 4 through 13 and Figures 15 through 44 represent the performance specifications of the LXT908. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in Tables 6 through 13 apply over the recommended operating conditions specified in Table 5. . Table 4: Absolute Maximum Values Parameter Symbol Min Max Units VCC -0.3 6 V Ambient operating temperature (Commercial) TA 0 +70 ºC Ambient operating temperature (Extended) TA -40 +85 ºC TSTG -65 +150 ºC Supply voltage Storage temperature CAUTION Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 5: Recommended Operating Conditions Parameter Symbol Min Typ Max Units Recommended supply voltage1 VCC 3.13 3.3 3.47 V Recommended operating temperature (Commercial) TOP 0 – +70 ºC Recommended operating temperature (Extended) TOP -40 – +85 ºC 1. Voltages with respect to ground unless otherwise specified. 20 LXT908 Test Specifications Table 6: I/O Electrical Characteristics Sym Min Typ1 Max Units Input Low voltage2 VIL – – 0.8 V Input High voltage2 VIH 2.0 – – V Output Low voltage VOL – – 0.4 V IOL = 1.6 mA VOL – – 10 %VCC IOL < 10 µ A Output Low voltage (Open drain LED driver) VOLL – – 0.7 V IOLL = 10 mA Output High voltage VOH 2.4 – – V IOH = 40 µ A VOH 90 – – %VCC IOH < 10 µ A CLOAD = 20 pF Parameter Test Conditions Output rise time CMOS – – 3 12 ns TCLK & RCLK TTL – – 2 8 ns Output fall time CMOS – – 3 12 ns TCLK & RCLK TTL – – 2 8 ns CLKI rise time (externally driven) – – – 10 ns CLKI duty cycle (externally driven) – – 40/60 % ICC – 65 85 mA Idle Mode ICC – 95 120 mA Transmitting on TP ICC – 90 120 mA Transmitting on AUI ICC – 0.75 2 mA Supply current Normal Mode Power Down Mode CLOAD= 20 pF 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and 3V. Table 7: AUI Electrical Characteristics Symbol Min Typ1 Max Units Input Low current IIL – – -700 µA Input High current IIH – – 500 µA Differential output voltage VOD ±550 – ±1200 mV Differential squelch threshold VDS 150 260 350 mV Parameter Test Conditions 5 MHz square wave input 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 21 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Table 8: Twisted-Pair Electrical Characteristics Symbol Min Typ1 Max Units ZOUT – 5 – Ω Transmit timing jitter addition2 – – ±6.4 ±10 ns 0 line length for internal MAU Transmit timing jitter added by the MAU and PLS sections2, 3 – – ±3.5 ±5.5 ns After line model specified by IEEE 802.3 for 10BASE-T internal MAU Receive input impedance ZIN – 20 – kΩ Between TPIP/TPIN, CIP/ CIN & DIP/DIN Differential Squelch Threshold Normal Threshold NTH = High VDS 300 395 585 mV 5 MHz square wave input Reduced Threshold NTH = Low VDS 180 250 345 mV 5 MHz square wave input Parameter Transmit output impedance Test Conditions 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. 22 LXT908 Test Specifications Table 9: Switching Characteristics Symbol Minimum Typical1 Maximum Units Maximum transmit time – 20 – 150 ms Unjab time – 250 – 750 ms Time link loss receive – 50 – 150 ms Link min receive – 2 – 7 ms Link max receive – 50 – 150 ms Link transmit period – 8 10/20 24 ms Parameter Jabber Timing Link Integrity Timing 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 10: RCLK/Start-of-Frame Timing Symbol Minimum Typical1 Maximum Units tDATA – 900 1100 ns tDATA – 1200 1500 ns AUI tCD – 25 200 ns TP tCD – 420 550 ns Receive data setup from RCLK Mode 1 tRDS 60 70 – ns Modes 2 through 5 tRDS 30 45 – ns Receive data hold from RCLK Mode 1 tRDH 10 20 – ns Modes 2 through 5 tRDH 30 45 – ns RCLK shut off delay from CD assert (Mode 3 and Mode 5) tsws – ±100 – ns Parameter Decoder acquisition time AUI TP CD turn-on delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 23 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Table 11: RCLK/End-of-Frame Timing Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Units RCLK after CD off Min tRC 5 1 – 5 – BT RXD throughput delay Max tRD 400 375 375 375 375 ns CD turn off delay2 Max tCDOFF 500 475 475 475 475 ns Receive block out after TEN off Typ1 tIFG 5 50 – – – BT RCLK switching delay after CD off (Mode 3 and 5) Typ1 tSWE – – 120(±80) – 120(±80) ns Parameter 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. Table 12: Transmit Timing Symbol Minimum Typical 1 Maximum Units TEN setup from TCLK tEHCH 22 – – ns TXD setup from TCLK tDSCH 22 – – ns TEN hold after TCLK tCHEL 5 – – ns TXD hold after TCLK tCHDU 5 – – ns Transmit start-up delay - AUI tSTUD – 220 450 ns Transmit start-up delay - TP tSTUD – 430 450 ns Transmit through-put delay - AUI tTPD – – 300 ns Transmit through-put delay - TP tTPD – 305 350 ns Parameter 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 24 LXT908 Test Specifications Table 13: Collision, COL/CI Output and Loopback Timing Symbol Minimum Typical1 Maximum Units COL turn-on delay tCOLD – 40 500 ns COL turn-off delay tCOLOFF – 420 500 ns COL (SQE) Delay after TEN off tSQED 0.65 1.2 1.6 µs COL (SQE) Pulse Duration tSQEP 500 1000 1500 ns LBK setup from TEN tKHEH 10 25 – ns LBK hold after TEN tKHEL 10 0 – ns Parameter 1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing. 25 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figures 15 through 20 Figure 15: Mode 1 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN or DIP/DIN tC D CD RCLK tR D S tR D H tD A T A RXD 1 0 1 0 1 0 1 NOTE: RXD changes 25 ns after the rising edge of RCLK. Figure 16: Mode 1 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tC D O F F CD tR D tR C RCLK RXD 1 0 1 0 1 0 1 0 0 NOTE: RXD changes 25 ns after the rising edge of RCLK. 26 LXT908 Test Specifications Figure 17: Mode 1 Transmit Timing TEN tC H E L tE H C H TCLK tD S C H tC H D U TXD tS T U D tT P D TPO Figure 18: Mode 1 Collision Detect Timing CI tC O L O F F tC O L D COL Figure 19: Mode 1 COL/SQE Output Timing/CI Output Timing TEN tS Q E D COL tS Q E P Figure 20: Mode 1 Loopback Timing LBK tK H E H tK H E L TEN 27 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figures 21 through 26 Figure 21: Mode 2 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN or DIP/DIN tC D CD RCLK tR D S tR D H tD A T A RXD 1 0 1 0 1 0 1 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 22: Mode 2 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN CD tC D O F F tR D RCLK RXD 1 0 1 0 1 0 1 0 0 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. 28 LXT908 Test Specifications Figure 23: Mode 2 Transmit Timing TEN tC H E L tE H C H TCLK tD S C H tC H D U TXD tS T U D tTPD TPO Figure 24: Mode 2 Collision Detect Timing CI tC O L D tC O L O F F COL Figure 25: Mode 2 COL/SQE Output Timing tIFG TEN tS Q E D COL tS Q E P Figure 26: Mode 2 Loopback Timing LBK tK H E H tK H E L TEN 29 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figures 27 through 32 Figure 27: Mode 3 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/TPIN or DIP/DIN tC D CD tS W S Recovered from Input Data Stream RCLK tR D S Generated from TCLK tR D H tD A T A RXD 1 0 1 0 1 0 1 0 1 1 1 0 1 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 28: Mode 3 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tC D O F F CD tR D tS W E RCLK Recovered Clock Generated from TCLK RXD 1 0 1 0 1 0 1 0 0 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. 30 LXT908 Test Specifications Figure 29: Mode 3 Transmit Timing TEN tC H E L tE H C H TCLK tD S C H tC H D U TXD tS T U D tT P D TPO Figure 30: Mode 3 Collision Detect Timing CI tC O L O F F tC O L D COL Figure 31: Mode 3 COL/SQE Output Timing TEN tS Q E D tS Q E P COL Figure 32: Mode 3 Loopback Timing LBK tK H E H tK H E L TEN 31 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figures 33 through 38 Figure 33: Mode 4 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/TPIN or DIP/DIN tC D CD RCLK tR D S tR D H tD A T A RXD 1 0 1 0 1 0 1 0 1 1 1 0 1 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 34: Mode 4 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN tC D O F F CD tR D RCLK RXD 1 0 1 0 1 0 1 0 0 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. 32 LXT908 Test Specifications Figure 35: Mode 4 Transmit Timing TEN tC H E L tE H C H TCLK tD S C H tC H D U TXD tT P D tS T U D TPO Figure 36: Mode 4 Collision Detect Timing CI tC O L D tC O L O F F COL Figure 37: Mode 4 COL/SQE Output Timing TEN tS Q E D COL tS Q E P Figure 38: Mode 4 Loopback Timing LBK tK H E H tK H E L TEN 33 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figures 39 through 44 Figure 39: Mode 5 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/ TPIN tC D CD tS W S Recovered from Input Data Stream RCLK tR D S Generated from TCLK tR D H tD A T A RXD 1 0 1 0 1 0 1 0 1 1 1 0 1 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 40: Mode 5 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/ TPIN tC D O F F CD tR D tS W E RCLK Recovered Clock Generated from TCLK RXD 1 0 1 0 1 0 1 0 0 NOTE: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. 34 LXT908 Test Specifications Figure 41: Mode 5 Transmit Timing TEN tC H E L tE H C H TCLK tD S C H tC H D U TXD tS T U D tT P D TPO Figure 42: Mode 5 Collision Detect Timing CI tC O L O F F tC O L D COL Figure 43: Mode 5 COL/SQE Output Timing TEN tS Q E D tS Q E P COL Figure 44: Mode 5 Loopback Timing LBK tK H E H tK H E L TEN 35 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver MECHANICAL SPECIFICATIONS Figure 45: 44-Pin PLCC Package Specifications 44-Pin Plastic Leaded Chip Carrier • Part Number LXT908PC - Commercial temperature range (0°C to +70°C) • Part Number LXT908PE - Extended temperature range (-40°C to +85°C) CL Inches C Millimeters Dim Min Max Min Max A 0.165 0.180 4.191 4.572 A1 0.090 0.120 2.286 3.048 A2 0.062 0.083 1.575 2.108 B 0.050 – 1.270 – C 0.026 0.032 0.660 0.813 D 0.685 0.695 17.399 17.653 D1 0.650 0.656 16.510 16.662 F 0.013 0.021 0.330 0.533 B D1 D D A2 A A1 F 36 LXT908 Mechanical Specifications Figure 46: 64-Pin LQFP Package Specifications 64-Pin Low-Profile Quad Flat Package • Part Number LXT908LC (Commercial Temperature Range) • Part Number LXT908LE (Extended Temperature Range) D D1 Inches Millimeters Dim Min Max Min Max A – 0.063 – 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.007 .011 0.17 0.27 D 0.472 BSC 12.00 BSC D1 0.394 BSC 10.00 BSC E 0.472 BSC 12.00 BSC E1 0.394 BSC 10.00 BSC e 0.020 BSC 0.50 BSC L 0.018 L1 θ3 θ 0.030 0.039 REF 11 o 0o 13 0.45 E1 e /2 0.75 1.00 REF o 7o 11o 13o 0o 7o θ3 L1 A2 A A1 L e E B θ θ3 37 LXT908 Universal 3.3V 10BASE-T and AUI Transceiver REVISION HISTORY Table 14: Changes from Revision 1.5 to Revision 1.6 (03/00) Section Page Change Text Table 1 4 Modify Add to LEDT/PDN Description: “Do not allow this pin to float. If unused, tie High.” LXT908 Signal Descriptions Table 15: Changes from Revision 1.4 to Revision 1.5 (01/99) Section Page Change Text Front Page 1 Update Delete 5V reference in general description and features list. Table 1 4 Update Delete 5V reference to supply pins. 12 Update Delete Magnetics Table 4 (renumber all subsequent tables) and reference Application Note 73. Layout Requirements 12 Update Add power and ground pins (VCCA and GNDA) for 64Pin LQFP package. Figures 13, 14 18, 19 Update Correct RBIAS value to 12.4 kΩ in diagrams. Signal Descriptions Table 4 Magnetics Application Diagrams Figures 8 - 14 Delete Note 1 in Figure 13 (duplication RBIAS placement). 13 - 19 Update Delete 5V supply reference (3.3V only). 20 Update Change recommended supply voltage: Application Diagrams Table 6 Recommended Operating Conditions (Min to Max respectively) From: 3.135 5.0 5.25V To: 3.13 3.3 3.47V All All Edit Various minor editing. Table 16: Changes from Revision 1.3 to Revision 1.4 (09/98) Section Page Change Text Product Title 1 Update Change product name to Universal 10BASE-T and AUI Transceiver. Table 1 4 Update Correct pin 9 of the LQFP package to include 3.3V supply. 20-25 Update Replace test spec note with updated version and delete Signal Descriptions Test Specifications (over recommended range) note on all test spec tables. Backpage 38 40 Update Update backpage. LXT908 Revision History Table 17: Changes from Revision 1.2 to Revision 1.3 (04/98) Section Page Change Text Front Page 1 Update Add 64-pin LQFP to features list. Figure 1 3 Update Add 64-pin LQFP pin assignment diagram. 4 Update Add LQFP package column and pins. 35 Update Add 64-pin LQFP package diagram. Pin Assignments Table 1 Signal Descriptions Figure 46 Package Diagram Table 18: Changes from Revision 1.1 to Revision 1.2 (03/98) Section Page Change Text Front Page 1 Update Add Commercial (0 to +70°C) and extended (-40 to +85°C) temperature range to Features list. Figure 1 3 Update Add “PE” to package designator for extended temperature. 18 Update Add extended temperature (-40 to +85°C). 34 Update Add part number LXT908PE and extended temperature range (-40 to +85°C). 35 Update Add revision history section. Pin Assignments Tables 5 and 6 Absolute Max Values Operating Conditions Figure 45 Package Diagram Revision History Table 19: Changes from Revision 1.0 to Revision 1.1 (10/97) Section Page Change Text Table 1 4&5 Update Change note for no connect pins #7 and #29. This pin may be left unconnected or tied to ground. 10 Update Change Belfuse AUI magnetic part number from S553-1006-AE to S553-1006-D0. Signal Descriptions Table 4 Suitable Magnetics 39 Corporate Headquarters 9750 Goethe Road Sacramento, California 95827 Telephone: (916) 855-5000 Web: www.level1.com ) The Americas EAST International WEST ASIA/PACIFIC EUROPE Eastern Area Headquarters Western Area Headquarters Asia / Pacific Area Headquarters European Area HQ & Southern Regional Office 234 Littleton Road, Unit 1A Westford, MA 01886 USA Tel: (978) 692-1193 Fax: (978) 692-1244 3375 Scott Blvd., #110 Santa Clara, CA 95054 USA Tel: (408) 496-1950 Fax: (408) 496-1955 101 Thomson Road United Square #08-01 Singapore 307591 Thailand Tel: +65 353 6722 Fax: +65 353 6711 Parc Technopolis-Bat. Zeta 3, avenue du Canada Z.A. de Courtaboeuf Les Ulis Cedex 91974 France Tel: +33 1 64 86 2828 Fax: +33 1 60 92 0608 North Central Regional Office South Central Regional Office Central Asia/Pacific Regional Office Central Europe Regional Office One Pierce Place Suite 500E Itasca, IL 60143 USA Tel: (630) 250-6044 Fax: (630) 250-6045 800 E. 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If unused, tie High.” Information in this document is provided in connection with Level One products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Level One's Terms and Conditions of Sale for such products, Level One assumes no liability whatsoever, and Level One disclaims any express or implied warranty, relating to sale and/or use of Level One products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Level One products are not interned for use in medical, life saving, or life sustaining applications. Level One may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Level One reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Third party brands and names are the property of their respective owners. The products listed in this publication are covered by one or more of the following patents. Additional patents pending. 5,008,637; 5,028,888; 5,057,794; 5,059,924; 5,068,628; 5,077,529; 5,084,866; 5,148,427; 5,153,875; 5,157,690; 5,159,291; 5,162,746; 5,166,635; 5,181,228; 5,204,880; 5,249,183; 5,257,286; 5,267,269; 5,461,661; 5,493,243; 5,534,863; 5,574,726; 5,581,585; 5,608,341; 5,666,129; 5,671,249; 5,701,099; 5,717,714; 5,742,603; 5,748,634; 5,764,638; 5,777,996; 5,802,052; 5,880,645; 5,881,074; 5,907,553; 5,926,049; 5,926,504; 5,946,398 Copyright © 2000 Level One Communications, Inc., an Intel Company. Specifications subject to change without notice. All rights reserved. IS908DS-R1.6-0300