ETC LXT905PE

LXT905
Universal 10BASE-T Transceiver with 3.3V Support
Datasheet
The LXT905 Universal 10BASE-T Transceiver is designed for IEEE 802.3 physical layer
applications. It provides, in a single CMOS device, all the active circuitry for interfacing most
standard 802.3 controllers to 10BASE- T media.
LXT905 functions include Manchester encoding/decoding, receiver squelch and transmit pulse
shaping, jabber, link integrity testing, and reversed polarity detection/correction. The LXT905
drives the 10BASE-T twisted-pair cable with only a simple isolation transformer using a single
3.3V or 5V power supply. Integrated filters simplify the design work required for FCCcompliant EMI performance.
Applications
■
■
Cable Modems
Hub/Switched Dedicated LANs for
10BASE-T
■
■
Desktop 10BASE-T LAN adapter boards
USB to Ethernet Converters
Product Features
■
■
■
■
■
■
■
Transparent 3.3 V or 5 V operation
Integrated filters – Simplifies FCC
compliance
Integrated Manchester encoder/decoder
10BASE-T compliant transceiver
Automatic polarity correction
SQE enable/disable
Four LED drivers
■
■
■
■
■
Full duplex capability
Power-down mode with tristate
Available in 28-pin PLCC and 32-pin
LQFP packages
Commercial Temperature Range ( 0 to
+70ºC)
Extended Temperature Range (-40 to
+85ºC)
As of January 15, 2001, this document replaces the Level One document
LXT905 Universal 10BASE-T Transceiver with 3.3V Support Datasheet.
Order Number: 249271-001
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT905 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Contents
1.0
Pin Assignments and Signal Descriptions ...................................................... 8
2.0
Functional Description...........................................................................................10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
3.0
Application Information .........................................................................................17
3.1
3.2
3.3
3.4
4.0
Datasheet
Introduction..........................................................................................................17
3.1.1 Termination Circuitry ..............................................................................17
3.1.2 Twisted-Pair Interface ............................................................................17
3.1.3 RBIAS Pin ..............................................................................................17
3.1.4 Crystal Information .................................................................................17
3.1.5 Magnetic Information..............................................................................17
Typical 10BASE-T Application ............................................................................18
Dual Network Support - 10BASE-T and Token Ring...........................................19
Simple 10BASE-T Connection ............................................................................21
Test Specifications ..................................................................................................22
4.1
4.2
4.3
4.4
5.0
Introduction..........................................................................................................10
Controller Compatibility Modes ...........................................................................10
Transmit Function................................................................................................10
Jabber Control Function ......................................................................................12
SQE Function ......................................................................................................13
Receive Function.................................................................................................13
Polarity Reverse Function ...................................................................................14
Collision Detection Function................................................................................14
Loopback Functions ............................................................................................15
2.9.1 Internal Loopback...................................................................................15
2.9.2 External Loopback/Full Duplex...............................................................15
Link Integrity Test Function .................................................................................15
Timing Diagrams for Mode 1(MD1 = Low, MD0 = Low) ......................................25
Timing Diagrams for Mode 2 (MD1=Low, MD0=High) ........................................27
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) ....................................29
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) ...................................31
Mechanical Specifications....................................................................................34
3
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
4
LXT905 Block Diagram ......................................................................................... 7
LXT905 Pin Assignments...................................................................................... 8
LXT905 TPO Output Waveform .......................................................................... 10
Jabber Control Function...................................................................................... 12
SQE Function...................................................................................................... 13
Collision Detection Function................................................................................ 14
Link Integrity Test Function ................................................................................. 16
Intel Controller Application (Mode 2)................................................................... 18
LXT905/380C26 Interface for Dual 10BASE-T and Token Ring Support
(Mode 4).............................................................................................................. 20
LXT905/MC68EN360 Interface for Full Duplex 10BASE-T (Mode 1) ................. 21
Mode 1 RCLK/Start-of-Frame Timing ................................................................ 25
Mode 1 RCLK/End-of-Frame Timing .................................................................. 26
Mode 1 Transmit Timing .................................................................................... 26
Mode 1 COL Output Timing ............................................................................... 27
Mode 2 RCLK/Start-of-Frame ............................................................................ 27
Mode 2 RCLK/End-of-Frame Timing .................................................................. 28
Mode 2 Transmit Timing .................................................................................... 28
Mode 2 COL Output Timing ............................................................................... 29
Mode 3 RCLK/Start-of-Frame Timing ................................................................ 29
Mode 3 RCLK/End-of-Frame Timing................................................................... 30
Mode 3 Transmit Timing .................................................................................... 30
Mode 3 COL Output Timing ............................................................................... 31
Mode 4 RCLK/Start-of-Frame Timing ................................................................ 31
Mode 4 RCLK/End-of-Frame Timing .................................................................. 32
Mode 4 Transmit Timing .................................................................................... 32
Mode 4 COL Output Timing ............................................................................... 33
LXT905PC Package Specifications ................................................................... 34
LXT905LC Package Specifications .................................................................... 35
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Datasheet
LXT905 Signal Descriptions .................................................................................. 8
Controller Compatibility Mode Options................................................................11
Loopback Modes .................................................................................................15
Suitable Crystals .................................................................................................17
Absolute Maximum Values..................................................................................22
Recommended Operating Conditions .................................................................22
I/O Electrical Characteristics ...............................................................................22
TP Electrical Characteristics ...............................................................................23
Switching Characteristics ....................................................................................23
RCLK/Start-of-Frame Timing...............................................................................23
RCLK/End-of-Frame Timing................................................................................24
Transmit Timing...................................................................................................24
Miscellaneous Timing..........................................................................................24
PLASTIC LEADED CHIP CARRIER ...................................................................34
QUAD FLAT PACKAGE......................................................................................35
5
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Revision History
6
Revision
Date
2.7
10/00
Description
Change resistor values for Figures 7, 8, and 9.
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Figure 1. LXT905 Block Diagram
Mode Select Logic
Controller
Compatibility /
Loopback /
Link Test
LI
TCLK
CLKI
CLKO
TEN
TXD
XTAL
OSC
Manchester
Encoder
RC
Watch-Dog
Timer
D
Pulse
Shaper
&
Filter
Loopback
Control
CD
LEDL
RCLK
RXD
Squelch/
Link Detect
Manchester
Decoder
COL
Collision
Logic
LEDR
Datasheet
MD0
MD1
LEDT/PDN
LEDC/FDE
TPOP
TPON
RC
Collision/
Polarity
Detect/
Correct
DSQE
CMO
S
TX
RX
Slicer
TPIP
TPIN
LBK
7
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
1.0
Pin Assignments and Signal Descriptions
LQFP
Rev #
GND3
CLKO
CLKI
VCC1
TPIN
TPIP
MD1
MD1
MD0
TPON
GND3
VCC2
TPOP
DSQE
RBIAS
LEDL
CD
GND1
GND2
VCC1
RCLK
RXD
LI
Table 1.
LQFP
Pin #
LBK
TEN
TCLK
TXD
COL
LEDC/FDE
LEDT/PDN
5
6
Rev #
7
PLCC
8 Part # LXT905PC/PE XX
9 LOT # XXXXXX
FPO # XXXXXXXX
10
11
25
24
23
22
21
20
19
MD0
TPON
GND2
VCC2
TPOP
DSQE
RBIAS
LEDR
LEDL
CD
GND1
RCLK
RXD
LI
9
10
11
12
13
14
15
16
Part # LXT905LC/LE XX
LOT # XXXXXX
FPO # XXXXXXXX
24
23
22
21
20
19
18
17
4
3
2
1
28
27
26
1
2
3
4
5
6
7
8
LBK
TEN
TCLK
TXD
COL
LEDC/FDE
LEDT/PDN
LEDR
12
13
14
15
16
17
18
32
31
30
29
28
27
26
25
GND4
CLKO
CLKI
VCC5
VCC4
VCC3
TPIN
TPIP
Figure 2. LXT905 Pin Assignments
LXT905 Signal Descriptions
PLCC
Pin #
Symbol
I/O
13
1
VCC1
–
20
22
VCC2
–
27
–
VCC3
–
28
–
VCC4
–
29
–
VCC5
–
30
2
CLKI
I
31
3
CLKO
O
Description
Power Inputs 1 thru 5. Power supply inputs of 3.3V or 5V.
Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or
a 20 MHz clock applied at CLKI with CLKO left open.
11
15
GND1
–
12
23
GND2
–
21
4
GND3
–
32
–
GND4
–
1
5
LBK
I
Loopback. When High, forces internal loopback. Disables collision and the
transmission of both data and link pulses. Pulled Low internally1.
2
6
TEN
I
Transmit Enable. Enables data transmission and starts the Watch-Dog Timer (WDT).
Synchronous to TCLK. Pulled Low internally1.
3
7
TCLK
O
Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
4
8
TXD
I
Transmit Data. Input signal containing NRZ data to be transmitted on the network.
TXD should be connected directly to the transmit data output of the controller. Pulled
Low internally1.
5
9
COL
O
Collision Signal. Output that drives the collision detect input of the controller.
Ground.
1. Externally pull-up or pull-down each pin separately using a 10k Ω, 1% termination resistor or tie directly to VCC or ground.
2. Do not allow this pin to float. If unused, tie High.
8
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Table 1.
LQFP
Pin #
LXT905 Signal Descriptions (Continued)
PLCC
Pin #
Symbol
I/O
Description
O
LEDC is an open drain driver for the collision indicator pulls Low during collision.
LED “on” (which is Low output) time is extended by approximately 100 ms.
LED Collision or Full Duplex Enable.
6
10
LEDC/
FDE
I
FDE enables full duplex mode (external loopback) if tied Low externally. Pulled
High internally1.
LED Transmit or Power Down.
7
11
LEDT/
O
PDN
I
LEDT is an open drain driver for the transmit indicator. LED “on” (which is Low
output) time is extended by approximately 100 ms. Output is pulled Low during
transmit.2
If externally tied Low, the LXT905 goes to power down state (PDN). In powerdown mode, all logic inputs and outputs are tristated.
8
12
LEDR
O
LED Receive. Open drain driver for the receive indicator LED. LED “on” (i.e., Low
output) time is extended by approximately 100 ms. Output is pulled Low during receive.
Pulled High internally1.
9
13
LEDL
O
LED Link. Open drain driver for link integrity indicator. Output is pulled Low during
link test pass. Pulled High internally1.
10
14
CD
O
Carrier Detect. An output for notifying the controller that activity exists on the
network.
14
16
RCLK
O
Receive Clock. A recovered 10 MHz clock that is synchronous to the received data and
connected to the controller receive clock input.
15
17
RXD
O
Receive Data. Output signal connected directly to the receive data input of the
controller.
16
18
LI
I
Link Enable. Controls link integrity test; enabled when LI is High, disabled when LI is
Low.
17
19
RBIAS
I
Bias Circuitry. A 7.5 kΩ 1% resistor to ground at this pin controls operating circuit
bias.
18
20
DSQE
I
SQE Disable. When DSQE is High, the SQE function is disabled.
When DSQE is Low, the SQE function is enabled. SQE should be disabled for normal
operation in Hub/Switch/Repeater applications. Pulled Low internally1.
19
21
TPOP
O
22
24
TPON
O
23
25
MDO
I
24
26
MDI
I
25
27
TPIP
I
26
28
TPIN
I
Twisted-Pair Outputs. Differential outputs to the twisted-pair cable. The outputs are
pre-equalized.
Mode Select 0 and 1. Mode select pins determine controller compatibility mode in
accordance with Table 2. Pulled Low internally1.
Twisted-Pair Inputs. A differential input pair from the twisted-pair cable. Receive
filter is integrated on-chip. No external filters are required.
1. Externally pull-up or pull-down each pin separately using a 10k Ω, 1% termination resistor or tie directly to VCC or ground.
2. Do not allow this pin to float. If unused, tie High.
Datasheet
9
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
2.0
Functional Description
2.1
Introduction
The LXT905 Universal 10BASE-T Transceiver performs the physical layer signaling (PLS) and
Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions
as an integrated PLS/MAU for use with 10BASE-T twisted-pair networks.
The LXT905 interfaces a back-end controller to a twisted-pair (TP) cable. The controller interface
includes transmit and receive clock and NRZ data channels, as well as mode control logic and
signaling. The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and
Twisted-Pair Output (TPO). In addition to the two basic interfaces, the LXT905 contains an
internal crystal oscillator and four LED drivers for visual status reporting.
Functions are defined from the back-end controller side of the interface. The LXT905 Transmit
function refers to data transmitted by the back end to the twisted-pair network. The LXT905
Receive function refers to data received by the back end from the twisted-pair network. The
LXT905 performs all required functions defined by the IEEE 802.3 10BASE-T MAU specification
such as collision detection, link integrity testing, signal quality error messaging, jabber control, and
loopback.
Figure 3. LXT905 TPO Output Waveform
2.2
Controller Compatibility Modes
The LXT905 is compatible with most industry standard controllers including devices produced by
Advanced Micro Devices (AMD), Intel, Fujitsu, National Semiconductor, Seeq, Motorola and
Texas Instruments. Four different control signal timing and polarity schemes (Modes 1 through 4)
are required to achieve this compatibility. Mode select pins MD0 and MD1 determine controller
compatibility modes as listed in Table 2. Refer to the Test Specifications section for timing
diagrams and parameters.
2.3
Transmit Function
The LXT905 receives NRZ data from the controller at the TXD input as shown in the block
diagram, and passes it through a Manchester encoder. The encoded data is then transferred to the
twisted-pair network (the TPO circuit). The advanced integrated pulse shaping and filtering
network produces the output signal on TPON and TPOP, shown in Figure 3. The TPO output is
pre-distorted and prefiltered to meet the 10BASE-T jitter template. An internal continuous resistorcapacitor filter is used to remove any high-frequency clocking noise from the pulse shaping
10
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
circuitry. Integrated filters simplify the design work required for FCC compliant EMI performance.
During idle periods, the LXT905 transmits link integrity test pulses on the TPO circuit (if LI is
enabled and LBK is disabled).
Table 2.
Controller Compatibility Mode Options
Controller Mode
Mode 1 - For Motorola MC68EN360 or compatible controllers (AMD AM7990)
1
MD1
MD0
Low
Low
Low
High
Mode 3 - For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)2
High
Low
Mode 4 - For TI TMS380C26 or compatible controllers
High
High
Mode 2 - For Intel 82596 or compatible controllers
1. Refer to Intel Application Note 51 (MAC Interface Design Guide for Intel Controllers) when designing with Intel controllers.
2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
Datasheet
11
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
2.4
Jabber Control Function
Figure 4 is a state diagram of the LXT905 jabber control function. The LXT905 on-chip WatchDog Timer (WDT) prevents the DTE from locking into a continuous transmit mode. When a
transmission exceeds the time limit, the WDT disables the transmit and loopback functions and
activates the COL pin. Once the LXT905 is in the jabber state, the TXD circuit must remain idle
for a period of 0.25 to 0.75 seconds before it exits the jabber state.
Figure 4. Jabber Control Function
Power On
No Output
DO=Active
Nonjabber Output
Start_XMIT_MAX_Timer
DO=Active ∗
XMIT_Max_Timer_Done
DO=Idle
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Idle
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab_ Timer_Done
12
DO=Active ∗
Unjab_Timer_Not_Done
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
2.5
SQE Function
The LXT905 supports the Signal Quality Error (SQE) function as shown in Figure 5. After every
successful transmission on the 10BASE-T network, the LXT905 transmits the SQE signal for 10
bit times (BT) ± 5BT on the COL pin of the device.
The SQE can be disabled for repeater/switch applications. When DSQE is set High, the SQE
function is disabled. When DSQE is Low, the SQE function is enabled.
Figure 5. SQE Function
Power On
Output Idle
DO=Active
Output Detected
DSQE=1
DO=Idle ∗
DSQE=0
SQE Wait Test
Start_SQE_Test__Wait_Timer
XMIT=Disable
SQE_Test__Wait_Timer_Done ∗
XMIT=Enable
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test_Timer_Done
2.6
Receive Function
The LXT905 receive function acquires timing and data from the twisted-pair network (the TPI
circuit). Valid received signals are passed through the on-chip filters and Manchester decoder then
output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively.
An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squelch level with proper timing.
If the differential signal at the TPI circuit inputs falls below 85% of the threshold level
(unsquelched) for 8 bit times (typical), the LXT905 receive function enters the idle state. The
LXT905 automatically corrects reversed polarity on the TPI circuit.
Datasheet
13
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
2.7
Polarity Reverse Function
The LXT905 polarity reverse function uses both link pulses and end-of-frame data to determine
polarity of the received signal. If Link Integrity testing is disabled, polarity detection is based only
on received data. A reversed polarity condition is detected when eight consecutive opposite
receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed
polarity is also detected if four consecutive frames are received with a reversed start-of-idle.
Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to
zero. If the LXT905 enters the link fail state and no valid data or link pulses are received within 96
to 128 ms, the polarity is reset to the default non-flipped condition. Polarity correction is always
enabled.
2.8
Collision Detection Function
A collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the
TPO circuit. The LXT905 reports collisions to the back-end via the COL pin. If the TPI circuit
becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end
over the RXD circuit, disabling normal loopback. Figure 6 is a state diagram of the LXT905
collision detection function.
Figure 6. Collision Detection Function
A
TEN=Active ∗
TPI=Idle ∗
XMIT=Enable
Power On
Idle
TPI=Active
Output
Input
TPO=TXD
RXD=TXD
RXD=TPI
TEN=Active ∗
TPI=Active ∗
XMIT=Enable
TEN=Active ∗
TPI=Active ∗
XMIT=Enable
Collision
A
TEN=Idle +
XMIT=Disable
TPO=TXD
RXD=TPI
COL=ACTIVE
TEN=Active ∗
TPI=Idle
14
A
TPI=Idle
TEN=Idle
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
2.9
Loopback Functions
2.9.1
Internal Loopback
The LXT905 provides standard loopback mode as specified in the IEEE specification for the
twisted-pair port, as well as a forced internal loopback mode. Loopback mode operates in
conjunction with the transmit function. Data transmitted by the MAC is internally looped back
within the LXT905 from the TXD pin through the Manchester encoder/decoder to the RXD pin
and returned to the MAC.
Standard loopback mode is disabled when a data collision occurs, clearing the RXD circuit for the
TPI data. Standard loopback is also disabled during link fail, jabber, and full-duplex states.
Loopback is always enabled during forced internal loopback mode.
2.9.2
External Loopback/Full Duplex
The LXT905 also provides an external loopback test mode for system-level testing. When both
LEDC/FDE and LBK are Low, the LXT905 enables external loopback and full-duplex mode.
Internal loopback circuits, SQE, and collision detection are disabled. Refer to Table 3 for a
summary of loopback and duplex modes.
Table 3.
Loopback Modes
Pin Settings
LBK
LEDC/
FDE
Low
Low
Mode Description
Disable internal loopback.
Enable external loopback test mode and full-duplex mode.
Standard loopback mode (default).
Low
High
Data transmitted by the MAC is internally looped back and returned to the MAC except during
collision.
Standard loopback is disabled when a data collision occurs, clearing RXD for data on the
twisted-pair port.
2.10
High
Low
High
High
Not Used.
Forced internal loopback.
Transmit data is looped back on the receive data bus and the twisted-pair port is ignored.
Link Integrity Test Function
Figure 7 is a state diagram of the LXT905 Link Integrity test function. The link integrity test is
used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled
when LI is tied High. When enabled, the receiver recognizes link integrity pulses which are
transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are
detected within 50~150 ms, the chip enters a link fail state and disables the transmit and normal
loopback functions. The LXT905 ignores any link integrity pulse with interval less than 2~7 ms.
The LXT905 remains in the link fail state until it detects either a serial data packet or two or more
link integrity pulses.
Datasheet
15
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figure 7. Link Integrity Test Function
Power On
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
Link_Loss_Timer_Done ∗
TPI=Idle ∗
Link_Test_Rcvd=False
TPI=Active +
(Link_Test_Rcvd=True ∗
Link_Test_Min_Timer_Done)
Link Test Fail Reset
Link Test Fail Wait
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link_Test_Rcvd=False
∗ TPI=Idle
TPI=Active
Link_Test_Rcvd=Idle
∗ TPI=Idle
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
∗ Link_Test_Rcvd=True
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
(TPI=Idle ∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done ∗
Link_Test_Rcvd=True)
TPI=Idle ∗
DO=Idle
16
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
3.0
Application Information
3.1
Introduction
Figures 7 through 9 show typical LXT905 applications. These diagrams group similar pins; they do
not portray the actual chip pinout. The controller interface pins; Transmit Data (TXD), Transmit
Clock (TCLK) Transmit Enable (TEN), Receive Data (RXD), Receive Clock (RCLK), Collision
Signal (COL) and Carrier Detect (CD) pins are at the upper left.
Power and ground pins are at the bottom of each diagram. VCC1 and VCC2 use a single power
supply with decoupling capacitors installed between the power and ground busses. VCC may be
powered by a 5V or 3.3V supply.
3.1.1
Termination Circuitry
Several I/O pins are internally pulled-up or pulled-down to keep the signals from floating. It is
recommended to hard-wire these pins either High or Low. Externally pull-up pins (LEDT/PDN,
LEDC/FDE, LEDR, LEDL) and pull-down pins (LBK, TEN, TXD, DSQE, MDO, MDI)
separately using a 10k Ω, 1% resistor or tie directly to VCC or ground.
3.1.2
Twisted-Pair Interface
The Twisted-Pair interface (TPOP/N and TPIP/N) is at the upper right. The I/O pairs have
impedance-matching resistors for 100Ω UTP, but no external filters are required.
3.1.3
RBIAS Pin
The RBIAS pin sets the levels for the LXT905 output drivers. The LXT905 requires a 7.5kΩ, 1%
resistor directly connected between the RBIAS pin and ground. This resistor should be located as
close to the device as possible. Keep the traces as short as possible and isolated from all other high
speed signals.
3.1.4
Crystal Information
Based on limited evaluation, Table 4 lists some of the suitable crystals. Designers should test and
validate all crystals before committing to a specific component.
Table 4.
Suitable Crystals
Manufacturer
Part Number
MTRON
MP-1
MP-2
3.1.5
Magnetic Information
The LXT905 requires a 1:1 turns ratio for the receive transformer and a 1:2 turns ratio for the
transmit transformer. Application Note 073 lists transformers suitable for the applications
described in this data sheet. Designers are advised to test and validate all magnetics before
committing to a specific component.
Datasheet
17
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
3.2
Typical 10BASE-T Application
Figure 8 is a typical LXT905 application. The DTE is connected to a 10BASE-T network through
the twisted-pair RJ-45 connector. With MD0 tied high and MD1 grounded, the LXT905 logic and
framing are set to Mode 2 (compatible with Intel 82596 controllers*). Connect 20 MHz system
clock input at CLKI. (Leave CLKO open.) The LI pin externally controls the link test function.
* Refer to Intel Application Note 51 (MAC Interface Design Guide for Intel Controllers) when
designing with Intel controllers.
Figure 8. Intel Controller Application (Mode 2)
1
RTS
TXC
RXC
RXD
82596
Back-End/
Controller
Interface
CRS
CDT
Programming
Options
CLKO
50 Ω 1%
TEN
TCLK
50 Ω 1%
TPIP
RCLK
RXD
CD
COL
MD0
MD1
DSQE
LI
LBK
Link Test Enable
Loopback Enable
TPIN
CLKI
TXD
TPON
LXT905
CLK
TXD
20 MHz System Clock
1 1:1
16
11.8 Ω 1%
6
5
3
14
6 1:2
11
11.8 Ω 1%
TPOP
RJ-45
4
3
2
To 10 Base-T
Twisted-Pair Network
0.1 µF
Not Connected
1
8
9
100 pF
100 pF
Line Status
10K
LEDL
LEDC/FDE
LEDT/PDN
10K
10K
+5V
Power
Down
Full
Duplex
VCC1
VCC2
7.5 kΩ 1%
RBIAS
GND1 GND2
0.1 µF
1
18
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
3.3
Dual Network Support - 10BASE-T and Token Ring
Figure 9 shows the LXT905 with a Texas Instruments 380C26 CommProcessor. The 380C26 is
compatible with Mode 4 (MD0 and MD1 both high). When used with the 380C26, both the
LXT905 and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual
network support from a single connector.
Datasheet
19
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figure 9. LXT905/380C26 Interface for Dual 10BASE-T and Token Ring Support
(Mode 4)
20 MHz
20 pF
20 pF
CLKI
TXD
TXD
TXE
TXC
TEN
TCLK
RXC
RXD
RCLK
RXD
CRS
COL
CD
COL
LBK
LBK
MD0
MD1
LI
Line Status
CLKO
1
0.1 µF
1 1:1
TPIN
2 RJ-45
16
50 Ω 1%
50 Ω 1%
TPIP
LXT905
380C26
From TI TMS38054
Token Ring
Transceiver
TPON
5
3
14
6 1:2
11
11.8 Ω 1%
11.8 Ω 1%
TPOP
6
4
3
2
To 10 Base-T
Twisted-Pair Network
To TI TMS38054
Token Ring
Transceiver
1
8
9
100 pF
300
300
300
Green Red
Red
300
Red
+5V
100 pF
LEDR
LEDC/FDE
LEDT/PDN
LEDL
VCC1
7.5 kΩ 1%
RBIAS
VCC2
GND1 GND2 GND3
0.1 µF
20
1
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
2
Additional magnetics and switching logic (not shown) are required to implement the dual network solution.
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
3.4
Simple 10BASE-T Connection
Figure 10 shows a simple 10BASE-T application using an LXT905 transceiver and a Motorola
MC68EN360. The MC68EN360 is compatible with Mode 1 (MD0 and MD1 both Low).
Figure 10. LXT905/MC68EN360 Interface for Full Duplex 10BASE-T (Mode 1)
RCLK
CLK1-4
TXD
TCLK
TXD
RXD
RTS
RXD
TEN
CD
CTS
CD
COL
+5V
10 kΩ
LBK
DSQE
1 1:1
TPIN
16
1
TPIP
TPON
3
14
6 1:2
11
11.8 Ω 1%
11.8 Ω 1%
TPOP
RJ-45
6
5
100 Ω
LEDC/FDE
+5V
Not Connected
4
3
2
To 10 Base-T
Twisted-Pair Network
SCC1
CLK1-4
Parallel
I/O
CLKO
CLKI
LXT905
20 MHz
System
Clock
MC68EN360
1
8
9
100 pF
MD0
MD1
100 pF
300 Ω
Green
LEDL
+5V
VCC1
VCC2
LI
0.1 µF
1
Datasheet
7.5 kΩ 1%
RBIAS
GND1 GND2 GND3
LEDC/FDE requires an open-collector driver.
21
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
4.0
Test Specifications
Note:
The minimum and maximum values in Table 5 through Table 13 and Figure 11 through Figure 26
represent the performance specifications of the LXT905 and are guaranteed by test, except where
noted by design. Minimum and maximum values in Table 7 through Table 13 apply over the
recommended operating conditions specified in Table 6.
Table 5.
Absolute Maximum Values
Parameter
Symbol
Min
Max
Units
Supply voltage
VCC
-0.3
+6
V
Ambient operating temperature (Commercial)
TOP
0
+70
ºC
Ambient operating temperature (Extended)
TOP
-40
+85
ºC
Storage temperature
TST
-65
+150
ºC
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 6.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Recommended supply voltage1
VCC
3.135
5.0
5.25
V
Recommended operating temperature (Commercial)
TOP
0
–
+70
ºC
Recommended operating temperature (Extended)
TOP
-40
–
+85
ºC
1. Voltage is with respect to ground unless specified otherwise.
Table 7.
I/O Electrical Characteristics
Parameter
2
Sym
Min
Typ1
Max
Units
0.8
V
Test Conditions
VIL
–
–
2
VIH
2.0
–
–
V
Output low voltage
VOL
–
–
0.4
V
IOL = 1.6 mA
VOL
–
–
10
%VCC
IOL < 10 µA
Output low voltage
(Open drain LED driver)
VOLL
–
–
0.7
%VCC
IOLL = 10 mA
Output high voltage
VOH
2.4
–
–
V
IOH = 40 µA
VOH
90
–
–
%VCC
IOH < 10 µA
Input low voltage
Input high voltage
Output rise time
CMOS
–
–
3
15
ns
TCLK & RCLK
TTL
–
–
2
15
ns
Output fall time
CMOS
–
–
3
15
ns
TCLK & RCLK
TTL
–
–
2
15
ns
–
–
–
10
ns
CLKI rise time (externally driven)
CLOAD = 20 pF
CLOAD= 20 pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and
3V. This applies to all inputs except TPIP and TPIN.
22
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Table 7.
I/O Electrical Characteristics
Parameter
CLKI duty cycle (externally driven)
Supply current
Sym
Min
Typ1
Max
Units
Test Conditions
–
–
50/50
40/60
%
Normal
ICC
–
40
80
mA
Idle Mode
Mode
ICC
–
70
100
mA
Transmitting on TP
Power Down Mode
ICC
–
0.01
1
µA
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and
3V. This applies to all inputs except TPIP and TPIN.
Table 8.
TP Electrical Characteristics
Parameter
Symbol
Typ1
Min
Max
Units
Test Conditions
ZOUT
–
5
–
Ω
Transmit timing jitter addition2
–
–
±6.4
±10
ns
0 line length for internal MAU
Transmit timing jitter added by the
MAU and PLS sections2, 3
–
–
±3.5
±5.5
ns
After line model specified by IEEE
802.3 for 10BASE-T internal MAU
Receive input impedance
ZIN
–
24
–
kΩ
Between TPIP/TPIN
Differential squelch threshold
VDS
300
420
585
mV
5 MHz square wave input
Transmit output impedance
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 0.5 ns from the encoder, and 3.5 ns from the MAU.
Table 9.
Switching Characteristics
Symbol
Minimum
Typical1
Maximum
Units
Maximum transmit time
–
20
–
150
ms
Unjab time
–
250
–
750
ms
Time link loss receive
–
50
–
150
ms
Link min receive
–
2
–
7
ms
Link max receive
–
50
–
150
ms
Link transmit period
–
8
10
24
ms
Parameter
Jabber Timing
Link Integrity
Timing
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 10. RCLK/Start-of-Frame Timing
Symbol
Min
Typ1
Max
Units
tDATA
–
1300
1500
ns
tCD
–
400
550
ns
Mode 1
tRDS
60
70
–
ns
Modes 2, 3, and 4
tRDS
30
45
–
ns
Parameter
Decoder acquisition time
CD turn-on delay
Receive data setup from RCLK
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Datasheet
23
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Table 10. RCLK/Start-of-Frame Timing
Symbol
Min
Typ1
Max
Units
Mode 1
tRDH
10
20
–
ns
Modes 2, 3, and 4
tRDH
30
45
–
ns
tsws
–
±100
–
ns
Parameter
Receive data hold from RCLK
RCLK shut off delay from CD assert (Mode 3)
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Table 11. RCLK/End-of-Frame Timing
Parameter
Type
Sym
Mode 1
Mode 2
Mode 3
Mode 4
Units
RCLK after CD off
Min
tRC
5
1
–
5
BT
Rcv data through-put delay
Max
tRD
400
375
375
375
ns
tCDOFF
500
475
475
475
ns
CD turn-off delay
2
Max
Receive block out after TEN off
3
RCLK switching delay after CD off
1
tIFG
5
50
–
–
BT
Typical1
tswe
–
–
120 (±80)
–
ns
Typical
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. CD Turnoff delay measured from middle of last bit: timing specification is unaffected by the value of the last bit.
3. Blocking of Carrier Detect is disabled during full duplex operation.
Table 12. Transmit Timing
Parameter
Symbol
Minimum
Typical1
Maximum
Units
TEN setup from TCLK
tEHCH
22
–
–
ns
TXD setup from TCLK
tDSCH
22
–
–
ns
TEN hold after TCLK
tCHEL
5
–
–
ns
TXD hold after TCLK
tCHDU
5
–
–
ns
Transmit start-up delay
tSTUD
–
350
450
ns
Transmit through-put delay
tTPD
–
338
350
ns
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Table 13. Miscellaneous Timing
Parameter
COL (SQE) Delay after TEN off
COL (SQE) Pulse Duration
Power Down recovery time
2
2
Symbol
Minimum
Typical1
Maximum
Units
tSQED
0.65
–
1.6
µs
tSQEP
500
–
1500
ns
tPDR
–
25
–
ms
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. When SQE is enabled (DSQE is Low).
24
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
4.1
Timing Diagrams for Mode 1(MD1 = Low, MD0 = Low)
(Figure 11 through Figure 14)
Figure 11. Mode 1 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
0
1
0
1
1
1
TPIP/TPIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
Datasheet
0
1
0
1
0
1
25
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figure 12. Mode 1 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF
CD
tRD
tRC
RCLK
RXD
1
0
1
0
1
0
1
0
0
Figure 13. Mode 1 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
26
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Figure 14. Mode 1 COL Output Timing
TEN
tSQED
COL
4.2
tSQEP
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
(Figure 15 through Figure 18)
Figure 15. Mode 2 RCLK/Start-of-Frame
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
0
1
0
1
1
1
TPIP/TPIN
CD
tCD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
27
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figure 16. Mode 2 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
CD
tCDOFF
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 17. Mode 2 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
28
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Figure 18. Mode 2 COL Output Timing
tIFG
TEN
tSQED
COL
tSQEP
NOTE:
1. CD output is disabled for a maximum of 55 bit times after TEN turns off.
4.3
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
(Figure 19 through Figure 22)
Figure 19. Mode 3 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
tCD
CD
tSWS
Recovered from Input Data Stream
RCLK
Generated from TCLK
RXD
tRDS
tRDH
tDATA
1
0
1
0
1
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
29
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figure 20. Mode 3 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RSD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 21. Mode 3 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
30
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Figure 22. Mode 3 COL Output Timing
TEN
tSQED
tSQEP
COL
4.4
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
(Figure 23 through Figure 26)
Figure 23. Mode 4 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
tCD
CRS
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Datasheet
31
LXT905 — Universal 10BASE-T Transceiver with 3.3V Support
Figure 24. Mode 4 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
tCDOFF
CD
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.
Figure 25. Mode 4 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tTPD
tSTUD
TPO
32
Datasheet
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Figure 26. Mode 4 COL Output Timing
TEN
tSQED
COL
Datasheet
tSQEP
33
5.0
Mechanical Specifications
Figure 27. LXT905PC Package Specifications
28-Pin PLCC
• Part Number LXT905PC (Commercial Temperature Range)
• Part Number LXT905PE (Extended Temperature Range)
Table 14. PLASTIC LEADED CHIP CARRIER
CL
Inches
Millimeters
Dim
Min
Max
Min
Max
A
0.165
0.180
4.191
4.572
A1
0.090
0.120
2.286
3.048
A2
0.062
0.083
1.575
2.108
B
0.050
–
1.270
–
C
0.026
0.032
0.660
0.813
D
0.485
0.495
12.319
12.573
D1
0.450
0.456
11.430
11.582
F
0.013
0.021
0.330
0.533
C
B
D1
D
D
A2
A
A1
F
Universal 10BASE-T Transceiver with 3.3V Support — LXT905
Figure 28. LXT905LC Package Specifications
32-Pin LQFP
• Part Number LXT905LC (Commercial Temperature Range)
• Part Number LXT905LE (Extended Temperature Range)
D
D1
e
E1 E
e/
2
o
11/13 8 PLACES
o
0 MIN.
0.08/0.20 R.
-H-
A A2
0-7
o
-C-
b
A1
M
All Dimensions in millimeters
Table 15. QUAD FLAT PACKAGE
All Dimensions in millimeters
Dim.
Min.
Max.
A
---
---
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.4
Notes
D
9.00 BSC.
5
D1
7.00 BSC.
6, 7, 8
E
9.00 BSC
5
E1
7.00 BSC
6, 7, 8
L
0.45
M
0.15
---
---
b
0.30
0.37
0.45
e
Datasheet
Typ.
0.60
L
0.20 MIN.
0.08 R. MIN.
1.00 REF.
NOTES:
1. All dimensions are in millimeters.
2. This package conforms to JEDEC publication 95
registration MO-136, variation BC.
3. Datum plane -H- located at mold parting line and is
coincident with leads where leads exit plastic body at
bottom of parting line.
4. Measured at seating plane -C-.
5. Measured at datum plane -H-.
6. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254 mm.
7. Package top dimensions are smaller than bottom
dimensions. Top of package will not overhang bottom of
package.
8. Dimension b does not include dambar protrusion.
Allowable dambar protrusion is no more than 0.08 mm.
0.75
9
0.80 BSC.
35